USE std.textio.all;

ENTITY RegReadWrite_tb IS
END ENTITY RegReadWrite_tb -- no generic/port clause

-- Architecture Body

FILE test_vectors : text OPEN read_mode IS
    "RegReadWrite_vec.txt" -- set of test vectors,

    SIGNAL D : std_ulogic_vector(7 DOWNTO 0); -- these signals are the interface to the DUV
    SIGNAL C, LE, OE : std_ulogic;

    signal vecno : NATURAL := 0; -- which vector I want, (vector number)

    BEGIN
    DUV : ENTITY work.RegReadWrite(Mixed)
    GENERIC MAP(size => 8)
    PORT MAP(D=>D, Q=>Q, C=>C, LE=>LE, OE=>OE);

    -- stimulus process
    Stim : PROCESS
    VARIABLE L : LINE;
    VARIABLE Dval : std_ulogic_vector(7 DOWNTO 0);
    VARIABLE Qval : std_ulogic_vector(7 DOWNTO 0);
    VARIABLE LEval, OEval : std_ulogic;
    BEGIN
    C <= '0'; -- clock
    wait for 40 ns; -- to suspend process, must have sensitivity list or a wait statement
    readline(test_vectors, L); -- read one line of the test_vectors "file", store in LE


    WHILE NOT endfile(test_vectors) LOOP
    readline(test_vectors, L);
    read(L, LEval);
    LE <= Leval;
    read(L, OEval);
    OE <= OEval;
    read(L, Dval);
    D <= Dval;
    read(L, Qval);
    Qv <= Qval;
    wait for 10 ns;
    C <= '1';
    wait for 50 ns;
    C <= '0';
    wait for 40 ns;
    END LOOP;

    report "End of Testbench.";
    std.env.finish;

    END PROCESS;

    Check : PROCESS(C)
    BEGIN
    IF(falling_edge(c)) THEN
    ASSERT Q = Qval
        REPORT "ERROR: Incorrect output for vector " & to_string(vecno)
        SEVERITY WARNING;
    vecno <= vecno + 1;
    END IF
    END PROCESS;

END ARCHITECTURE Testbench;