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  1.  
  2. LIBRARY ieee;
  3. USE ieee.std_logic_1164.ALL;
  4.  
  5. -- Uncomment the following library declaration if using
  6. -- arithmetic functions with Signed or Unsigned values
  7. --USE ieee.numeric_std.ALL;
  8.  
  9. ENTITY mux_7x1_test IS
  10. END mux_7x1_test;
  11.  
  12. ARCHITECTURE behavior OF mux_7x1_test IS
  13.  
  14.     -- Component Declaration for the Unit Under Test (UUT)
  15.  
  16.     COMPONENT mux_7x1
  17.     PORT(
  18.          A : IN  std_logic_vector(3 downto 0);
  19.          B : IN  std_logic_vector(3 downto 0);
  20.          C : IN  std_logic_vector(3 downto 0);
  21.          D : IN  std_logic_vector(3 downto 0);
  22.          E : IN  std_logic_vector(3 downto 0);
  23.          F : IN  std_logic_vector(3 downto 0);
  24.          G : IN  std_logic_vector(3 downto 0);
  25.          Result : OUT  std_logic_vector(3 downto 0);
  26.          Select_Port : IN  std_logic_vector(2 downto 0)
  27.         );
  28.     END COMPONENT;
  29.    
  30.  
  31.    --Inputs
  32.    signal A : std_logic_vector(3 downto 0) := (others => '0');
  33.    signal B : std_logic_vector(3 downto 0) := (others => '0');
  34.    signal C : std_logic_vector(3 downto 0) := (others => '0');
  35.    signal D : std_logic_vector(3 downto 0) := (others => '0');
  36.    signal E : std_logic_vector(3 downto 0) := (others => '0');
  37.    signal F : std_logic_vector(3 downto 0) := (others => '0');
  38.    signal G : std_logic_vector(3 downto 0) := (others => '0');
  39.    signal Select_Port : std_logic_vector(2 downto 0) := (others => '0');
  40.  
  41.      --Outputs
  42.    signal Result : std_logic_vector(3 downto 0);
  43.    -- No clocks detected in port list. Replace <clock> below with
  44.    -- appropriate port name
  45.  
  46. --   constant <clock>_period : time := 10 ns;
  47.  
  48. BEGIN
  49.  
  50.     -- Instantiate the Unit Under Test (UUT)
  51.    uut: mux_7x1 PORT MAP (
  52.           A => A,
  53.           B => B,
  54.           C => C,
  55.           D => D,
  56.           E => E,
  57.           F => F,
  58.           G => G,
  59.           Result => Result,
  60.           Select_Port => Select_Port
  61.         );
  62.  
  63.    -- Clock process definitions
  64. --  <clock>_process :process
  65. --   begin
  66. --        <clock> <= '0';
  67. --        wait for <clock>_period/2;
  68. --        <clock> <= '1';
  69. --        wait for <clock>_period/2;
  70. --   end process;
  71.  
  72.  
  73.    -- Stimulus process
  74.    stim_proc: process
  75.    begin    
  76.     Select_Port <= "001";
  77.     wait for 50 ns;
  78.     A <= "0001";
  79.     wait for 50 ns;
  80.     Select_Port <= "010";
  81.     wait for 50 ns;
  82.     B <= "0010";
  83.     wait for 50 ns;
  84.     Select_Port <= "011";
  85.     wait for 50 ns;
  86.     C <= "0011";
  87.     wait for 50 ns;
  88.     Select_Port <= "100";
  89.     wait for 50 ns;
  90.     D <= "0100";
  91.     wait for 50 ns;
  92.     Select_Port <= "101";
  93.     wait for 50 ns;
  94.     E <= "0101";
  95.     wait for 50 ns;
  96.     Select_Port <= "110";
  97.     wait for 50 ns;
  98.     F <= "0110";
  99.     wait for 50 ns;
  100.     Select_Port <= "111";
  101.     wait for 50 ns;
  102.     G <= "0111";
  103.     wait for 50 ns;
  104.     Select_Port <= "000";
  105.     wait for 300 ns;
  106.    end process;
  107.  
  108. END;
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