library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity counter is
    generic(
    N:integer:=4
    );
     port(
         sum : in STD_LOGIC;
         dec : in STD_LOGIC;
         inp : in STD_LOGIC;
         zero : in STD_LOGIC;
         q: out std_logic_vector(N downto 1)
         );
end counter;

--}} End of automatically maintained section

architecture counter of counter is
component jktrigger
    port(
         nsa : in STD_LOGIC;
         J : in STD_LOGIC;
         C : in STD_LOGIC;
         K : in STD_LOGIC;
         nra : in STD_LOGIC;
         Q : out STD_LOGIC;
         nQ : out STD_LOGIC
         );
end component jktrigger;
component and_and_or
     port(
         x1 : in STD_LOGIC;
         x2 : in STD_LOGIC;
         x3 : in STD_LOGIC;
         x4 : in STD_LOGIC;
         o : out STD_LOGIC
         );
end component and_and_or;
signal or2_in: Std_logic_vector(1 to N);
signal q_in, nq_in: Std_logic_vector(1 to N+1);
signal ra:std_logic;
begin
    q_in(1) <= inp;
    nq_in(1) <= not inp;
    ra <= not zero;
    trigs: for i in 1 to N generate
        jktrigger: jktrigger port map('1', '1', or2_in(i), '1', ra, q_in(i+1), nq_in(i+1));
        or_n: and_and_or port map(sum, q_in(i), dec, nq_in(i), or2_in(i));
        q(i) <= q_in(i+1);
    end generate;
     -- enter your statements here --

end counter;