VHDL BMSTU HW

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY control_unit IS
   PORT( U : IN std_logic_vector ( 5 DOWNTO 0 );
   clk : IN std_logic;
   rst : IN std_logic;
   V : OUT std_logic_vector ( 7 DOWNTO 0 ) );
END control_unit;

ARCHITECTURE moore OF control_unit IS
TYPE STATE_TYPE IS (s1,s2,s3,s4,s5,s6);
SIGNAL current_state : STATE_TYPE;
BEGIN
   clocked_proc : PROCESS (clk, rst)
   BEGIN
      IF (rst = '0') THEN
         current_state <= s1;
      ELSIF (clk'EVENT AND clk = '1') THEN
         CASE current_state IS
            WHEN s1 =>
               V <= (others => '0');
               IF (U(0) = '1' AND U(3) = '1' AND U(4) = '0') THEN
                  current_state <= s2;
               ELSIF (U(0) = '1' AND U(2) = '0') THEN
                  current_state <= s4;
               ELSE
                  current_state <= s1;
               END IF;
            WHEN s2 =>
               V <= "00000101";
               IF (U(2) = '1' OR U(4) = '1' THEN
                  current_state <= s3;
               ELSE
                  current_state <= s2;
               END IF;
            WHEN s3 =>
               V <= "10000000";
               IF (U(0) = '1' AND U(1) = '1' THEN
                  current_state <= s1;
               ELSE
                  current_state <= s3;
               END IF;
            WHEN s4 =>
               V <= "00001010";
               IF (U(0) = '1' AND U(5) = '0') THEN
                  current_state <= s3;
               ELSIF (U(1) = '1') THEN
                  current_state <= s5;
               ELSE
                  current_state <= s4;
               END IF;
            WHEN s5 =>
               V <= "00110000";
               IF (U(0) = '0' OR U(2) = '1') THEN
                  current_state <= s6;
               ELSE
                  current_state <= s5;
               END IF;
            WHEN s6 =>
               V <= (6 => '1', others => '0');
               IF (U(0) = '1' OR U(5) = '1') THEN
                  current_state <= s1;
               ELSE
                  current_state <= s6;
               END IF;
            WHEN OTHERS =>
               current_state <= s0;
         END CASE;
      END IF;
   END PROCESS clocked_proc;
END moore;