VHDL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;



-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;



ENTITY TB IS

END TB;



ARCHITECTURE behavior OF TB IS



    -- Component Declaration for the Unit Under Test (UUT)



    COMPONENT Beep

    PORT(

         E : IN  std_logic;

         Clk : IN  std_logic;

         Start : OUT  std_logic;

         Addr : OUT  std_logic_vector(3 downto 0);

         Cmd : OUT  std_logic_vector(3 downto 0);

         DATA : OUT  std_logic_vector(11 downto 0)

        );

    END COMPONENT;





   --Inputs

   signal E : std_logic := '1';

   signal Clk : std_logic := '0';



    --Outputs

   signal Start : std_logic;

   signal Addr : std_logic_vector(3 downto 0);

   signal Cmd : std_logic_vector(3 downto 0);

   signal DATA : std_logic_vector(11 downto 0);





BEGIN



    -- Instantiate the Unit Under Test (UUT)

   uut: Beep PORT MAP (

          E => E,

          Clk => Clk,

          Start => Start,

          Addr => Addr,

          Cmd => Cmd,

          DATA => DATA

        );



Clk<=not Clk after 20ns;



END;