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RS232_beta2

Vedro May 25th, 2019 62 Never
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.numeric_std.all;
  4.  
  5. entity RS_kod is
  6.     Port ( clk_i : in  STD_LOGIC;
  7.            rst_i : in  STD_LOGIC;
  8.            RXD_i : in  STD_LOGIC;
  9.            TXD_o : out  STD_LOGIC);
  10. end RS_kod;
  11.  
  12. architecture Behavioral of RS_kod is
  13. component Dzielnik_kod 
  14.     generic(N : integer := 5208);                               -- tak właściwie to powinno być 5208.(3) ale to nielegalne  
  15.     Port ( CLK : in  STD_LOGIC;
  16.              RST : in  STD_LOGIC;          
  17.              LED : out  STD_LOGIC);
  18. end component;
  19. component F_edge_detector
  20.     Port ( clk_i      : in  std_logic;
  21.              sygnal_i  : in  std_logic;
  22.              pulse_o    : out std_logic);
  23. end component;         
  24.  
  25. signal CLK_DIV : std_logic;
  26. signal R_EDGE : std_logic := '0';
  27. signal NASLUCH : std_logic := '1';
  28. signal BUFOR : std_logic_vector (9 downto 0) := (others => '1');
  29. signal DANE : std_logic_vector (9 downto 0) := (others => '1');
  30. --signal HEX : std_logic_vector (7 downto 0) := (others => '1');
  31. signal i : integer range 0 to 10 := 0;
  32. signal j : integer range 0 to 10 := 0;                                                 
  33.  
  34. begin
  35.     ET1: Dzielnik_kod port map (CLK => CLK_i, RST => RST_i, LED => CLK_DIV);
  36.     ET2: F_edge_detector port map (clk_i => clk_i, sygnal_i => ClK_DIV, pulse_o => R_EDGE);
  37.    
  38.     DANE(0) <= '0';
  39.     DANE(9) <= '1';
  40. --  HEX <= "0010 0000";                                            
  41.     Zapis: process (clk_i, rst_i) is
  42.     begin
  43.         if (rst_i = '1') then
  44.             NASLUCH <= '1';
  45.             BUFOR <= "1111111111";
  46.             DANE(8 downto 1) <= "11111111";
  47.         elsif rising_edge(clk_i) then
  48.             if NASLUCH = '1' then
  49.                 if RXD_i = '0' then
  50.                     NASLUCH <= '0';
  51.                 end if;
  52.             else
  53.                 if i = 9 then
  54.                    
  55.                 end if;
  56.                 if i = 10 then
  57.                     i <= 0;
  58.                     DANE(8 downto 1) <= std_logic_vector(unsigned(BUFOR(8 downto 1)) + x"20");
  59. --                  DANE(8 downto 1) <= BUFOR(8 downto 1) + x"20";
  60.                 elsif R_EDGE = '1' then
  61.                     BUFOR(i) <= RXD_i;
  62.                     i <= i + 1;
  63.                 end if;
  64.             end if;
  65.         end if;
  66.     end process Zapis;
  67.    
  68.     Wyslanie: process(clk_i) is
  69.     begin
  70.         if rising_edge(clk_i) then
  71.             if DANE /= "1111111111" then
  72.                 if j = 10 then
  73.                     j <= 0;
  74.                 elsif R_EDGE = '1' then
  75.                     TXD_O <= DANE(j);
  76.                 end if;
  77.             end if;
  78.         end if;
  79.     end process Wyslanie;
  80.            
  81. end Behavioral;
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