RS232_beta2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity RS_kod is
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           RXD_i : in  STD_LOGIC;
           TXD_o : out  STD_LOGIC);
end RS_kod;

architecture Behavioral of RS_kod is
component Dzielnik_kod
    generic(N : integer := 5208);                               -- tak właściwie to powinno być 5208.(3) ale to nielegalne
    Port ( CLK : in  STD_LOGIC;
             RST : in  STD_LOGIC;
             LED : out  STD_LOGIC);
end component;
component F_edge_detector
    Port ( clk_i      : in  std_logic;
             sygnal_i  : in  std_logic;
             pulse_o    : out std_logic);
end component;

signal CLK_DIV : std_logic;
signal R_EDGE : std_logic := '0';
signal NASLUCH : std_logic := '1';
signal BUFOR : std_logic_vector (9 downto 0) := (others => '1');
signal DANE : std_logic_vector (9 downto 0) := (others => '1');
--signal HEX : std_logic_vector (7 downto 0) := (others => '1');
signal i : integer range 0 to 10 := 0;
signal j : integer range 0 to 10 := 0;

begin
    ET1: Dzielnik_kod port map (CLK => CLK_i, RST => RST_i, LED => CLK_DIV);
    ET2: F_edge_detector port map (clk_i => clk_i, sygnal_i => ClK_DIV, pulse_o => R_EDGE);

    DANE(0) <= '0';
    DANE(9) <= '1';
--  HEX <= "0010 0000";
    Zapis: process (clk_i, rst_i) is
    begin
        if (rst_i = '1') then
            NASLUCH <= '1';
            BUFOR <= "1111111111";
            DANE(8 downto 1) <= "11111111";
        elsif rising_edge(clk_i) then
            if NASLUCH = '1' then
                if RXD_i = '0' then
                    NASLUCH <= '0';
                end if;
            else
                if i = 9 then

                end if;
                if i = 10 then
                    i <= 0;
                    DANE(8 downto 1) <= std_logic_vector(unsigned(BUFOR(8 downto 1)) + x"20");
--                  DANE(8 downto 1) <= BUFOR(8 downto 1) + x"20";
                elsif R_EDGE = '1' then
                    BUFOR(i) <= RXD_i;
                    i <= i + 1;
                end if;
            end if;
        end if;
    end process Zapis;

    Wyslanie: process(clk_i) is
    begin
        if rising_edge(clk_i) then
            if DANE /= "1111111111" then
                if j = 10 then
                    j <= 0;
                elsif R_EDGE = '1' then
                    TXD_O <= DANE(j);
                end if;
            end if;
        end if;
    end process Wyslanie;

end Behavioral;