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-- SystemTop.vhd
-- Top-Level des Kernsystems (einige Hilfsmodule sind in Basys2Top instanziert)
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library ieee;
use ieee.std_logic_1164.all;

entity SystemTop is
  port (
        btn         : in  std_ulogic_vector (2 downto 0);   -- Taster 1,2,3 des Boards (Taster 0 ist der Resettaster)
        sw          : in  std_ulogic_vector (7 downto 0);   -- Schalter des Boards
        ps2code     : in  std_ulogic_vector (15 downto 0);  -- PS2 Code von Tastatur

        seg0        : out std_ulogic_vector (6 downto 0);   -- Siebensegmentanzeige 0 (= rechts)
        dp0         : out std_ulogic;                       -- Dezimalpunkt 0
        seg1        : out std_ulogic_vector (6 downto 0);   -- Siebensegmentanzeige 1
        dp1         : out std_ulogic;                       -- Dezimalpunkt 1
        seg2        : out std_ulogic_vector (6 downto 0);   -- Siebensegmentanzeige 2
        dp2         : out std_ulogic;                       -- Dezimalpunkt 2
        seg3        : out std_ulogic_vector (6 downto 0);   -- Siebensegmentanzeige 3 (= links)
        dp3         : out std_ulogic;                       -- Dezimalpunkt 3

        led         : out std_ulogic_vector (7 downto 0)    -- 8 LEDs (1 = an)
    );
end;

architecture rtl of SystemTop is

-- >>>>>>>>>>  Hier: Ihr Code   <<<<<<<<<<<<
      component SevenSegDecoder
         port(dpin        : in std_ulogic;
              hexval      : in std_ulogic_vector (4 downto 0);
              segout      : out std_ulogic_vector (6 downto 0);
              dpout       : out std_ulogic
              );
      end component;

      begin
        comp0 : SevenSegDecoder
            port map (,seq0,dp0);

        comp1 : SevenSegDecoder
            port map (,seq1,dp1);

        comp2 : SevenSegDecoder
            port map (,seq2,dp2);

        comp3 : SevenSegDecoder
            port map (,seq3,dp3);

end rtl;