afisor_entity

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity asta is
    port(clok : in std_logic;
         unitati_BCD: in std_logic_vector(3 downto 0);
         zeci_BCD: in std_logic_vector(3 downto 0);
         anod:out std_logic_vector(3 downto 0);
         catod:out std_logic_vector(6 downto 0));

end asta;

architecture asta1 of afisor is
signal clk_div1: std_logic;

component div_frec is
    port(clk:in std_logic;
        --clk_div:out std_logic;
        clk_div_afis:out std_logic);
end component;

component afisor is
    port(--clkb:in std_logic;
         clk_div1: in std_logic;
         unitati_BCD: in std_logic_vector(3 downto 0);
         zeci_BCD: in std_logic_vector(3 downto 0);
         anod:out std_logic_vector(3 downto 0);
         catod:out std_logic_vector(6 downto 0));

end component;
begin

    C1: div_frec port map(clok, clk_div1);
    C2: afisor port map(clk_div1,unitati_bcd, zeci_bcd,anod,catod);
end architecture asta1;