[SEM6][ISP]Lab1.vhd

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-- Company:
-- Engineer:
--
-- Create Date:    10:41:00 03/03/2015
-- Design Name:
-- Module Name:    top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( pb_i : in  STD_LOGIC;
           sw_i : in  STD_LOGIC_VECTOR (7 downto 0);
              led7_an_o : out STD_LOGIC_VECTOR (3 downto 0);
              led7_seg_o : out STD_LOGIC_VECTOR (7 downto 0);
              led_o : out STD_LOGIC_VECTOR (7 downto 0));
end top;

architecture Behavioral of top is

signal x : std_logic_vector (3 downto 0);
signal y : std_logic_vector (1 downto 0);
signal is_odd : std_logic;

begin
x <= sw_i(7 downto 4) xor sw_i(3 downto 0);
y <= x(3 downto 2) xor x(1 downto 0);
is_odd <= y(1) xor y(0);


led7_an_o <= "1110";
led7_seg_o <= "01100001" when is_odd = '0' else "00000011";

led_o <= "00000000" when pb_i = '1' else "00000000";

end Behavioral;