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-- Company:
-- Engineer:
--
-- Create Date:    12:00:01 05/01/2018
-- Design Name:
-- Module Name:    pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pwm is
    Port ( clk : in  STD_LOGIC;
           ref_A : in  STD_LOGIC_VECTOR (7 downto 0);
           ref_B : in  STD_LOGIC_VECTOR (7 downto 0);
           dir_A : in  STD_LOGIC;
           dir_B : in  STD_LOGIC;
           A1 : out  STD_LOGIC;
           A2 : out  STD_LOGIC;
           B1 : out  STD_LOGIC;
           B2 : out  STD_LOGIC);
end pwm;

architecture Behavioral of pwm is

signal counter : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal A : STD_LOGIC := '0';
signal B : STD_LOGIC := '0';

begin
    process(clk)
    begin
        if clk='1' and clk'event then
            counter <= counter + 1;
            if counter > ref_A then
                A <= '0';
            else
                A <= '1';
            end if;
            if counter > ref_B then
                B <= '0';
            else
                B <= '1';
            end if;
        end if;
    end process;

    B1 <= B AND dir_B;
    B2 <= B AND NOT dir_B;
    A1 <= A AND dir_A;
    A2 <= A AND NOT dir_A;

end Behavioral;