CN LAB 5

//mux_4x1.v

/*
 * Do not change Module name
*/
`timescale 1ns / 1ps

module Mux(Input0, Input1, Input2, Input3, Sel, Data_out);

    input [3:0] Input0;
    input [3:0] Input1;
    input [3:0] Input2;
    input [3:0] Input3;
    input [2:0] Sel;
    output [3:0] Data_out;
    reg [3:0] Data_out;

    //constant declaration
    parameter S0 = 2'b00;
    parameter S1 = 2'b01;
    parameter S2 = 2'b10;
    parameter S3 = 2'b11;

    always @ (Sel or Input0 or Input1 or Input2 or Input3)
    begin
    case (Sel)
        S0: begin
            Data_out <= Input0;
            end
        S1: begin
            Data_out <= Input1;
            end
        S2: begin
            Data_out <= Input2;
            end
        S3: begin
            Data_out <= Input3;
            end
        endcase
    end
endmodule

module Testbench;

    reg [3:0] Input0_t, Input1_t, Input2_t, Input3_t;
    reg [2:0] Sel_t;
    wire [3:0] Dat_out_t;

    Mux Mux_1(Input0_t, Input1_t, Input2_t, Input3_t, Sel_t, Data_out_t);

    initial
    begin

        //asign values to input register
        Input0_t <= 0;
        Input1_t <= 1;
        Input2_t <= 2;
        Input3_t <= 3;

        //case 0 - Input0 value should be display on output
        Sel_t <= 0;
        #1 $display("Data_out_t = %b", Data_out_t);

        //case 1 - Input1 ... analog
        Sel_t <= 1;
        #1 $display("Data_out_t = %b", Data_out_t);

         Sel_t <= 2;
        #1 $display("Data_out_t = %b", Data_out_t);

         Sel_t <= 3;
        #1 $display("Data_out_t = %b", Data_out_t);

         Input0_t = 8;
         Sel_t <= 0;
        #1 $display("Data_out_t = %b", Data_out_t);

        Input0_t = 4;
        Sel_t <= 0;
        #1 $display("Data_out_t = %b", Data_out_t);

    end
endmodule

//task_parity
module tasks;

task parity;
    input [3:0] x;
    output z;
    z = ^x;
endtask

initial
    begin: init1
        reg r;
        parity(4'b0110,r); //invocare task: 1011, 1111
        $display("p = %b",r);
    end

endmodule

//task_factorial.v

module fact;

task factorial;
    input [3:0] n;
    output [31:0] outfact;
    integer count;
    begin
        outfact = 1;
        for (count = n; count > 0; count = count - 1)
            outfact = outfact * count;
    end
endtask

initial
    begin: init1
        reg [3:0] n;
        reg [31:0] result;
        n = 4'b0111;
        factorial(n, result);
        $display("n = %d fact = %d", n , result);
    end

endmodule

//task_factorial2.v
module fact;

task factorial;
    input [4:0] n;
    output [31:0] outfact;
    integer count;
    begin
        outfact = 1;
        for (count = n; count > 0; count = count - 1)
            outfact = outfact * count;
    end
endtask

initial
    begin: init1
        reg [4:0] n;
        reg [31:0] result;
        n = 5'b10100;
        factorial(n, result);
        $display("n = %d fact = %d", n , result);
    end

endmodule