API tools faq
paste
unkwntech

iostm8s105c6.h

unkwntech
May 11th, 2012
1,270
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
C 155.52 KB | None | 0 0
raw download clone embed print report
  1. /*-------------------------------------------------------------------------
  2.  *      STM8 definitions of SFR registers
  3.  *
  4.  *      Used with STM8 IAR C/C++ Compiler and Assembler.
  5.  *
  6.  *      Copyright 2010 IAR Systems AB.
  7.  *
  8.  *-----------------------------------------------------------------------*/
  9.  
  10. #ifndef __IOSTM8S105C6_H__
  11. #define __IOSTM8S105C6_H__
  12.  
  13. #if (((__TID__ >> 8) & 0x7F) != 0x38)     /* 0x38 = 56 dec */
  14. #error This file should only be compiled by STM8 IAR compiler and assembler
  15. #endif
  16.  
  17. /*-------------------------------------------------------------------------
  18.  *      I/O register macros
  19.  *-----------------------------------------------------------------------*/
  20.  
  21. #include "io_macros.h"
  22.  
  23.  
  24. #ifdef __IAR_SYSTEMS_ICC__
  25. #pragma system_include
  26. #pragma language=save
  27. #pragma language=extended
  28. #endif
  29.  
  30. /*-------------------------------------------------------------------------
  31.  *      Port A register definitions
  32.  *-----------------------------------------------------------------------*/
  33. /* Port A data output latch register */
  34. #ifdef __IAR_SYSTEMS_ICC__
  35. typedef struct
  36. {
  37.   unsigned char ODR0        : 1;
  38.   unsigned char ODR1        : 1;
  39.   unsigned char ODR2        : 1;
  40.   unsigned char ODR3        : 1;
  41.   unsigned char ODR4        : 1;
  42.   unsigned char ODR5        : 1;
  43.   unsigned char ODR6        : 1;
  44.   unsigned char ODR7        : 1;
  45. } __BITS_PA_ODR;
  46. #endif
  47. __IO_REG8_BIT(PA_ODR,      0x5000, __READ_WRITE, __BITS_PA_ODR);
  48.  
  49. /* Port A input pin value register */
  50. #ifdef __IAR_SYSTEMS_ICC__
  51. typedef struct
  52. {
  53.   unsigned char IDR0        : 1;
  54.   unsigned char IDR1        : 1;
  55.   unsigned char IDR2        : 1;
  56.   unsigned char IDR3        : 1;
  57.   unsigned char IDR4        : 1;
  58.   unsigned char IDR5        : 1;
  59.   unsigned char IDR6        : 1;
  60.   unsigned char IDR7        : 1;
  61. } __BITS_PA_IDR;
  62. #endif
  63. __IO_REG8_BIT(PA_IDR,      0x5001, __READ, __BITS_PA_IDR);
  64.  
  65. /* Port A data direction register */
  66. #ifdef __IAR_SYSTEMS_ICC__
  67. typedef struct
  68. {
  69.   unsigned char DDR0        : 1;
  70.   unsigned char DDR1        : 1;
  71.   unsigned char DDR2        : 1;
  72.   unsigned char DDR3        : 1;
  73.   unsigned char DDR4        : 1;
  74.   unsigned char DDR5        : 1;
  75.   unsigned char DDR6        : 1;
  76.   unsigned char DDR7        : 1;
  77. } __BITS_PA_DDR;
  78. #endif
  79. __IO_REG8_BIT(PA_DDR,      0x5002, __READ_WRITE, __BITS_PA_DDR);
  80.  
  81. /* Port A control register 1 */
  82. #ifdef __IAR_SYSTEMS_ICC__
  83. typedef struct
  84. {
  85.   unsigned char C10         : 1;
  86.   unsigned char C11         : 1;
  87.   unsigned char C12         : 1;
  88.   unsigned char C13         : 1;
  89.   unsigned char C14         : 1;
  90.   unsigned char C15         : 1;
  91.   unsigned char C16         : 1;
  92.   unsigned char C17         : 1;
  93. } __BITS_PA_CR1;
  94. #endif
  95. __IO_REG8_BIT(PA_CR1,      0x5003, __READ_WRITE, __BITS_PA_CR1);
  96.  
  97. /* Port A control register 2 */
  98. #ifdef __IAR_SYSTEMS_ICC__
  99. typedef struct
  100. {
  101.   unsigned char C20         : 1;
  102.   unsigned char C21         : 1;
  103.   unsigned char C22         : 1;
  104.   unsigned char C23         : 1;
  105.   unsigned char C24         : 1;
  106.   unsigned char C25         : 1;
  107.   unsigned char C26         : 1;
  108.   unsigned char C27         : 1;
  109. } __BITS_PA_CR2;
  110. #endif
  111. __IO_REG8_BIT(PA_CR2,      0x5004, __READ_WRITE, __BITS_PA_CR2);
  112.  
  113.  
  114. /*-------------------------------------------------------------------------
  115.  *      Port A bit fields
  116.  *-----------------------------------------------------------------------*/
  117. #ifdef __IAR_SYSTEMS_ICC__
  118.  
  119. #define PA_ODR_ODR0              PA_ODR_bit.ODR0
  120. #define PA_ODR_ODR1              PA_ODR_bit.ODR1
  121. #define PA_ODR_ODR2              PA_ODR_bit.ODR2
  122. #define PA_ODR_ODR3              PA_ODR_bit.ODR3
  123. #define PA_ODR_ODR4              PA_ODR_bit.ODR4
  124. #define PA_ODR_ODR5              PA_ODR_bit.ODR5
  125. #define PA_ODR_ODR6              PA_ODR_bit.ODR6
  126. #define PA_ODR_ODR7              PA_ODR_bit.ODR7
  127.  
  128. #define PA_IDR_IDR0              PA_IDR_bit.IDR0
  129. #define PA_IDR_IDR1              PA_IDR_bit.IDR1
  130. #define PA_IDR_IDR2              PA_IDR_bit.IDR2
  131. #define PA_IDR_IDR3              PA_IDR_bit.IDR3
  132. #define PA_IDR_IDR4              PA_IDR_bit.IDR4
  133. #define PA_IDR_IDR5              PA_IDR_bit.IDR5
  134. #define PA_IDR_IDR6              PA_IDR_bit.IDR6
  135. #define PA_IDR_IDR7              PA_IDR_bit.IDR7
  136.  
  137. #define PA_DDR_DDR0              PA_DDR_bit.DDR0
  138. #define PA_DDR_DDR1              PA_DDR_bit.DDR1
  139. #define PA_DDR_DDR2              PA_DDR_bit.DDR2
  140. #define PA_DDR_DDR3              PA_DDR_bit.DDR3
  141. #define PA_DDR_DDR4              PA_DDR_bit.DDR4
  142. #define PA_DDR_DDR5              PA_DDR_bit.DDR5
  143. #define PA_DDR_DDR6              PA_DDR_bit.DDR6
  144. #define PA_DDR_DDR7              PA_DDR_bit.DDR7
  145.  
  146. #define PA_CR1_C10               PA_CR1_bit.C10
  147. #define PA_CR1_C11               PA_CR1_bit.C11
  148. #define PA_CR1_C12               PA_CR1_bit.C12
  149. #define PA_CR1_C13               PA_CR1_bit.C13
  150. #define PA_CR1_C14               PA_CR1_bit.C14
  151. #define PA_CR1_C15               PA_CR1_bit.C15
  152. #define PA_CR1_C16               PA_CR1_bit.C16
  153. #define PA_CR1_C17               PA_CR1_bit.C17
  154.  
  155. #define PA_CR2_C20               PA_CR2_bit.C20
  156. #define PA_CR2_C21               PA_CR2_bit.C21
  157. #define PA_CR2_C22               PA_CR2_bit.C22
  158. #define PA_CR2_C23               PA_CR2_bit.C23
  159. #define PA_CR2_C24               PA_CR2_bit.C24
  160. #define PA_CR2_C25               PA_CR2_bit.C25
  161. #define PA_CR2_C26               PA_CR2_bit.C26
  162. #define PA_CR2_C27               PA_CR2_bit.C27
  163.  
  164. #endif
  165.  
  166. /*-------------------------------------------------------------------------
  167.  *      Port A bit masks
  168.  *-----------------------------------------------------------------------*/
  169. #define MASK_PA_ODR_ODR0         0x01
  170. #define MASK_PA_ODR_ODR1         0x02
  171. #define MASK_PA_ODR_ODR2         0x04
  172. #define MASK_PA_ODR_ODR3         0x08
  173. #define MASK_PA_ODR_ODR4         0x10
  174. #define MASK_PA_ODR_ODR5         0x20
  175. #define MASK_PA_ODR_ODR6         0x40
  176. #define MASK_PA_ODR_ODR7         0x80
  177.  
  178. #define MASK_PA_IDR_IDR0         0x01
  179. #define MASK_PA_IDR_IDR1         0x02
  180. #define MASK_PA_IDR_IDR2         0x04
  181. #define MASK_PA_IDR_IDR3         0x08
  182. #define MASK_PA_IDR_IDR4         0x10
  183. #define MASK_PA_IDR_IDR5         0x20
  184. #define MASK_PA_IDR_IDR6         0x40
  185. #define MASK_PA_IDR_IDR7         0x80
  186.  
  187. #define MASK_PA_DDR_DDR0         0x01
  188. #define MASK_PA_DDR_DDR1         0x02
  189. #define MASK_PA_DDR_DDR2         0x04
  190. #define MASK_PA_DDR_DDR3         0x08
  191. #define MASK_PA_DDR_DDR4         0x10
  192. #define MASK_PA_DDR_DDR5         0x20
  193. #define MASK_PA_DDR_DDR6         0x40
  194. #define MASK_PA_DDR_DDR7         0x80
  195.  
  196. #define MASK_PA_CR1_C10          0x01
  197. #define MASK_PA_CR1_C11          0x02
  198. #define MASK_PA_CR1_C12          0x04
  199. #define MASK_PA_CR1_C13          0x08
  200. #define MASK_PA_CR1_C14          0x10
  201. #define MASK_PA_CR1_C15          0x20
  202. #define MASK_PA_CR1_C16          0x40
  203. #define MASK_PA_CR1_C17          0x80
  204.  
  205. #define MASK_PA_CR2_C20          0x01
  206. #define MASK_PA_CR2_C21          0x02
  207. #define MASK_PA_CR2_C22          0x04
  208. #define MASK_PA_CR2_C23          0x08
  209. #define MASK_PA_CR2_C24          0x10
  210. #define MASK_PA_CR2_C25          0x20
  211. #define MASK_PA_CR2_C26          0x40
  212. #define MASK_PA_CR2_C27          0x80
  213.  
  214.  
  215. /*-------------------------------------------------------------------------
  216.  *      Port B register definitions
  217.  *-----------------------------------------------------------------------*/
  218. /* Port B data output latch register */
  219. #ifdef __IAR_SYSTEMS_ICC__
  220. typedef struct
  221. {
  222.   unsigned char ODR0        : 1;
  223.   unsigned char ODR1        : 1;
  224.   unsigned char ODR2        : 1;
  225.   unsigned char ODR3        : 1;
  226.   unsigned char ODR4        : 1;
  227.   unsigned char ODR5        : 1;
  228.   unsigned char ODR6        : 1;
  229.   unsigned char ODR7        : 1;
  230. } __BITS_PB_ODR;
  231. #endif
  232. __IO_REG8_BIT(PB_ODR,      0x5005, __READ_WRITE, __BITS_PB_ODR);
  233.  
  234. /* Port B input pin value register */
  235. #ifdef __IAR_SYSTEMS_ICC__
  236. typedef struct
  237. {
  238.   unsigned char IDR0        : 1;
  239.   unsigned char IDR1        : 1;
  240.   unsigned char IDR2        : 1;
  241.   unsigned char IDR3        : 1;
  242.   unsigned char IDR4        : 1;
  243.   unsigned char IDR5        : 1;
  244.   unsigned char IDR6        : 1;
  245.   unsigned char IDR7        : 1;
  246. } __BITS_PB_IDR;
  247. #endif
  248. __IO_REG8_BIT(PB_IDR,      0x5006, __READ, __BITS_PB_IDR);
  249.  
  250. /* Port B data direction register */
  251. #ifdef __IAR_SYSTEMS_ICC__
  252. typedef struct
  253. {
  254.   unsigned char DDR0        : 1;
  255.   unsigned char DDR1        : 1;
  256.   unsigned char DDR2        : 1;
  257.   unsigned char DDR3        : 1;
  258.   unsigned char DDR4        : 1;
  259.   unsigned char DDR5        : 1;
  260.   unsigned char DDR6        : 1;
  261.   unsigned char DDR7        : 1;
  262. } __BITS_PB_DDR;
  263. #endif
  264. __IO_REG8_BIT(PB_DDR,      0x5007, __READ_WRITE, __BITS_PB_DDR);
  265.  
  266. /* Port B control register 1 */
  267. #ifdef __IAR_SYSTEMS_ICC__
  268. typedef struct
  269. {
  270.   unsigned char C10         : 1;
  271.   unsigned char C11         : 1;
  272.   unsigned char C12         : 1;
  273.   unsigned char C13         : 1;
  274.   unsigned char C14         : 1;
  275.   unsigned char C15         : 1;
  276.   unsigned char C16         : 1;
  277.   unsigned char C17         : 1;
  278. } __BITS_PB_CR1;
  279. #endif
  280. __IO_REG8_BIT(PB_CR1,      0x5008, __READ_WRITE, __BITS_PB_CR1);
  281.  
  282. /* Port B control register 2 */
  283. #ifdef __IAR_SYSTEMS_ICC__
  284. typedef struct
  285. {
  286.   unsigned char C20         : 1;
  287.   unsigned char C21         : 1;
  288.   unsigned char C22         : 1;
  289.   unsigned char C23         : 1;
  290.   unsigned char C24         : 1;
  291.   unsigned char C25         : 1;
  292.   unsigned char C26         : 1;
  293.   unsigned char C27         : 1;
  294. } __BITS_PB_CR2;
  295. #endif
  296. __IO_REG8_BIT(PB_CR2,      0x5009, __READ_WRITE, __BITS_PB_CR2);
  297.  
  298.  
  299. /*-------------------------------------------------------------------------
  300.  *      Port B bit fields
  301.  *-----------------------------------------------------------------------*/
  302. #ifdef __IAR_SYSTEMS_ICC__
  303.  
  304. #define PB_ODR_ODR0              PB_ODR_bit.ODR0
  305. #define PB_ODR_ODR1              PB_ODR_bit.ODR1
  306. #define PB_ODR_ODR2              PB_ODR_bit.ODR2
  307. #define PB_ODR_ODR3              PB_ODR_bit.ODR3
  308. #define PB_ODR_ODR4              PB_ODR_bit.ODR4
  309. #define PB_ODR_ODR5              PB_ODR_bit.ODR5
  310. #define PB_ODR_ODR6              PB_ODR_bit.ODR6
  311. #define PB_ODR_ODR7              PB_ODR_bit.ODR7
  312.  
  313. #define PB_IDR_IDR0              PB_IDR_bit.IDR0
  314. #define PB_IDR_IDR1              PB_IDR_bit.IDR1
  315. #define PB_IDR_IDR2              PB_IDR_bit.IDR2
  316. #define PB_IDR_IDR3              PB_IDR_bit.IDR3
  317. #define PB_IDR_IDR4              PB_IDR_bit.IDR4
  318. #define PB_IDR_IDR5              PB_IDR_bit.IDR5
  319. #define PB_IDR_IDR6              PB_IDR_bit.IDR6
  320. #define PB_IDR_IDR7              PB_IDR_bit.IDR7
  321.  
  322. #define PB_DDR_DDR0              PB_DDR_bit.DDR0
  323. #define PB_DDR_DDR1              PB_DDR_bit.DDR1
  324. #define PB_DDR_DDR2              PB_DDR_bit.DDR2
  325. #define PB_DDR_DDR3              PB_DDR_bit.DDR3
  326. #define PB_DDR_DDR4              PB_DDR_bit.DDR4
  327. #define PB_DDR_DDR5              PB_DDR_bit.DDR5
  328. #define PB_DDR_DDR6              PB_DDR_bit.DDR6
  329. #define PB_DDR_DDR7              PB_DDR_bit.DDR7
  330.  
  331. #define PB_CR1_C10               PB_CR1_bit.C10
  332. #define PB_CR1_C11               PB_CR1_bit.C11
  333. #define PB_CR1_C12               PB_CR1_bit.C12
  334. #define PB_CR1_C13               PB_CR1_bit.C13
  335. #define PB_CR1_C14               PB_CR1_bit.C14
  336. #define PB_CR1_C15               PB_CR1_bit.C15
  337. #define PB_CR1_C16               PB_CR1_bit.C16
  338. #define PB_CR1_C17               PB_CR1_bit.C17
  339.  
  340. #define PB_CR2_C20               PB_CR2_bit.C20
  341. #define PB_CR2_C21               PB_CR2_bit.C21
  342. #define PB_CR2_C22               PB_CR2_bit.C22
  343. #define PB_CR2_C23               PB_CR2_bit.C23
  344. #define PB_CR2_C24               PB_CR2_bit.C24
  345. #define PB_CR2_C25               PB_CR2_bit.C25
  346. #define PB_CR2_C26               PB_CR2_bit.C26
  347. #define PB_CR2_C27               PB_CR2_bit.C27
  348.  
  349. #endif
  350.  
  351. /*-------------------------------------------------------------------------
  352.  *      Port B bit masks
  353.  *-----------------------------------------------------------------------*/
  354. #define MASK_PB_ODR_ODR0         0x01
  355. #define MASK_PB_ODR_ODR1         0x02
  356. #define MASK_PB_ODR_ODR2         0x04
  357. #define MASK_PB_ODR_ODR3         0x08
  358. #define MASK_PB_ODR_ODR4         0x10
  359. #define MASK_PB_ODR_ODR5         0x20
  360. #define MASK_PB_ODR_ODR6         0x40
  361. #define MASK_PB_ODR_ODR7         0x80
  362.  
  363. #define MASK_PB_IDR_IDR0         0x01
  364. #define MASK_PB_IDR_IDR1         0x02
  365. #define MASK_PB_IDR_IDR2         0x04
  366. #define MASK_PB_IDR_IDR3         0x08
  367. #define MASK_PB_IDR_IDR4         0x10
  368. #define MASK_PB_IDR_IDR5         0x20
  369. #define MASK_PB_IDR_IDR6         0x40
  370. #define MASK_PB_IDR_IDR7         0x80
  371.  
  372. #define MASK_PB_DDR_DDR0         0x01
  373. #define MASK_PB_DDR_DDR1         0x02
  374. #define MASK_PB_DDR_DDR2         0x04
  375. #define MASK_PB_DDR_DDR3         0x08
  376. #define MASK_PB_DDR_DDR4         0x10
  377. #define MASK_PB_DDR_DDR5         0x20
  378. #define MASK_PB_DDR_DDR6         0x40
  379. #define MASK_PB_DDR_DDR7         0x80
  380.  
  381. #define MASK_PB_CR1_C10          0x01
  382. #define MASK_PB_CR1_C11          0x02
  383. #define MASK_PB_CR1_C12          0x04
  384. #define MASK_PB_CR1_C13          0x08
  385. #define MASK_PB_CR1_C14          0x10
  386. #define MASK_PB_CR1_C15          0x20
  387. #define MASK_PB_CR1_C16          0x40
  388. #define MASK_PB_CR1_C17          0x80
  389.  
  390. #define MASK_PB_CR2_C20          0x01
  391. #define MASK_PB_CR2_C21          0x02
  392. #define MASK_PB_CR2_C22          0x04
  393. #define MASK_PB_CR2_C23          0x08
  394. #define MASK_PB_CR2_C24          0x10
  395. #define MASK_PB_CR2_C25          0x20
  396. #define MASK_PB_CR2_C26          0x40
  397. #define MASK_PB_CR2_C27          0x80
  398.  
  399.  
  400. /*-------------------------------------------------------------------------
  401.  *      Port C register definitions
  402.  *-----------------------------------------------------------------------*/
  403. /* Port C data output latch register */
  404. #ifdef __IAR_SYSTEMS_ICC__
  405. typedef struct
  406. {
  407.   unsigned char ODR0        : 1;
  408.   unsigned char ODR1        : 1;
  409.   unsigned char ODR2        : 1;
  410.   unsigned char ODR3        : 1;
  411.   unsigned char ODR4        : 1;
  412.   unsigned char ODR5        : 1;
  413.   unsigned char ODR6        : 1;
  414.   unsigned char ODR7        : 1;
  415. } __BITS_PC_ODR;
  416. #endif
  417. __IO_REG8_BIT(PC_ODR,      0x500A, __READ_WRITE, __BITS_PC_ODR);
  418.  
  419. /* Port C input pin value register */
  420. #ifdef __IAR_SYSTEMS_ICC__
  421. typedef struct
  422. {
  423.   unsigned char IDR0        : 1;
  424.   unsigned char IDR1        : 1;
  425.   unsigned char IDR2        : 1;
  426.   unsigned char IDR3        : 1;
  427.   unsigned char IDR4        : 1;
  428.   unsigned char IDR5        : 1;
  429.   unsigned char IDR6        : 1;
  430.   unsigned char IDR7        : 1;
  431. } __BITS_PC_IDR;
  432. #endif
  433. __IO_REG8_BIT(PC_IDR,      0x500B, __READ, __BITS_PC_IDR);
  434.  
  435. /* Port C data direction register */
  436. #ifdef __IAR_SYSTEMS_ICC__
  437. typedef struct
  438. {
  439.   unsigned char DDR0        : 1;
  440.   unsigned char DDR1        : 1;
  441.   unsigned char DDR2        : 1;
  442.   unsigned char DDR3        : 1;
  443.   unsigned char DDR4        : 1;
  444.   unsigned char DDR5        : 1;
  445.   unsigned char DDR6        : 1;
  446.   unsigned char DDR7        : 1;
  447. } __BITS_PC_DDR;
  448. #endif
  449. __IO_REG8_BIT(PC_DDR,      0x500C, __READ_WRITE, __BITS_PC_DDR);
  450.  
  451. /* Port C control register 1 */
  452. #ifdef __IAR_SYSTEMS_ICC__
  453. typedef struct
  454. {
  455.   unsigned char C10         : 1;
  456.   unsigned char C11         : 1;
  457.   unsigned char C12         : 1;
  458.   unsigned char C13         : 1;
  459.   unsigned char C14         : 1;
  460.   unsigned char C15         : 1;
  461.   unsigned char C16         : 1;
  462.   unsigned char C17         : 1;
  463. } __BITS_PC_CR1;
  464. #endif
  465. __IO_REG8_BIT(PC_CR1,      0x500D, __READ_WRITE, __BITS_PC_CR1);
  466.  
  467. /* Port C control register 2 */
  468. #ifdef __IAR_SYSTEMS_ICC__
  469. typedef struct
  470. {
  471.   unsigned char C20         : 1;
  472.   unsigned char C21         : 1;
  473.   unsigned char C22         : 1;
  474.   unsigned char C23         : 1;
  475.   unsigned char C24         : 1;
  476.   unsigned char C25         : 1;
  477.   unsigned char C26         : 1;
  478.   unsigned char C27         : 1;
  479. } __BITS_PC_CR2;
  480. #endif
  481. __IO_REG8_BIT(PC_CR2,      0x500E, __READ_WRITE, __BITS_PC_CR2);
  482.  
  483.  
  484. /*-------------------------------------------------------------------------
  485.  *      Port C bit fields
  486.  *-----------------------------------------------------------------------*/
  487. #ifdef __IAR_SYSTEMS_ICC__
  488.  
  489. #define PC_ODR_ODR0              PC_ODR_bit.ODR0
  490. #define PC_ODR_ODR1              PC_ODR_bit.ODR1
  491. #define PC_ODR_ODR2              PC_ODR_bit.ODR2
  492. #define PC_ODR_ODR3              PC_ODR_bit.ODR3
  493. #define PC_ODR_ODR4              PC_ODR_bit.ODR4
  494. #define PC_ODR_ODR5              PC_ODR_bit.ODR5
  495. #define PC_ODR_ODR6              PC_ODR_bit.ODR6
  496. #define PC_ODR_ODR7              PC_ODR_bit.ODR7
  497.  
  498. #define PC_IDR_IDR0              PC_IDR_bit.IDR0
  499. #define PC_IDR_IDR1              PC_IDR_bit.IDR1
  500. #define PC_IDR_IDR2              PC_IDR_bit.IDR2
  501. #define PC_IDR_IDR3              PC_IDR_bit.IDR3
  502. #define PC_IDR_IDR4              PC_IDR_bit.IDR4
  503. #define PC_IDR_IDR5              PC_IDR_bit.IDR5
  504. #define PC_IDR_IDR6              PC_IDR_bit.IDR6
  505. #define PC_IDR_IDR7              PC_IDR_bit.IDR7
  506.  
  507. #define PC_DDR_DDR0              PC_DDR_bit.DDR0
  508. #define PC_DDR_DDR1              PC_DDR_bit.DDR1
  509. #define PC_DDR_DDR2              PC_DDR_bit.DDR2
  510. #define PC_DDR_DDR3              PC_DDR_bit.DDR3
  511. #define PC_DDR_DDR4              PC_DDR_bit.DDR4
  512. #define PC_DDR_DDR5              PC_DDR_bit.DDR5
  513. #define PC_DDR_DDR6              PC_DDR_bit.DDR6
  514. #define PC_DDR_DDR7              PC_DDR_bit.DDR7
  515.  
  516. #define PC_CR1_C10               PC_CR1_bit.C10
  517. #define PC_CR1_C11               PC_CR1_bit.C11
  518. #define PC_CR1_C12               PC_CR1_bit.C12
  519. #define PC_CR1_C13               PC_CR1_bit.C13
  520. #define PC_CR1_C14               PC_CR1_bit.C14
  521. #define PC_CR1_C15               PC_CR1_bit.C15
  522. #define PC_CR1_C16               PC_CR1_bit.C16
  523. #define PC_CR1_C17               PC_CR1_bit.C17
  524.  
  525. #define PC_CR2_C20               PC_CR2_bit.C20
  526. #define PC_CR2_C21               PC_CR2_bit.C21
  527. #define PC_CR2_C22               PC_CR2_bit.C22
  528. #define PC_CR2_C23               PC_CR2_bit.C23
  529. #define PC_CR2_C24               PC_CR2_bit.C24
  530. #define PC_CR2_C25               PC_CR2_bit.C25
  531. #define PC_CR2_C26               PC_CR2_bit.C26
  532. #define PC_CR2_C27               PC_CR2_bit.C27
  533.  
  534. #endif
  535.  
  536. /*-------------------------------------------------------------------------
  537.  *      Port C bit masks
  538.  *-----------------------------------------------------------------------*/
  539. #define MASK_PC_ODR_ODR0         0x01
  540. #define MASK_PC_ODR_ODR1         0x02
  541. #define MASK_PC_ODR_ODR2         0x04
  542. #define MASK_PC_ODR_ODR3         0x08
  543. #define MASK_PC_ODR_ODR4         0x10
  544. #define MASK_PC_ODR_ODR5         0x20
  545. #define MASK_PC_ODR_ODR6         0x40
  546. #define MASK_PC_ODR_ODR7         0x80
  547.  
  548. #define MASK_PC_IDR_IDR0         0x01
  549. #define MASK_PC_IDR_IDR1         0x02
  550. #define MASK_PC_IDR_IDR2         0x04
  551. #define MASK_PC_IDR_IDR3         0x08
  552. #define MASK_PC_IDR_IDR4         0x10
  553. #define MASK_PC_IDR_IDR5         0x20
  554. #define MASK_PC_IDR_IDR6         0x40
  555. #define MASK_PC_IDR_IDR7         0x80
  556.  
  557. #define MASK_PC_DDR_DDR0         0x01
  558. #define MASK_PC_DDR_DDR1         0x02
  559. #define MASK_PC_DDR_DDR2         0x04
  560. #define MASK_PC_DDR_DDR3         0x08
  561. #define MASK_PC_DDR_DDR4         0x10
  562. #define MASK_PC_DDR_DDR5         0x20
  563. #define MASK_PC_DDR_DDR6         0x40
  564. #define MASK_PC_DDR_DDR7         0x80
  565.  
  566. #define MASK_PC_CR1_C10          0x01
  567. #define MASK_PC_CR1_C11          0x02
  568. #define MASK_PC_CR1_C12          0x04
  569. #define MASK_PC_CR1_C13          0x08
  570. #define MASK_PC_CR1_C14          0x10
  571. #define MASK_PC_CR1_C15          0x20
  572. #define MASK_PC_CR1_C16          0x40
  573. #define MASK_PC_CR1_C17          0x80
  574.  
  575. #define MASK_PC_CR2_C20          0x01
  576. #define MASK_PC_CR2_C21          0x02
  577. #define MASK_PC_CR2_C22          0x04
  578. #define MASK_PC_CR2_C23          0x08
  579. #define MASK_PC_CR2_C24          0x10
  580. #define MASK_PC_CR2_C25          0x20
  581. #define MASK_PC_CR2_C26          0x40
  582. #define MASK_PC_CR2_C27          0x80
  583.  
  584.  
  585. /*-------------------------------------------------------------------------
  586.  *      Port D register definitions
  587.  *-----------------------------------------------------------------------*/
  588. /* Port D data output latch register */
  589. #ifdef __IAR_SYSTEMS_ICC__
  590. typedef struct
  591. {
  592.   unsigned char ODR0        : 1;
  593.   unsigned char ODR1        : 1;
  594.   unsigned char ODR2        : 1;
  595.   unsigned char ODR3        : 1;
  596.   unsigned char ODR4        : 1;
  597.   unsigned char ODR5        : 1;
  598.   unsigned char ODR6        : 1;
  599.   unsigned char ODR7        : 1;
  600. } __BITS_PD_ODR;
  601. #endif
  602. __IO_REG8_BIT(PD_ODR,      0x500F, __READ_WRITE, __BITS_PD_ODR);
  603.  
  604. /* Port D input pin value register */
  605. #ifdef __IAR_SYSTEMS_ICC__
  606. typedef struct
  607. {
  608.   unsigned char IDR0        : 1;
  609.   unsigned char IDR1        : 1;
  610.   unsigned char IDR2        : 1;
  611.   unsigned char IDR3        : 1;
  612.   unsigned char IDR4        : 1;
  613.   unsigned char IDR5        : 1;
  614.   unsigned char IDR6        : 1;
  615.   unsigned char IDR7        : 1;
  616. } __BITS_PD_IDR;
  617. #endif
  618. __IO_REG8_BIT(PD_IDR,      0x5010, __READ, __BITS_PD_IDR);
  619.  
  620. /* Port D data direction register */
  621. #ifdef __IAR_SYSTEMS_ICC__
  622. typedef struct
  623. {
  624.   unsigned char DDR0        : 1;
  625.   unsigned char DDR1        : 1;
  626.   unsigned char DDR2        : 1;
  627.   unsigned char DDR3        : 1;
  628.   unsigned char DDR4        : 1;
  629.   unsigned char DDR5        : 1;
  630.   unsigned char DDR6        : 1;
  631.   unsigned char DDR7        : 1;
  632. } __BITS_PD_DDR;
  633. #endif
  634. __IO_REG8_BIT(PD_DDR,      0x5011, __READ_WRITE, __BITS_PD_DDR);
  635.  
  636. /* Port D control register 1 */
  637. #ifdef __IAR_SYSTEMS_ICC__
  638. typedef struct
  639. {
  640.   unsigned char C10         : 1;
  641.   unsigned char C11         : 1;
  642.   unsigned char C12         : 1;
  643.   unsigned char C13         : 1;
  644.   unsigned char C14         : 1;
  645.   unsigned char C15         : 1;
  646.   unsigned char C16         : 1;
  647.   unsigned char C17         : 1;
  648. } __BITS_PD_CR1;
  649. #endif
  650. __IO_REG8_BIT(PD_CR1,      0x5012, __READ_WRITE, __BITS_PD_CR1);
  651.  
  652. /* Port D control register 2 */
  653. #ifdef __IAR_SYSTEMS_ICC__
  654. typedef struct
  655. {
  656.   unsigned char C20         : 1;
  657.   unsigned char C21         : 1;
  658.   unsigned char C22         : 1;
  659.   unsigned char C23         : 1;
  660.   unsigned char C24         : 1;
  661.   unsigned char C25         : 1;
  662.   unsigned char C26         : 1;
  663.   unsigned char C27         : 1;
  664. } __BITS_PD_CR2;
  665. #endif
  666. __IO_REG8_BIT(PD_CR2,      0x5013, __READ_WRITE, __BITS_PD_CR2);
  667.  
  668.  
  669. /*-------------------------------------------------------------------------
  670.  *      Port D bit fields
  671.  *-----------------------------------------------------------------------*/
  672. #ifdef __IAR_SYSTEMS_ICC__
  673.  
  674. #define PD_ODR_ODR0              PD_ODR_bit.ODR0
  675. #define PD_ODR_ODR1              PD_ODR_bit.ODR1
  676. #define PD_ODR_ODR2              PD_ODR_bit.ODR2
  677. #define PD_ODR_ODR3              PD_ODR_bit.ODR3
  678. #define PD_ODR_ODR4              PD_ODR_bit.ODR4
  679. #define PD_ODR_ODR5              PD_ODR_bit.ODR5
  680. #define PD_ODR_ODR6              PD_ODR_bit.ODR6
  681. #define PD_ODR_ODR7              PD_ODR_bit.ODR7
  682.  
  683. #define PD_IDR_IDR0              PD_IDR_bit.IDR0
  684. #define PD_IDR_IDR1              PD_IDR_bit.IDR1
  685. #define PD_IDR_IDR2              PD_IDR_bit.IDR2
  686. #define PD_IDR_IDR3              PD_IDR_bit.IDR3
  687. #define PD_IDR_IDR4              PD_IDR_bit.IDR4
  688. #define PD_IDR_IDR5              PD_IDR_bit.IDR5
  689. #define PD_IDR_IDR6              PD_IDR_bit.IDR6
  690. #define PD_IDR_IDR7              PD_IDR_bit.IDR7
  691.  
  692. #define PD_DDR_DDR0              PD_DDR_bit.DDR0
  693. #define PD_DDR_DDR1              PD_DDR_bit.DDR1
  694. #define PD_DDR_DDR2              PD_DDR_bit.DDR2
  695. #define PD_DDR_DDR3              PD_DDR_bit.DDR3
  696. #define PD_DDR_DDR4              PD_DDR_bit.DDR4
  697. #define PD_DDR_DDR5              PD_DDR_bit.DDR5
  698. #define PD_DDR_DDR6              PD_DDR_bit.DDR6
  699. #define PD_DDR_DDR7              PD_DDR_bit.DDR7
  700.  
  701. #define PD_CR1_C10               PD_CR1_bit.C10
  702. #define PD_CR1_C11               PD_CR1_bit.C11
  703. #define PD_CR1_C12               PD_CR1_bit.C12
  704. #define PD_CR1_C13               PD_CR1_bit.C13
  705. #define PD_CR1_C14               PD_CR1_bit.C14
  706. #define PD_CR1_C15               PD_CR1_bit.C15
  707. #define PD_CR1_C16               PD_CR1_bit.C16
  708. #define PD_CR1_C17               PD_CR1_bit.C17
  709.  
  710. #define PD_CR2_C20               PD_CR2_bit.C20
  711. #define PD_CR2_C21               PD_CR2_bit.C21
  712. #define PD_CR2_C22               PD_CR2_bit.C22
  713. #define PD_CR2_C23               PD_CR2_bit.C23
  714. #define PD_CR2_C24               PD_CR2_bit.C24
  715. #define PD_CR2_C25               PD_CR2_bit.C25
  716. #define PD_CR2_C26               PD_CR2_bit.C26
  717. #define PD_CR2_C27               PD_CR2_bit.C27
  718.  
  719. #endif
  720.  
  721. /*-------------------------------------------------------------------------
  722.  *      Port D bit masks
  723.  *-----------------------------------------------------------------------*/
  724. #define MASK_PD_ODR_ODR0         0x01
  725. #define MASK_PD_ODR_ODR1         0x02
  726. #define MASK_PD_ODR_ODR2         0x04
  727. #define MASK_PD_ODR_ODR3         0x08
  728. #define MASK_PD_ODR_ODR4         0x10
  729. #define MASK_PD_ODR_ODR5         0x20
  730. #define MASK_PD_ODR_ODR6         0x40
  731. #define MASK_PD_ODR_ODR7         0x80
  732.  
  733. #define MASK_PD_IDR_IDR0         0x01
  734. #define MASK_PD_IDR_IDR1         0x02
  735. #define MASK_PD_IDR_IDR2         0x04
  736. #define MASK_PD_IDR_IDR3         0x08
  737. #define MASK_PD_IDR_IDR4         0x10
  738. #define MASK_PD_IDR_IDR5         0x20
  739. #define MASK_PD_IDR_IDR6         0x40
  740. #define MASK_PD_IDR_IDR7         0x80
  741.  
  742. #define MASK_PD_DDR_DDR0         0x01
  743. #define MASK_PD_DDR_DDR1         0x02
  744. #define MASK_PD_DDR_DDR2         0x04
  745. #define MASK_PD_DDR_DDR3         0x08
  746. #define MASK_PD_DDR_DDR4         0x10
  747. #define MASK_PD_DDR_DDR5         0x20
  748. #define MASK_PD_DDR_DDR6         0x40
  749. #define MASK_PD_DDR_DDR7         0x80
  750.  
  751. #define MASK_PD_CR1_C10          0x01
  752. #define MASK_PD_CR1_C11          0x02
  753. #define MASK_PD_CR1_C12          0x04
  754. #define MASK_PD_CR1_C13          0x08
  755. #define MASK_PD_CR1_C14          0x10
  756. #define MASK_PD_CR1_C15          0x20
  757. #define MASK_PD_CR1_C16          0x40
  758. #define MASK_PD_CR1_C17          0x80
  759.  
  760. #define MASK_PD_CR2_C20          0x01
  761. #define MASK_PD_CR2_C21          0x02
  762. #define MASK_PD_CR2_C22          0x04
  763. #define MASK_PD_CR2_C23          0x08
  764. #define MASK_PD_CR2_C24          0x10
  765. #define MASK_PD_CR2_C25          0x20
  766. #define MASK_PD_CR2_C26          0x40
  767. #define MASK_PD_CR2_C27          0x80
  768.  
  769.  
  770. /*-------------------------------------------------------------------------
  771.  *      Port E register definitions
  772.  *-----------------------------------------------------------------------*/
  773. /* Port E data output latch register */
  774. #ifdef __IAR_SYSTEMS_ICC__
  775. typedef struct
  776. {
  777.   unsigned char ODR0        : 1;
  778.   unsigned char ODR1        : 1;
  779.   unsigned char ODR2        : 1;
  780.   unsigned char ODR3        : 1;
  781.   unsigned char ODR4        : 1;
  782.   unsigned char ODR5        : 1;
  783.   unsigned char ODR6        : 1;
  784.   unsigned char ODR7        : 1;
  785. } __BITS_PE_ODR;
  786. #endif
  787. __IO_REG8_BIT(PE_ODR,      0x5014, __READ_WRITE, __BITS_PE_ODR);
  788.  
  789. /* Port E input pin value register */
  790. #ifdef __IAR_SYSTEMS_ICC__
  791. typedef struct
  792. {
  793.   unsigned char IDR0        : 1;
  794.   unsigned char IDR1        : 1;
  795.   unsigned char IDR2        : 1;
  796.   unsigned char IDR3        : 1;
  797.   unsigned char IDR4        : 1;
  798.   unsigned char IDR5        : 1;
  799.   unsigned char IDR6        : 1;
  800.   unsigned char IDR7        : 1;
  801. } __BITS_PE_IDR;
  802. #endif
  803. __IO_REG8_BIT(PE_IDR,      0x5015, __READ, __BITS_PE_IDR);
  804.  
  805. /* Port E data direction register */
  806. #ifdef __IAR_SYSTEMS_ICC__
  807. typedef struct
  808. {
  809.   unsigned char DDR0        : 1;
  810.   unsigned char DDR1        : 1;
  811.   unsigned char DDR2        : 1;
  812.   unsigned char DDR3        : 1;
  813.   unsigned char DDR4        : 1;
  814.   unsigned char DDR5        : 1;
  815.   unsigned char DDR6        : 1;
  816.   unsigned char DDR7        : 1;
  817. } __BITS_PE_DDR;
  818. #endif
  819. __IO_REG8_BIT(PE_DDR,      0x5016, __READ_WRITE, __BITS_PE_DDR);
  820.  
  821. /* Port E control register 1 */
  822. #ifdef __IAR_SYSTEMS_ICC__
  823. typedef struct
  824. {
  825.   unsigned char C10         : 1;
  826.   unsigned char C11         : 1;
  827.   unsigned char C12         : 1;
  828.   unsigned char C13         : 1;
  829.   unsigned char C14         : 1;
  830.   unsigned char C15         : 1;
  831.   unsigned char C16         : 1;
  832.   unsigned char C17         : 1;
  833. } __BITS_PE_CR1;
  834. #endif
  835. __IO_REG8_BIT(PE_CR1,      0x5017, __READ_WRITE, __BITS_PE_CR1);
  836.  
  837. /* Port E control register 2 */
  838. #ifdef __IAR_SYSTEMS_ICC__
  839. typedef struct
  840. {
  841.   unsigned char C20         : 1;
  842.   unsigned char C21         : 1;
  843.   unsigned char C22         : 1;
  844.   unsigned char C23         : 1;
  845.   unsigned char C24         : 1;
  846.   unsigned char C25         : 1;
  847.   unsigned char C26         : 1;
  848.   unsigned char C27         : 1;
  849. } __BITS_PE_CR2;
  850. #endif
  851. __IO_REG8_BIT(PE_CR2,      0x5018, __READ_WRITE, __BITS_PE_CR2);
  852.  
  853.  
  854. /*-------------------------------------------------------------------------
  855.  *      Port E bit fields
  856.  *-----------------------------------------------------------------------*/
  857. #ifdef __IAR_SYSTEMS_ICC__
  858.  
  859. #define PE_ODR_ODR0              PE_ODR_bit.ODR0
  860. #define PE_ODR_ODR1              PE_ODR_bit.ODR1
  861. #define PE_ODR_ODR2              PE_ODR_bit.ODR2
  862. #define PE_ODR_ODR3              PE_ODR_bit.ODR3
  863. #define PE_ODR_ODR4              PE_ODR_bit.ODR4
  864. #define PE_ODR_ODR5              PE_ODR_bit.ODR5
  865. #define PE_ODR_ODR6              PE_ODR_bit.ODR6
  866. #define PE_ODR_ODR7              PE_ODR_bit.ODR7
  867.  
  868. #define PE_IDR_IDR0              PE_IDR_bit.IDR0
  869. #define PE_IDR_IDR1              PE_IDR_bit.IDR1
  870. #define PE_IDR_IDR2              PE_IDR_bit.IDR2
  871. #define PE_IDR_IDR3              PE_IDR_bit.IDR3
  872. #define PE_IDR_IDR4              PE_IDR_bit.IDR4
  873. #define PE_IDR_IDR5              PE_IDR_bit.IDR5
  874. #define PE_IDR_IDR6              PE_IDR_bit.IDR6
  875. #define PE_IDR_IDR7              PE_IDR_bit.IDR7
  876.  
  877. #define PE_DDR_DDR0              PE_DDR_bit.DDR0
  878. #define PE_DDR_DDR1              PE_DDR_bit.DDR1
  879. #define PE_DDR_DDR2              PE_DDR_bit.DDR2
  880. #define PE_DDR_DDR3              PE_DDR_bit.DDR3
  881. #define PE_DDR_DDR4              PE_DDR_bit.DDR4
  882. #define PE_DDR_DDR5              PE_DDR_bit.DDR5
  883. #define PE_DDR_DDR6              PE_DDR_bit.DDR6
  884. #define PE_DDR_DDR7              PE_DDR_bit.DDR7
  885.  
  886. #define PE_CR1_C10               PE_CR1_bit.C10
  887. #define PE_CR1_C11               PE_CR1_bit.C11
  888. #define PE_CR1_C12               PE_CR1_bit.C12
  889. #define PE_CR1_C13               PE_CR1_bit.C13
  890. #define PE_CR1_C14               PE_CR1_bit.C14
  891. #define PE_CR1_C15               PE_CR1_bit.C15
  892. #define PE_CR1_C16               PE_CR1_bit.C16
  893. #define PE_CR1_C17               PE_CR1_bit.C17
  894.  
  895. #define PE_CR2_C20               PE_CR2_bit.C20
  896. #define PE_CR2_C21               PE_CR2_bit.C21
  897. #define PE_CR2_C22               PE_CR2_bit.C22
  898. #define PE_CR2_C23               PE_CR2_bit.C23
  899. #define PE_CR2_C24               PE_CR2_bit.C24
  900. #define PE_CR2_C25               PE_CR2_bit.C25
  901. #define PE_CR2_C26               PE_CR2_bit.C26
  902. #define PE_CR2_C27               PE_CR2_bit.C27
  903.  
  904. #endif
  905.  
  906. /*-------------------------------------------------------------------------
  907.  *      Port E bit masks
  908.  *-----------------------------------------------------------------------*/
  909. #define MASK_PE_ODR_ODR0         0x01
  910. #define MASK_PE_ODR_ODR1         0x02
  911. #define MASK_PE_ODR_ODR2         0x04
  912. #define MASK_PE_ODR_ODR3         0x08
  913. #define MASK_PE_ODR_ODR4         0x10
  914. #define MASK_PE_ODR_ODR5         0x20
  915. #define MASK_PE_ODR_ODR6         0x40
  916. #define MASK_PE_ODR_ODR7         0x80
  917.  
  918. #define MASK_PE_IDR_IDR0         0x01
  919. #define MASK_PE_IDR_IDR1         0x02
  920. #define MASK_PE_IDR_IDR2         0x04
  921. #define MASK_PE_IDR_IDR3         0x08
  922. #define MASK_PE_IDR_IDR4         0x10
  923. #define MASK_PE_IDR_IDR5         0x20
  924. #define MASK_PE_IDR_IDR6         0x40
  925. #define MASK_PE_IDR_IDR7         0x80
  926.  
  927. #define MASK_PE_DDR_DDR0         0x01
  928. #define MASK_PE_DDR_DDR1         0x02
  929. #define MASK_PE_DDR_DDR2         0x04
  930. #define MASK_PE_DDR_DDR3         0x08
  931. #define MASK_PE_DDR_DDR4         0x10
  932. #define MASK_PE_DDR_DDR5         0x20
  933. #define MASK_PE_DDR_DDR6         0x40
  934. #define MASK_PE_DDR_DDR7         0x80
  935.  
  936. #define MASK_PE_CR1_C10          0x01
  937. #define MASK_PE_CR1_C11          0x02
  938. #define MASK_PE_CR1_C12          0x04
  939. #define MASK_PE_CR1_C13          0x08
  940. #define MASK_PE_CR1_C14          0x10
  941. #define MASK_PE_CR1_C15          0x20
  942. #define MASK_PE_CR1_C16          0x40
  943. #define MASK_PE_CR1_C17          0x80
  944.  
  945. #define MASK_PE_CR2_C20          0x01
  946. #define MASK_PE_CR2_C21          0x02
  947. #define MASK_PE_CR2_C22          0x04
  948. #define MASK_PE_CR2_C23          0x08
  949. #define MASK_PE_CR2_C24          0x10
  950. #define MASK_PE_CR2_C25          0x20
  951. #define MASK_PE_CR2_C26          0x40
  952. #define MASK_PE_CR2_C27          0x80
  953.  
  954.  
  955. /*-------------------------------------------------------------------------
  956.  *      Port F register definitions
  957.  *-----------------------------------------------------------------------*/
  958. /* Port F data output latch register */
  959. #ifdef __IAR_SYSTEMS_ICC__
  960. typedef struct
  961. {
  962.   unsigned char ODR0        : 1;
  963.   unsigned char ODR1        : 1;
  964.   unsigned char ODR2        : 1;
  965.   unsigned char ODR3        : 1;
  966.   unsigned char ODR4        : 1;
  967.   unsigned char ODR5        : 1;
  968.   unsigned char ODR6        : 1;
  969.   unsigned char ODR7        : 1;
  970. } __BITS_PF_ODR;
  971. #endif
  972. __IO_REG8_BIT(PF_ODR,      0x5019, __READ_WRITE, __BITS_PF_ODR);
  973.  
  974. /* Port F input pin value register */
  975. #ifdef __IAR_SYSTEMS_ICC__
  976. typedef struct
  977. {
  978.   unsigned char IDR0        : 1;
  979.   unsigned char IDR1        : 1;
  980.   unsigned char IDR2        : 1;
  981.   unsigned char IDR3        : 1;
  982.   unsigned char IDR4        : 1;
  983.   unsigned char IDR5        : 1;
  984.   unsigned char IDR6        : 1;
  985.   unsigned char IDR7        : 1;
  986. } __BITS_PF_IDR;
  987. #endif
  988. __IO_REG8_BIT(PF_IDR,      0x501A, __READ, __BITS_PF_IDR);
  989.  
  990. /* Port F data direction register */
  991. #ifdef __IAR_SYSTEMS_ICC__
  992. typedef struct
  993. {
  994.   unsigned char DDR0        : 1;
  995.   unsigned char DDR1        : 1;
  996.   unsigned char DDR2        : 1;
  997.   unsigned char DDR3        : 1;
  998.   unsigned char DDR4        : 1;
  999.   unsigned char DDR5        : 1;
  1000.   unsigned char DDR6        : 1;
  1001.   unsigned char DDR7        : 1;
  1002. } __BITS_PF_DDR;
  1003. #endif
  1004. __IO_REG8_BIT(PF_DDR,      0x501B, __READ_WRITE, __BITS_PF_DDR);
  1005.  
  1006. /* Port F control register 1 */
  1007. #ifdef __IAR_SYSTEMS_ICC__
  1008. typedef struct
  1009. {
  1010.   unsigned char C10         : 1;
  1011.   unsigned char C11         : 1;
  1012.   unsigned char C12         : 1;
  1013.   unsigned char C13         : 1;
  1014.   unsigned char C14         : 1;
  1015.   unsigned char C15         : 1;
  1016.   unsigned char C16         : 1;
  1017.   unsigned char C17         : 1;
  1018. } __BITS_PF_CR1;
  1019. #endif
  1020. __IO_REG8_BIT(PF_CR1,      0x501C, __READ_WRITE, __BITS_PF_CR1);
  1021.  
  1022. /* Port F control register 2 */
  1023. #ifdef __IAR_SYSTEMS_ICC__
  1024. typedef struct
  1025. {
  1026.   unsigned char C20         : 1;
  1027.   unsigned char C21         : 1;
  1028.   unsigned char C22         : 1;
  1029.   unsigned char C23         : 1;
  1030.   unsigned char C24         : 1;
  1031.   unsigned char C25         : 1;
  1032.   unsigned char C26         : 1;
  1033.   unsigned char C27         : 1;
  1034. } __BITS_PF_CR2;
  1035. #endif
  1036. __IO_REG8_BIT(PF_CR2,      0x501D, __READ_WRITE, __BITS_PF_CR2);
  1037.  
  1038.  
  1039. /*-------------------------------------------------------------------------
  1040.  *      Port F bit fields
  1041.  *-----------------------------------------------------------------------*/
  1042. #ifdef __IAR_SYSTEMS_ICC__
  1043.  
  1044. #define PF_ODR_ODR0              PF_ODR_bit.ODR0
  1045. #define PF_ODR_ODR1              PF_ODR_bit.ODR1
  1046. #define PF_ODR_ODR2              PF_ODR_bit.ODR2
  1047. #define PF_ODR_ODR3              PF_ODR_bit.ODR3
  1048. #define PF_ODR_ODR4              PF_ODR_bit.ODR4
  1049. #define PF_ODR_ODR5              PF_ODR_bit.ODR5
  1050. #define PF_ODR_ODR6              PF_ODR_bit.ODR6
  1051. #define PF_ODR_ODR7              PF_ODR_bit.ODR7
  1052.  
  1053. #define PF_IDR_IDR0              PF_IDR_bit.IDR0
  1054. #define PF_IDR_IDR1              PF_IDR_bit.IDR1
  1055. #define PF_IDR_IDR2              PF_IDR_bit.IDR2
  1056. #define PF_IDR_IDR3              PF_IDR_bit.IDR3
  1057. #define PF_IDR_IDR4              PF_IDR_bit.IDR4
  1058. #define PF_IDR_IDR5              PF_IDR_bit.IDR5
  1059. #define PF_IDR_IDR6              PF_IDR_bit.IDR6
  1060. #define PF_IDR_IDR7              PF_IDR_bit.IDR7
  1061.  
  1062. #define PF_DDR_DDR0              PF_DDR_bit.DDR0
  1063. #define PF_DDR_DDR1              PF_DDR_bit.DDR1
  1064. #define PF_DDR_DDR2              PF_DDR_bit.DDR2
  1065. #define PF_DDR_DDR3              PF_DDR_bit.DDR3
  1066. #define PF_DDR_DDR4              PF_DDR_bit.DDR4
  1067. #define PF_DDR_DDR5              PF_DDR_bit.DDR5
  1068. #define PF_DDR_DDR6              PF_DDR_bit.DDR6
  1069. #define PF_DDR_DDR7              PF_DDR_bit.DDR7
  1070.  
  1071. #define PF_CR1_C10               PF_CR1_bit.C10
  1072. #define PF_CR1_C11               PF_CR1_bit.C11
  1073. #define PF_CR1_C12               PF_CR1_bit.C12
  1074. #define PF_CR1_C13               PF_CR1_bit.C13
  1075. #define PF_CR1_C14               PF_CR1_bit.C14
  1076. #define PF_CR1_C15               PF_CR1_bit.C15
  1077. #define PF_CR1_C16               PF_CR1_bit.C16
  1078. #define PF_CR1_C17               PF_CR1_bit.C17
  1079.  
  1080. #define PF_CR2_C20               PF_CR2_bit.C20
  1081. #define PF_CR2_C21               PF_CR2_bit.C21
  1082. #define PF_CR2_C22               PF_CR2_bit.C22
  1083. #define PF_CR2_C23               PF_CR2_bit.C23
  1084. #define PF_CR2_C24               PF_CR2_bit.C24
  1085. #define PF_CR2_C25               PF_CR2_bit.C25
  1086. #define PF_CR2_C26               PF_CR2_bit.C26
  1087. #define PF_CR2_C27               PF_CR2_bit.C27
  1088.  
  1089. #endif
  1090.  
  1091. /*-------------------------------------------------------------------------
  1092.  *      Port F bit masks
  1093.  *-----------------------------------------------------------------------*/
  1094. #define MASK_PF_ODR_ODR0         0x01
  1095. #define MASK_PF_ODR_ODR1         0x02
  1096. #define MASK_PF_ODR_ODR2         0x04
  1097. #define MASK_PF_ODR_ODR3         0x08
  1098. #define MASK_PF_ODR_ODR4         0x10
  1099. #define MASK_PF_ODR_ODR5         0x20
  1100. #define MASK_PF_ODR_ODR6         0x40
  1101. #define MASK_PF_ODR_ODR7         0x80
  1102.  
  1103. #define MASK_PF_IDR_IDR0         0x01
  1104. #define MASK_PF_IDR_IDR1         0x02
  1105. #define MASK_PF_IDR_IDR2         0x04
  1106. #define MASK_PF_IDR_IDR3         0x08
  1107. #define MASK_PF_IDR_IDR4         0x10
  1108. #define MASK_PF_IDR_IDR5         0x20
  1109. #define MASK_PF_IDR_IDR6         0x40
  1110. #define MASK_PF_IDR_IDR7         0x80
  1111.  
  1112. #define MASK_PF_DDR_DDR0         0x01
  1113. #define MASK_PF_DDR_DDR1         0x02
  1114. #define MASK_PF_DDR_DDR2         0x04
  1115. #define MASK_PF_DDR_DDR3         0x08
  1116. #define MASK_PF_DDR_DDR4         0x10
  1117. #define MASK_PF_DDR_DDR5         0x20
  1118. #define MASK_PF_DDR_DDR6         0x40
  1119. #define MASK_PF_DDR_DDR7         0x80
  1120.  
  1121. #define MASK_PF_CR1_C10          0x01
  1122. #define MASK_PF_CR1_C11          0x02
  1123. #define MASK_PF_CR1_C12          0x04
  1124. #define MASK_PF_CR1_C13          0x08
  1125. #define MASK_PF_CR1_C14          0x10
  1126. #define MASK_PF_CR1_C15          0x20
  1127. #define MASK_PF_CR1_C16          0x40
  1128. #define MASK_PF_CR1_C17          0x80
  1129.  
  1130. #define MASK_PF_CR2_C20          0x01
  1131. #define MASK_PF_CR2_C21          0x02
  1132. #define MASK_PF_CR2_C22          0x04
  1133. #define MASK_PF_CR2_C23          0x08
  1134. #define MASK_PF_CR2_C24          0x10
  1135. #define MASK_PF_CR2_C25          0x20
  1136. #define MASK_PF_CR2_C26          0x40
  1137. #define MASK_PF_CR2_C27          0x80
  1138.  
  1139.  
  1140. /*-------------------------------------------------------------------------
  1141.  *      Port G register definitions
  1142.  *-----------------------------------------------------------------------*/
  1143. /* Port G data output latch register */
  1144. #ifdef __IAR_SYSTEMS_ICC__
  1145. typedef struct
  1146. {
  1147.   unsigned char ODR0        : 1;
  1148.   unsigned char ODR1        : 1;
  1149.   unsigned char ODR2        : 1;
  1150.   unsigned char ODR3        : 1;
  1151.   unsigned char ODR4        : 1;
  1152.   unsigned char ODR5        : 1;
  1153.   unsigned char ODR6        : 1;
  1154.   unsigned char ODR7        : 1;
  1155. } __BITS_PG_ODR;
  1156. #endif
  1157. __IO_REG8_BIT(PG_ODR,      0x501E, __READ_WRITE, __BITS_PG_ODR);
  1158.  
  1159. /* Port G input pin value register */
  1160. #ifdef __IAR_SYSTEMS_ICC__
  1161. typedef struct
  1162. {
  1163.   unsigned char IDR0        : 1;
  1164.   unsigned char IDR1        : 1;
  1165.   unsigned char IDR2        : 1;
  1166.   unsigned char IDR3        : 1;
  1167.   unsigned char IDR4        : 1;
  1168.   unsigned char IDR5        : 1;
  1169.   unsigned char IDR6        : 1;
  1170.   unsigned char IDR7        : 1;
  1171. } __BITS_PG_IDR;
  1172. #endif
  1173. __IO_REG8_BIT(PG_IDR,      0x501F, __READ, __BITS_PG_IDR);
  1174.  
  1175. /* Port G data direction register */
  1176. #ifdef __IAR_SYSTEMS_ICC__
  1177. typedef struct
  1178. {
  1179.   unsigned char DDR0        : 1;
  1180.   unsigned char DDR1        : 1;
  1181.   unsigned char DDR2        : 1;
  1182.   unsigned char DDR3        : 1;
  1183.   unsigned char DDR4        : 1;
  1184.   unsigned char DDR5        : 1;
  1185.   unsigned char DDR6        : 1;
  1186.   unsigned char DDR7        : 1;
  1187. } __BITS_PG_DDR;
  1188. #endif
  1189. __IO_REG8_BIT(PG_DDR,      0x5020, __READ_WRITE, __BITS_PG_DDR);
  1190.  
  1191. /* Port G control register 1 */
  1192. #ifdef __IAR_SYSTEMS_ICC__
  1193. typedef struct
  1194. {
  1195.   unsigned char C10         : 1;
  1196.   unsigned char C11         : 1;
  1197.   unsigned char C12         : 1;
  1198.   unsigned char C13         : 1;
  1199.   unsigned char C14         : 1;
  1200.   unsigned char C15         : 1;
  1201.   unsigned char C16         : 1;
  1202.   unsigned char C17         : 1;
  1203. } __BITS_PG_CR1;
  1204. #endif
  1205. __IO_REG8_BIT(PG_CR1,      0x5021, __READ_WRITE, __BITS_PG_CR1);
  1206.  
  1207. /* Port G control register 2 */
  1208. #ifdef __IAR_SYSTEMS_ICC__
  1209. typedef struct
  1210. {
  1211.   unsigned char C20         : 1;
  1212.   unsigned char C21         : 1;
  1213.   unsigned char C22         : 1;
  1214.   unsigned char C23         : 1;
  1215.   unsigned char C24         : 1;
  1216.   unsigned char C25         : 1;
  1217.   unsigned char C26         : 1;
  1218.   unsigned char C27         : 1;
  1219. } __BITS_PG_CR2;
  1220. #endif
  1221. __IO_REG8_BIT(PG_CR2,      0x5022, __READ_WRITE, __BITS_PG_CR2);
  1222.  
  1223.  
  1224. /*-------------------------------------------------------------------------
  1225.  *      Port G bit fields
  1226.  *-----------------------------------------------------------------------*/
  1227. #ifdef __IAR_SYSTEMS_ICC__
  1228.  
  1229. #define PG_ODR_ODR0              PG_ODR_bit.ODR0
  1230. #define PG_ODR_ODR1              PG_ODR_bit.ODR1
  1231. #define PG_ODR_ODR2              PG_ODR_bit.ODR2
  1232. #define PG_ODR_ODR3              PG_ODR_bit.ODR3
  1233. #define PG_ODR_ODR4              PG_ODR_bit.ODR4
  1234. #define PG_ODR_ODR5              PG_ODR_bit.ODR5
  1235. #define PG_ODR_ODR6              PG_ODR_bit.ODR6
  1236. #define PG_ODR_ODR7              PG_ODR_bit.ODR7
  1237.  
  1238. #define PG_IDR_IDR0              PG_IDR_bit.IDR0
  1239. #define PG_IDR_IDR1              PG_IDR_bit.IDR1
  1240. #define PG_IDR_IDR2              PG_IDR_bit.IDR2
  1241. #define PG_IDR_IDR3              PG_IDR_bit.IDR3
  1242. #define PG_IDR_IDR4              PG_IDR_bit.IDR4
  1243. #define PG_IDR_IDR5              PG_IDR_bit.IDR5
  1244. #define PG_IDR_IDR6              PG_IDR_bit.IDR6
  1245. #define PG_IDR_IDR7              PG_IDR_bit.IDR7
  1246.  
  1247. #define PG_DDR_DDR0              PG_DDR_bit.DDR0
  1248. #define PG_DDR_DDR1              PG_DDR_bit.DDR1
  1249. #define PG_DDR_DDR2              PG_DDR_bit.DDR2
  1250. #define PG_DDR_DDR3              PG_DDR_bit.DDR3
  1251. #define PG_DDR_DDR4              PG_DDR_bit.DDR4
  1252. #define PG_DDR_DDR5              PG_DDR_bit.DDR5
  1253. #define PG_DDR_DDR6              PG_DDR_bit.DDR6
  1254. #define PG_DDR_DDR7              PG_DDR_bit.DDR7
  1255.  
  1256. #define PG_CR1_C10               PG_CR1_bit.C10
  1257. #define PG_CR1_C11               PG_CR1_bit.C11
  1258. #define PG_CR1_C12               PG_CR1_bit.C12
  1259. #define PG_CR1_C13               PG_CR1_bit.C13
  1260. #define PG_CR1_C14               PG_CR1_bit.C14
  1261. #define PG_CR1_C15               PG_CR1_bit.C15
  1262. #define PG_CR1_C16               PG_CR1_bit.C16
  1263. #define PG_CR1_C17               PG_CR1_bit.C17
  1264.  
  1265. #define PG_CR2_C20               PG_CR2_bit.C20
  1266. #define PG_CR2_C21               PG_CR2_bit.C21
  1267. #define PG_CR2_C22               PG_CR2_bit.C22
  1268. #define PG_CR2_C23               PG_CR2_bit.C23
  1269. #define PG_CR2_C24               PG_CR2_bit.C24
  1270. #define PG_CR2_C25               PG_CR2_bit.C25
  1271. #define PG_CR2_C26               PG_CR2_bit.C26
  1272. #define PG_CR2_C27               PG_CR2_bit.C27
  1273.  
  1274. #endif
  1275.  
  1276. /*-------------------------------------------------------------------------
  1277.  *      Port G bit masks
  1278.  *-----------------------------------------------------------------------*/
  1279. #define MASK_PG_ODR_ODR0         0x01
  1280. #define MASK_PG_ODR_ODR1         0x02
  1281. #define MASK_PG_ODR_ODR2         0x04
  1282. #define MASK_PG_ODR_ODR3         0x08
  1283. #define MASK_PG_ODR_ODR4         0x10
  1284. #define MASK_PG_ODR_ODR5         0x20
  1285. #define MASK_PG_ODR_ODR6         0x40
  1286. #define MASK_PG_ODR_ODR7         0x80
  1287.  
  1288. #define MASK_PG_IDR_IDR0         0x01
  1289. #define MASK_PG_IDR_IDR1         0x02
  1290. #define MASK_PG_IDR_IDR2         0x04
  1291. #define MASK_PG_IDR_IDR3         0x08
  1292. #define MASK_PG_IDR_IDR4         0x10
  1293. #define MASK_PG_IDR_IDR5         0x20
  1294. #define MASK_PG_IDR_IDR6         0x40
  1295. #define MASK_PG_IDR_IDR7         0x80
  1296.  
  1297. #define MASK_PG_DDR_DDR0         0x01
  1298. #define MASK_PG_DDR_DDR1         0x02
  1299. #define MASK_PG_DDR_DDR2         0x04
  1300. #define MASK_PG_DDR_DDR3         0x08
  1301. #define MASK_PG_DDR_DDR4         0x10
  1302. #define MASK_PG_DDR_DDR5         0x20
  1303. #define MASK_PG_DDR_DDR6         0x40
  1304. #define MASK_PG_DDR_DDR7         0x80
  1305.  
  1306. #define MASK_PG_CR1_C10          0x01
  1307. #define MASK_PG_CR1_C11          0x02
  1308. #define MASK_PG_CR1_C12          0x04
  1309. #define MASK_PG_CR1_C13          0x08
  1310. #define MASK_PG_CR1_C14          0x10
  1311. #define MASK_PG_CR1_C15          0x20
  1312. #define MASK_PG_CR1_C16          0x40
  1313. #define MASK_PG_CR1_C17          0x80
  1314.  
  1315. #define MASK_PG_CR2_C20          0x01
  1316. #define MASK_PG_CR2_C21          0x02
  1317. #define MASK_PG_CR2_C22          0x04
  1318. #define MASK_PG_CR2_C23          0x08
  1319. #define MASK_PG_CR2_C24          0x10
  1320. #define MASK_PG_CR2_C25          0x20
  1321. #define MASK_PG_CR2_C26          0x40
  1322. #define MASK_PG_CR2_C27          0x80
  1323.  
  1324.  
  1325. /*-------------------------------------------------------------------------
  1326.  *      Port H register definitions
  1327.  *-----------------------------------------------------------------------*/
  1328. /* Port H data output latch register */
  1329. #ifdef __IAR_SYSTEMS_ICC__
  1330. typedef struct
  1331. {
  1332.   unsigned char ODR0        : 1;
  1333.   unsigned char ODR1        : 1;
  1334.   unsigned char ODR2        : 1;
  1335.   unsigned char ODR3        : 1;
  1336.   unsigned char ODR4        : 1;
  1337.   unsigned char ODR5        : 1;
  1338.   unsigned char ODR6        : 1;
  1339.   unsigned char ODR7        : 1;
  1340. } __BITS_PH_ODR;
  1341. #endif
  1342. __IO_REG8_BIT(PH_ODR,      0x5023, __READ_WRITE, __BITS_PH_ODR);
  1343.  
  1344. /* Port H input pin value register */
  1345. #ifdef __IAR_SYSTEMS_ICC__
  1346. typedef struct
  1347. {
  1348.   unsigned char IDR0        : 1;
  1349.   unsigned char IDR1        : 1;
  1350.   unsigned char IDR2        : 1;
  1351.   unsigned char IDR3        : 1;
  1352.   unsigned char IDR4        : 1;
  1353.   unsigned char IDR5        : 1;
  1354.   unsigned char IDR6        : 1;
  1355.   unsigned char IDR7        : 1;
  1356. } __BITS_PH_IDR;
  1357. #endif
  1358. __IO_REG8_BIT(PH_IDR,      0x5024, __READ, __BITS_PH_IDR);
  1359.  
  1360. /* Port H data direction register */
  1361. #ifdef __IAR_SYSTEMS_ICC__
  1362. typedef struct
  1363. {
  1364.   unsigned char DDR0        : 1;
  1365.   unsigned char DDR1        : 1;
  1366.   unsigned char DDR2        : 1;
  1367.   unsigned char DDR3        : 1;
  1368.   unsigned char DDR4        : 1;
  1369.   unsigned char DDR5        : 1;
  1370.   unsigned char DDR6        : 1;
  1371.   unsigned char DDR7        : 1;
  1372. } __BITS_PH_DDR;
  1373. #endif
  1374. __IO_REG8_BIT(PH_DDR,      0x5025, __READ_WRITE, __BITS_PH_DDR);
  1375.  
  1376. /* Port H control register 1 */
  1377. #ifdef __IAR_SYSTEMS_ICC__
  1378. typedef struct
  1379. {
  1380.   unsigned char C10         : 1;
  1381.   unsigned char C11         : 1;
  1382.   unsigned char C12         : 1;
  1383.   unsigned char C13         : 1;
  1384.   unsigned char C14         : 1;
  1385.   unsigned char C15         : 1;
  1386.   unsigned char C16         : 1;
  1387.   unsigned char C17         : 1;
  1388. } __BITS_PH_CR1;
  1389. #endif
  1390. __IO_REG8_BIT(PH_CR1,      0x5026, __READ_WRITE, __BITS_PH_CR1);
  1391.  
  1392. /* Port H control register 2 */
  1393. #ifdef __IAR_SYSTEMS_ICC__
  1394. typedef struct
  1395. {
  1396.   unsigned char C20         : 1;
  1397.   unsigned char C21         : 1;
  1398.   unsigned char C22         : 1;
  1399.   unsigned char C23         : 1;
  1400.   unsigned char C24         : 1;
  1401.   unsigned char C25         : 1;
  1402.   unsigned char C26         : 1;
  1403.   unsigned char C27         : 1;
  1404. } __BITS_PH_CR2;
  1405. #endif
  1406. __IO_REG8_BIT(PH_CR2,      0x5027, __READ_WRITE, __BITS_PH_CR2);
  1407.  
  1408.  
  1409. /*-------------------------------------------------------------------------
  1410.  *      Port H bit fields
  1411.  *-----------------------------------------------------------------------*/
  1412. #ifdef __IAR_SYSTEMS_ICC__
  1413.  
  1414. #define PH_ODR_ODR0              PH_ODR_bit.ODR0
  1415. #define PH_ODR_ODR1              PH_ODR_bit.ODR1
  1416. #define PH_ODR_ODR2              PH_ODR_bit.ODR2
  1417. #define PH_ODR_ODR3              PH_ODR_bit.ODR3
  1418. #define PH_ODR_ODR4              PH_ODR_bit.ODR4
  1419. #define PH_ODR_ODR5              PH_ODR_bit.ODR5
  1420. #define PH_ODR_ODR6              PH_ODR_bit.ODR6
  1421. #define PH_ODR_ODR7              PH_ODR_bit.ODR7
  1422.  
  1423. #define PH_IDR_IDR0              PH_IDR_bit.IDR0
  1424. #define PH_IDR_IDR1              PH_IDR_bit.IDR1
  1425. #define PH_IDR_IDR2              PH_IDR_bit.IDR2
  1426. #define PH_IDR_IDR3              PH_IDR_bit.IDR3
  1427. #define PH_IDR_IDR4              PH_IDR_bit.IDR4
  1428. #define PH_IDR_IDR5              PH_IDR_bit.IDR5
  1429. #define PH_IDR_IDR6              PH_IDR_bit.IDR6
  1430. #define PH_IDR_IDR7              PH_IDR_bit.IDR7
  1431.  
  1432. #define PH_DDR_DDR0              PH_DDR_bit.DDR0
  1433. #define PH_DDR_DDR1              PH_DDR_bit.DDR1
  1434. #define PH_DDR_DDR2              PH_DDR_bit.DDR2
  1435. #define PH_DDR_DDR3              PH_DDR_bit.DDR3
  1436. #define PH_DDR_DDR4              PH_DDR_bit.DDR4
  1437. #define PH_DDR_DDR5              PH_DDR_bit.DDR5
  1438. #define PH_DDR_DDR6              PH_DDR_bit.DDR6
  1439. #define PH_DDR_DDR7              PH_DDR_bit.DDR7
  1440.  
  1441. #define PH_CR1_C10               PH_CR1_bit.C10
  1442. #define PH_CR1_C11               PH_CR1_bit.C11
  1443. #define PH_CR1_C12               PH_CR1_bit.C12
  1444. #define PH_CR1_C13               PH_CR1_bit.C13
  1445. #define PH_CR1_C14               PH_CR1_bit.C14
  1446. #define PH_CR1_C15               PH_CR1_bit.C15
  1447. #define PH_CR1_C16               PH_CR1_bit.C16
  1448. #define PH_CR1_C17               PH_CR1_bit.C17
  1449.  
  1450. #define PH_CR2_C20               PH_CR2_bit.C20
  1451. #define PH_CR2_C21               PH_CR2_bit.C21
  1452. #define PH_CR2_C22               PH_CR2_bit.C22
  1453. #define PH_CR2_C23               PH_CR2_bit.C23
  1454. #define PH_CR2_C24               PH_CR2_bit.C24
  1455. #define PH_CR2_C25               PH_CR2_bit.C25
  1456. #define PH_CR2_C26               PH_CR2_bit.C26
  1457. #define PH_CR2_C27               PH_CR2_bit.C27
  1458.  
  1459. #endif
  1460.  
  1461. /*-------------------------------------------------------------------------
  1462.  *      Port H bit masks
  1463.  *-----------------------------------------------------------------------*/
  1464. #define MASK_PH_ODR_ODR0         0x01
  1465. #define MASK_PH_ODR_ODR1         0x02
  1466. #define MASK_PH_ODR_ODR2         0x04
  1467. #define MASK_PH_ODR_ODR3         0x08
  1468. #define MASK_PH_ODR_ODR4         0x10
  1469. #define MASK_PH_ODR_ODR5         0x20
  1470. #define MASK_PH_ODR_ODR6         0x40
  1471. #define MASK_PH_ODR_ODR7         0x80
  1472.  
  1473. #define MASK_PH_IDR_IDR0         0x01
  1474. #define MASK_PH_IDR_IDR1         0x02
  1475. #define MASK_PH_IDR_IDR2         0x04
  1476. #define MASK_PH_IDR_IDR3         0x08
  1477. #define MASK_PH_IDR_IDR4         0x10
  1478. #define MASK_PH_IDR_IDR5         0x20
  1479. #define MASK_PH_IDR_IDR6         0x40
  1480. #define MASK_PH_IDR_IDR7         0x80
  1481.  
  1482. #define MASK_PH_DDR_DDR0         0x01
  1483. #define MASK_PH_DDR_DDR1         0x02
  1484. #define MASK_PH_DDR_DDR2         0x04
  1485. #define MASK_PH_DDR_DDR3         0x08
  1486. #define MASK_PH_DDR_DDR4         0x10
  1487. #define MASK_PH_DDR_DDR5         0x20
  1488. #define MASK_PH_DDR_DDR6         0x40
  1489. #define MASK_PH_DDR_DDR7         0x80
  1490.  
  1491. #define MASK_PH_CR1_C10          0x01
  1492. #define MASK_PH_CR1_C11          0x02
  1493. #define MASK_PH_CR1_C12          0x04
  1494. #define MASK_PH_CR1_C13          0x08
  1495. #define MASK_PH_CR1_C14          0x10
  1496. #define MASK_PH_CR1_C15          0x20
  1497. #define MASK_PH_CR1_C16          0x40
  1498. #define MASK_PH_CR1_C17          0x80
  1499.  
  1500. #define MASK_PH_CR2_C20          0x01
  1501. #define MASK_PH_CR2_C21          0x02
  1502. #define MASK_PH_CR2_C22          0x04
  1503. #define MASK_PH_CR2_C23          0x08
  1504. #define MASK_PH_CR2_C24          0x10
  1505. #define MASK_PH_CR2_C25          0x20
  1506. #define MASK_PH_CR2_C26          0x40
  1507. #define MASK_PH_CR2_C27          0x80
  1508.  
  1509.  
  1510. /*-------------------------------------------------------------------------
  1511.  *      Port I register definitions
  1512.  *-----------------------------------------------------------------------*/
  1513. /* Port I data output latch register */
  1514. #ifdef __IAR_SYSTEMS_ICC__
  1515. typedef struct
  1516. {
  1517.   unsigned char ODR0        : 1;
  1518.   unsigned char ODR1        : 1;
  1519.   unsigned char ODR2        : 1;
  1520.   unsigned char ODR3        : 1;
  1521.   unsigned char ODR4        : 1;
  1522.   unsigned char ODR5        : 1;
  1523.   unsigned char ODR6        : 1;
  1524.   unsigned char ODR7        : 1;
  1525. } __BITS_PI_ODR;
  1526. #endif
  1527. __IO_REG8_BIT(PI_ODR,      0x5028, __READ_WRITE, __BITS_PI_ODR);
  1528.  
  1529. /* Port I input pin value register */
  1530. #ifdef __IAR_SYSTEMS_ICC__
  1531. typedef struct
  1532. {
  1533.   unsigned char IDR0        : 1;
  1534.   unsigned char IDR1        : 1;
  1535.   unsigned char IDR2        : 1;
  1536.   unsigned char IDR3        : 1;
  1537.   unsigned char IDR4        : 1;
  1538.   unsigned char IDR5        : 1;
  1539.   unsigned char IDR6        : 1;
  1540.   unsigned char IDR7        : 1;
  1541. } __BITS_PI_IDR;
  1542. #endif
  1543. __IO_REG8_BIT(PI_IDR,      0x5029, __READ, __BITS_PI_IDR);
  1544.  
  1545. /* Port I data direction register */
  1546. #ifdef __IAR_SYSTEMS_ICC__
  1547. typedef struct
  1548. {
  1549.   unsigned char DDR0        : 1;
  1550.   unsigned char DDR1        : 1;
  1551.   unsigned char DDR2        : 1;
  1552.   unsigned char DDR3        : 1;
  1553.   unsigned char DDR4        : 1;
  1554.   unsigned char DDR5        : 1;
  1555.   unsigned char DDR6        : 1;
  1556.   unsigned char DDR7        : 1;
  1557. } __BITS_PI_DDR;
  1558. #endif
  1559. __IO_REG8_BIT(PI_DDR,      0x502A, __READ_WRITE, __BITS_PI_DDR);
  1560.  
  1561. /* Port I control register 1 */
  1562. #ifdef __IAR_SYSTEMS_ICC__
  1563. typedef struct
  1564. {
  1565.   unsigned char C10         : 1;
  1566.   unsigned char C11         : 1;
  1567.   unsigned char C12         : 1;
  1568.   unsigned char C13         : 1;
  1569.   unsigned char C14         : 1;
  1570.   unsigned char C15         : 1;
  1571.   unsigned char C16         : 1;
  1572.   unsigned char C17         : 1;
  1573. } __BITS_PI_CR1;
  1574. #endif
  1575. __IO_REG8_BIT(PI_CR1,      0x502B, __READ_WRITE, __BITS_PI_CR1);
  1576.  
  1577. /* Port I control register 2 */
  1578. #ifdef __IAR_SYSTEMS_ICC__
  1579. typedef struct
  1580. {
  1581.   unsigned char C20         : 1;
  1582.   unsigned char C21         : 1;
  1583.   unsigned char C22         : 1;
  1584.   unsigned char C23         : 1;
  1585.   unsigned char C24         : 1;
  1586.   unsigned char C25         : 1;
  1587.   unsigned char C26         : 1;
  1588.   unsigned char C27         : 1;
  1589. } __BITS_PI_CR2;
  1590. #endif
  1591. __IO_REG8_BIT(PI_CR2,      0x502C, __READ_WRITE, __BITS_PI_CR2);
  1592.  
  1593.  
  1594. /*-------------------------------------------------------------------------
  1595.  *      Port I bit fields
  1596.  *-----------------------------------------------------------------------*/
  1597. #ifdef __IAR_SYSTEMS_ICC__
  1598.  
  1599. #define PI_ODR_ODR0              PI_ODR_bit.ODR0
  1600. #define PI_ODR_ODR1              PI_ODR_bit.ODR1
  1601. #define PI_ODR_ODR2              PI_ODR_bit.ODR2
  1602. #define PI_ODR_ODR3              PI_ODR_bit.ODR3
  1603. #define PI_ODR_ODR4              PI_ODR_bit.ODR4
  1604. #define PI_ODR_ODR5              PI_ODR_bit.ODR5
  1605. #define PI_ODR_ODR6              PI_ODR_bit.ODR6
  1606. #define PI_ODR_ODR7              PI_ODR_bit.ODR7
  1607.  
  1608. #define PI_IDR_IDR0              PI_IDR_bit.IDR0
  1609. #define PI_IDR_IDR1              PI_IDR_bit.IDR1
  1610. #define PI_IDR_IDR2              PI_IDR_bit.IDR2
  1611. #define PI_IDR_IDR3              PI_IDR_bit.IDR3
  1612. #define PI_IDR_IDR4              PI_IDR_bit.IDR4
  1613. #define PI_IDR_IDR5              PI_IDR_bit.IDR5
  1614. #define PI_IDR_IDR6              PI_IDR_bit.IDR6
  1615. #define PI_IDR_IDR7              PI_IDR_bit.IDR7
  1616.  
  1617. #define PI_DDR_DDR0              PI_DDR_bit.DDR0
  1618. #define PI_DDR_DDR1              PI_DDR_bit.DDR1
  1619. #define PI_DDR_DDR2              PI_DDR_bit.DDR2
  1620. #define PI_DDR_DDR3              PI_DDR_bit.DDR3
  1621. #define PI_DDR_DDR4              PI_DDR_bit.DDR4
  1622. #define PI_DDR_DDR5              PI_DDR_bit.DDR5
  1623. #define PI_DDR_DDR6              PI_DDR_bit.DDR6
  1624. #define PI_DDR_DDR7              PI_DDR_bit.DDR7
  1625.  
  1626. #define PI_CR1_C10               PI_CR1_bit.C10
  1627. #define PI_CR1_C11               PI_CR1_bit.C11
  1628. #define PI_CR1_C12               PI_CR1_bit.C12
  1629. #define PI_CR1_C13               PI_CR1_bit.C13
  1630. #define PI_CR1_C14               PI_CR1_bit.C14
  1631. #define PI_CR1_C15               PI_CR1_bit.C15
  1632. #define PI_CR1_C16               PI_CR1_bit.C16
  1633. #define PI_CR1_C17               PI_CR1_bit.C17
  1634.  
  1635. #define PI_CR2_C20               PI_CR2_bit.C20
  1636. #define PI_CR2_C21               PI_CR2_bit.C21
  1637. #define PI_CR2_C22               PI_CR2_bit.C22
  1638. #define PI_CR2_C23               PI_CR2_bit.C23
  1639. #define PI_CR2_C24               PI_CR2_bit.C24
  1640. #define PI_CR2_C25               PI_CR2_bit.C25
  1641. #define PI_CR2_C26               PI_CR2_bit.C26
  1642. #define PI_CR2_C27               PI_CR2_bit.C27
  1643.  
  1644. #endif
  1645.  
  1646. /*-------------------------------------------------------------------------
  1647.  *      Port I bit masks
  1648.  *-----------------------------------------------------------------------*/
  1649. #define MASK_PI_ODR_ODR0         0x01
  1650. #define MASK_PI_ODR_ODR1         0x02
  1651. #define MASK_PI_ODR_ODR2         0x04
  1652. #define MASK_PI_ODR_ODR3         0x08
  1653. #define MASK_PI_ODR_ODR4         0x10
  1654. #define MASK_PI_ODR_ODR5         0x20
  1655. #define MASK_PI_ODR_ODR6         0x40
  1656. #define MASK_PI_ODR_ODR7         0x80
  1657.  
  1658. #define MASK_PI_IDR_IDR0         0x01
  1659. #define MASK_PI_IDR_IDR1         0x02
  1660. #define MASK_PI_IDR_IDR2         0x04
  1661. #define MASK_PI_IDR_IDR3         0x08
  1662. #define MASK_PI_IDR_IDR4         0x10
  1663. #define MASK_PI_IDR_IDR5         0x20
  1664. #define MASK_PI_IDR_IDR6         0x40
  1665. #define MASK_PI_IDR_IDR7         0x80
  1666.  
  1667. #define MASK_PI_DDR_DDR0         0x01
  1668. #define MASK_PI_DDR_DDR1         0x02
  1669. #define MASK_PI_DDR_DDR2         0x04
  1670. #define MASK_PI_DDR_DDR3         0x08
  1671. #define MASK_PI_DDR_DDR4         0x10
  1672. #define MASK_PI_DDR_DDR5         0x20
  1673. #define MASK_PI_DDR_DDR6         0x40
  1674. #define MASK_PI_DDR_DDR7         0x80
  1675.  
  1676. #define MASK_PI_CR1_C10          0x01
  1677. #define MASK_PI_CR1_C11          0x02
  1678. #define MASK_PI_CR1_C12          0x04
  1679. #define MASK_PI_CR1_C13          0x08
  1680. #define MASK_PI_CR1_C14          0x10
  1681. #define MASK_PI_CR1_C15          0x20
  1682. #define MASK_PI_CR1_C16          0x40
  1683. #define MASK_PI_CR1_C17          0x80
  1684.  
  1685. #define MASK_PI_CR2_C20          0x01
  1686. #define MASK_PI_CR2_C21          0x02
  1687. #define MASK_PI_CR2_C22          0x04
  1688. #define MASK_PI_CR2_C23          0x08
  1689. #define MASK_PI_CR2_C24          0x10
  1690. #define MASK_PI_CR2_C25          0x20
  1691. #define MASK_PI_CR2_C26          0x40
  1692. #define MASK_PI_CR2_C27          0x80
  1693.  
  1694.  
  1695. /*-------------------------------------------------------------------------
  1696.  *      Flash register definitions
  1697.  *-----------------------------------------------------------------------*/
  1698. /* Flash control register 1 */
  1699. #ifdef __IAR_SYSTEMS_ICC__
  1700. typedef struct
  1701. {
  1702.   unsigned char FIX         : 1;
  1703.   unsigned char IE          : 1;
  1704.   unsigned char AHALT       : 1;
  1705.   unsigned char HALT        : 1;
  1706. } __BITS_FLASH_CR1;
  1707. #endif
  1708. __IO_REG8_BIT(FLASH_CR1,   0x505A, __READ_WRITE, __BITS_FLASH_CR1);
  1709.  
  1710. /* Flash control register 2 */
  1711. #ifdef __IAR_SYSTEMS_ICC__
  1712. typedef struct
  1713. {
  1714.   unsigned char PRG         : 1;
  1715.   unsigned char             : 3;
  1716.   unsigned char FPRG        : 1;
  1717.   unsigned char ERASE       : 1;
  1718.   unsigned char WPRG        : 1;
  1719.   unsigned char OPT         : 1;
  1720. } __BITS_FLASH_CR2;
  1721. #endif
  1722. __IO_REG8_BIT(FLASH_CR2,   0x505B, __READ_WRITE, __BITS_FLASH_CR2);
  1723.  
  1724. /* Flash complementary control register 2 */
  1725. #ifdef __IAR_SYSTEMS_ICC__
  1726. typedef struct
  1727. {
  1728.   unsigned char NPRG        : 1;
  1729.   unsigned char             : 3;
  1730.   unsigned char NFPRG       : 1;
  1731.   unsigned char NERASE      : 1;
  1732.   unsigned char NWPRG       : 1;
  1733.   unsigned char NOPT        : 1;
  1734. } __BITS_FLASH_NCR2;
  1735. #endif
  1736. __IO_REG8_BIT(FLASH_NCR2,  0x505C, __READ_WRITE, __BITS_FLASH_NCR2);
  1737.  
  1738. /* Flash protection register */
  1739. #ifdef __IAR_SYSTEMS_ICC__
  1740. typedef struct
  1741. {
  1742.   unsigned char WPB0        : 1;
  1743.   unsigned char WPB1        : 1;
  1744.   unsigned char WPB2        : 1;
  1745.   unsigned char WPB3        : 1;
  1746.   unsigned char WPB4        : 1;
  1747.   unsigned char WPB5        : 1;
  1748. } __BITS_FLASH_FPR;
  1749. #endif
  1750. __IO_REG8_BIT(FLASH_FPR,   0x505D, __READ, __BITS_FLASH_FPR);
  1751.  
  1752. /* Flash complementary protection register */
  1753. #ifdef __IAR_SYSTEMS_ICC__
  1754. typedef struct
  1755. {
  1756.   unsigned char NWPB0       : 1;
  1757.   unsigned char NWPB1       : 1;
  1758.   unsigned char NWPB2       : 1;
  1759.   unsigned char NWPB3       : 1;
  1760.   unsigned char NWPB4       : 1;
  1761.   unsigned char NWPB5       : 1;
  1762. } __BITS_FLASH_NFPR;
  1763. #endif
  1764. __IO_REG8_BIT(FLASH_NFPR,  0x505E, __READ, __BITS_FLASH_NFPR);
  1765.  
  1766. /* Flash in-application programming status register */
  1767. #ifdef __IAR_SYSTEMS_ICC__
  1768. typedef struct
  1769. {
  1770.   unsigned char WR_PG_DIS   : 1;
  1771.   unsigned char PUL         : 1;
  1772.   unsigned char EOP         : 1;
  1773.   unsigned char DUL         : 1;
  1774.   unsigned char             : 2;
  1775.   unsigned char HVOFF       : 1;
  1776. } __BITS_FLASH_IAPSR;
  1777. #endif
  1778. __IO_REG8_BIT(FLASH_IAPSR, 0x505F, __READ_WRITE, __BITS_FLASH_IAPSR);
  1779.  
  1780. /* Flash program memory unprotection register */
  1781. __IO_REG8    (FLASH_PUKR,  0x5062, __READ_WRITE);
  1782. /* Data EEPROM unprotection register */
  1783. __IO_REG8    (FLASH_DUKR,  0x5064, __READ_WRITE);
  1784.  
  1785. /*-------------------------------------------------------------------------
  1786.  *      Flash bit fields
  1787.  *-----------------------------------------------------------------------*/
  1788. #ifdef __IAR_SYSTEMS_ICC__
  1789.  
  1790. #define FLASH_CR1_FIX            FLASH_CR1_bit.FIX
  1791. #define FLASH_CR1_IE             FLASH_CR1_bit.IE
  1792. #define FLASH_CR1_AHALT          FLASH_CR1_bit.AHALT
  1793. #define FLASH_CR1_HALT           FLASH_CR1_bit.HALT
  1794.  
  1795. #define FLASH_CR2_PRG            FLASH_CR2_bit.PRG
  1796. #define FLASH_CR2_FPRG           FLASH_CR2_bit.FPRG
  1797. #define FLASH_CR2_ERASE          FLASH_CR2_bit.ERASE
  1798. #define FLASH_CR2_WPRG           FLASH_CR2_bit.WPRG
  1799. #define FLASH_CR2_OPT            FLASH_CR2_bit.OPT
  1800.  
  1801. #define FLASH_NCR2_NPRG          FLASH_NCR2_bit.NPRG
  1802. #define FLASH_NCR2_NFPRG         FLASH_NCR2_bit.NFPRG
  1803. #define FLASH_NCR2_NERASE        FLASH_NCR2_bit.NERASE
  1804. #define FLASH_NCR2_NWPRG         FLASH_NCR2_bit.NWPRG
  1805. #define FLASH_NCR2_NOPT          FLASH_NCR2_bit.NOPT
  1806.  
  1807. #define FLASH_FPR_WPB0           FLASH_FPR_bit.WPB0
  1808. #define FLASH_FPR_WPB1           FLASH_FPR_bit.WPB1
  1809. #define FLASH_FPR_WPB2           FLASH_FPR_bit.WPB2
  1810. #define FLASH_FPR_WPB3           FLASH_FPR_bit.WPB3
  1811. #define FLASH_FPR_WPB4           FLASH_FPR_bit.WPB4
  1812. #define FLASH_FPR_WPB5           FLASH_FPR_bit.WPB5
  1813.  
  1814. #define FLASH_NFPR_NWPB0         FLASH_NFPR_bit.NWPB0
  1815. #define FLASH_NFPR_NWPB1         FLASH_NFPR_bit.NWPB1
  1816. #define FLASH_NFPR_NWPB2         FLASH_NFPR_bit.NWPB2
  1817. #define FLASH_NFPR_NWPB3         FLASH_NFPR_bit.NWPB3
  1818. #define FLASH_NFPR_NWPB4         FLASH_NFPR_bit.NWPB4
  1819. #define FLASH_NFPR_NWPB5         FLASH_NFPR_bit.NWPB5
  1820.  
  1821. #define FLASH_IAPSR_WR_PG_DIS    FLASH_IAPSR_bit.WR_PG_DIS
  1822. #define FLASH_IAPSR_PUL          FLASH_IAPSR_bit.PUL
  1823. #define FLASH_IAPSR_EOP          FLASH_IAPSR_bit.EOP
  1824. #define FLASH_IAPSR_DUL          FLASH_IAPSR_bit.DUL
  1825. #define FLASH_IAPSR_HVOFF        FLASH_IAPSR_bit.HVOFF
  1826.  
  1827. #endif
  1828.  
  1829. /*-------------------------------------------------------------------------
  1830.  *      Flash bit masks
  1831.  *-----------------------------------------------------------------------*/
  1832. #define MASK_FLASH_CR1_FIX       0x01
  1833. #define MASK_FLASH_CR1_IE        0x02
  1834. #define MASK_FLASH_CR1_AHALT     0x04
  1835. #define MASK_FLASH_CR1_HALT      0x08
  1836.  
  1837. #define MASK_FLASH_CR2_PRG       0x01
  1838. #define MASK_FLASH_CR2_FPRG      0x10
  1839. #define MASK_FLASH_CR2_ERASE     0x20
  1840. #define MASK_FLASH_CR2_WPRG      0x40
  1841. #define MASK_FLASH_CR2_OPT       0x80
  1842.  
  1843. #define MASK_FLASH_NCR2_NPRG     0x01
  1844. #define MASK_FLASH_NCR2_NFPRG    0x10
  1845. #define MASK_FLASH_NCR2_NERASE   0x20
  1846. #define MASK_FLASH_NCR2_NWPRG    0x40
  1847. #define MASK_FLASH_NCR2_NOPT     0x80
  1848.  
  1849. #define MASK_FLASH_FPR_WPB0      0x01
  1850. #define MASK_FLASH_FPR_WPB1      0x02
  1851. #define MASK_FLASH_FPR_WPB2      0x04
  1852. #define MASK_FLASH_FPR_WPB3      0x08
  1853. #define MASK_FLASH_FPR_WPB4      0x10
  1854. #define MASK_FLASH_FPR_WPB5      0x20
  1855.  
  1856. #define MASK_FLASH_NFPR_NWPB0    0x01
  1857. #define MASK_FLASH_NFPR_NWPB1    0x02
  1858. #define MASK_FLASH_NFPR_NWPB2    0x04
  1859. #define MASK_FLASH_NFPR_NWPB3    0x08
  1860. #define MASK_FLASH_NFPR_NWPB4    0x10
  1861. #define MASK_FLASH_NFPR_NWPB5    0x20
  1862.  
  1863. #define MASK_FLASH_IAPSR_WR_PG_DIS 0x01
  1864. #define MASK_FLASH_IAPSR_PUL     0x02
  1865. #define MASK_FLASH_IAPSR_EOP     0x04
  1866. #define MASK_FLASH_IAPSR_DUL     0x08
  1867. #define MASK_FLASH_IAPSR_HVOFF   0x40
  1868.  
  1869.  
  1870. /*-------------------------------------------------------------------------
  1871.  *      ITC - EXTI register definitions
  1872.  *-----------------------------------------------------------------------*/
  1873. /* External interrupt control register 1 */
  1874. #ifdef __IAR_SYSTEMS_ICC__
  1875. typedef struct
  1876. {
  1877.   unsigned char PAIS        : 2;
  1878.   unsigned char PBIS        : 2;
  1879.   unsigned char PCIS        : 2;
  1880.   unsigned char PDIS        : 2;
  1881. } __BITS_EXTI_CR1;
  1882. #endif
  1883. __IO_REG8_BIT(EXTI_CR1,    0x50A0, __READ_WRITE, __BITS_EXTI_CR1);
  1884.  
  1885. /* External interrupt control register 2 */
  1886. #ifdef __IAR_SYSTEMS_ICC__
  1887. typedef struct
  1888. {
  1889.   unsigned char PEIS        : 2;
  1890.   unsigned char TLIS        : 1;
  1891. } __BITS_EXTI_CR2;
  1892. #endif
  1893. __IO_REG8_BIT(EXTI_CR2,    0x50A1, __READ_WRITE, __BITS_EXTI_CR2);
  1894.  
  1895.  
  1896. /*-------------------------------------------------------------------------
  1897.  *      ITC - EXTI bit fields
  1898.  *-----------------------------------------------------------------------*/
  1899. #ifdef __IAR_SYSTEMS_ICC__
  1900.  
  1901. #define EXTI_CR1_PAIS            EXTI_CR1_bit.PAIS
  1902. #define EXTI_CR1_PBIS            EXTI_CR1_bit.PBIS
  1903. #define EXTI_CR1_PCIS            EXTI_CR1_bit.PCIS
  1904. #define EXTI_CR1_PDIS            EXTI_CR1_bit.PDIS
  1905.  
  1906. #define EXTI_CR2_PEIS            EXTI_CR2_bit.PEIS
  1907. #define EXTI_CR2_TLIS            EXTI_CR2_bit.TLIS
  1908.  
  1909. #endif
  1910.  
  1911. /*-------------------------------------------------------------------------
  1912.  *      ITC - EXTI bit masks
  1913.  *-----------------------------------------------------------------------*/
  1914. #define MASK_EXTI_CR1_PAIS       0x03
  1915. #define MASK_EXTI_CR1_PBIS       0x0C
  1916. #define MASK_EXTI_CR1_PCIS       0x30
  1917. #define MASK_EXTI_CR1_PDIS       0xC0
  1918.  
  1919. #define MASK_EXTI_CR2_PEIS       0x03
  1920. #define MASK_EXTI_CR2_TLIS       0x04
  1921.  
  1922.  
  1923. /*-------------------------------------------------------------------------
  1924.  *      RST register definitions
  1925.  *-----------------------------------------------------------------------*/
  1926. /* Reset status register */
  1927. #ifdef __IAR_SYSTEMS_ICC__
  1928. typedef struct
  1929. {
  1930.   unsigned char WWDGF       : 1;
  1931.   unsigned char IWDGF       : 1;
  1932.   unsigned char ILLOPF      : 1;
  1933.   unsigned char SWIMF       : 1;
  1934.   unsigned char EMCF        : 1;
  1935. } __BITS_RST_SR;
  1936. #endif
  1937. __IO_REG8_BIT(RST_SR,      0x50B3, __READ_WRITE, __BITS_RST_SR);
  1938.  
  1939.  
  1940. /*-------------------------------------------------------------------------
  1941.  *      RST bit fields
  1942.  *-----------------------------------------------------------------------*/
  1943. #ifdef __IAR_SYSTEMS_ICC__
  1944.  
  1945. #define RST_SR_WWDGF             RST_SR_bit.WWDGF
  1946. #define RST_SR_IWDGF             RST_SR_bit.IWDGF
  1947. #define RST_SR_ILLOPF            RST_SR_bit.ILLOPF
  1948. #define RST_SR_SWIMF             RST_SR_bit.SWIMF
  1949. #define RST_SR_EMCF              RST_SR_bit.EMCF
  1950.  
  1951. #endif
  1952.  
  1953. /*-------------------------------------------------------------------------
  1954.  *      RST bit masks
  1955.  *-----------------------------------------------------------------------*/
  1956. #define MASK_RST_SR_WWDGF        0x01
  1957. #define MASK_RST_SR_IWDGF        0x02
  1958. #define MASK_RST_SR_ILLOPF       0x04
  1959. #define MASK_RST_SR_SWIMF        0x08
  1960. #define MASK_RST_SR_EMCF         0x10
  1961.  
  1962.  
  1963. /*-------------------------------------------------------------------------
  1964.  *      CLK register definitions
  1965.  *-----------------------------------------------------------------------*/
  1966. /* Internal clock control register */
  1967. #ifdef __IAR_SYSTEMS_ICC__
  1968. typedef struct
  1969. {
  1970.   unsigned char HSIEN       : 1;
  1971.   unsigned char HSIRDY      : 1;
  1972.   unsigned char FHW         : 1;
  1973.   unsigned char LSIEN       : 1;
  1974.   unsigned char LSIRDY      : 1;
  1975.   unsigned char REGAH       : 1;
  1976. } __BITS_CLK_ICKR;
  1977. #endif
  1978. __IO_REG8_BIT(CLK_ICKR,    0x50C0, __READ_WRITE, __BITS_CLK_ICKR);
  1979.  
  1980. /* External clock control register */
  1981. #ifdef __IAR_SYSTEMS_ICC__
  1982. typedef struct
  1983. {
  1984.   unsigned char HSEEN       : 1;
  1985.   unsigned char HSERDY      : 1;
  1986. } __BITS_CLK_ECKR;
  1987. #endif
  1988. __IO_REG8_BIT(CLK_ECKR,    0x50C1, __READ_WRITE, __BITS_CLK_ECKR);
  1989.  
  1990. /* Clock master status register */
  1991. __IO_REG8    (CLK_CMSR,    0x50C3, __READ);
  1992. /* Clock master switch register */
  1993. __IO_REG8    (CLK_SWR,     0x50C4, __READ_WRITE);
  1994. /* Clock switch control register */
  1995. #ifdef __IAR_SYSTEMS_ICC__
  1996. typedef struct
  1997. {
  1998.   unsigned char SWBSY       : 1;
  1999.   unsigned char SWEN        : 1;
  2000.   unsigned char SWIEM       : 1;
  2001.   unsigned char SWIF        : 1;
  2002. } __BITS_CLK_SWCR;
  2003. #endif
  2004. __IO_REG8_BIT(CLK_SWCR,    0x50C5, __READ_WRITE, __BITS_CLK_SWCR);
  2005.  
  2006. /* Clock divider register */
  2007. #ifdef __IAR_SYSTEMS_ICC__
  2008. typedef struct
  2009. {
  2010.   unsigned char CPUDIV      : 3;
  2011.   unsigned char HSIDIV      : 2;
  2012. } __BITS_CLK_CKDIVR;
  2013. #endif
  2014. __IO_REG8_BIT(CLK_CKDIVR,  0x50C6, __READ_WRITE, __BITS_CLK_CKDIVR);
  2015.  
  2016. /* Peripheral clock gating register 1 */
  2017. __IO_REG8    (CLK_PCKENR1, 0x50C7, __READ_WRITE);
  2018. /* Clock security system register */
  2019. #ifdef __IAR_SYSTEMS_ICC__
  2020. typedef struct
  2021. {
  2022.   unsigned char CSSEN       : 1;
  2023.   unsigned char AUX         : 1;
  2024.   unsigned char CSSD        : 1;
  2025.   unsigned char CSSDIE      : 1;
  2026. } __BITS_CLK_CSSR;
  2027. #endif
  2028. __IO_REG8_BIT(CLK_CSSR,    0x50C8, __READ_WRITE, __BITS_CLK_CSSR);
  2029.  
  2030. /* Configurable clock control register */
  2031. #ifdef __IAR_SYSTEMS_ICC__
  2032. typedef struct
  2033. {
  2034.   unsigned char CCOEN       : 1;
  2035.   unsigned char CCOSEL      : 4;
  2036.   unsigned char CCORDY      : 1;
  2037.   unsigned char CC0BSY      : 1;
  2038. } __BITS_CLK_CCOR;
  2039. #endif
  2040. __IO_REG8_BIT(CLK_CCOR,    0x50C9, __READ_WRITE, __BITS_CLK_CCOR);
  2041.  
  2042. /* Peripheral clock gating register 2 */
  2043. __IO_REG8    (CLK_PCKENR2, 0x50CA, __READ_WRITE);
  2044. /* CAN clock control register */
  2045. #ifdef __IAR_SYSTEMS_ICC__
  2046. typedef struct
  2047. {
  2048.   unsigned char CANDIV      : 3;
  2049. } __BITS_CLK_CANCCR;
  2050. #endif
  2051. __IO_REG8_BIT(CLK_CANCCR,  0x50CB, __READ_WRITE, __BITS_CLK_CANCCR);
  2052.  
  2053. /* HSI clock calibration trimming register */
  2054. #ifdef __IAR_SYSTEMS_ICC__
  2055. typedef struct
  2056. {
  2057.   unsigned char HSITRIM     : 4;
  2058. } __BITS_CLK_HSITRIMR;
  2059. #endif
  2060. __IO_REG8_BIT(CLK_HSITRIMR, 0x50CC, __READ_WRITE, __BITS_CLK_HSITRIMR);
  2061.  
  2062. /* SWIM clock control register */
  2063. #ifdef __IAR_SYSTEMS_ICC__
  2064. typedef struct
  2065. {
  2066.   unsigned char SWIMCLK     : 1;
  2067. } __BITS_CLK_SWIMCCR;
  2068. #endif
  2069. __IO_REG8_BIT(CLK_SWIMCCR, 0x50CD, __READ_WRITE, __BITS_CLK_SWIMCCR);
  2070.  
  2071.  
  2072. /*-------------------------------------------------------------------------
  2073.  *      CLK bit fields
  2074.  *-----------------------------------------------------------------------*/
  2075. #ifdef __IAR_SYSTEMS_ICC__
  2076.  
  2077. #define CLK_ICKR_HSIEN           CLK_ICKR_bit.HSIEN
  2078. #define CLK_ICKR_HSIRDY          CLK_ICKR_bit.HSIRDY
  2079. #define CLK_ICKR_FHW             CLK_ICKR_bit.FHW
  2080. #define CLK_ICKR_LSIEN           CLK_ICKR_bit.LSIEN
  2081. #define CLK_ICKR_LSIRDY          CLK_ICKR_bit.LSIRDY
  2082. #define CLK_ICKR_REGAH           CLK_ICKR_bit.REGAH
  2083.  
  2084. #define CLK_ECKR_HSEEN           CLK_ECKR_bit.HSEEN
  2085. #define CLK_ECKR_HSERDY          CLK_ECKR_bit.HSERDY
  2086.  
  2087. #define CLK_SWCR_SWBSY           CLK_SWCR_bit.SWBSY
  2088. #define CLK_SWCR_SWEN            CLK_SWCR_bit.SWEN
  2089. #define CLK_SWCR_SWIEM           CLK_SWCR_bit.SWIEM
  2090. #define CLK_SWCR_SWIF            CLK_SWCR_bit.SWIF
  2091.  
  2092. #define CLK_CKDIVR_CPUDIV        CLK_CKDIVR_bit.CPUDIV
  2093. #define CLK_CKDIVR_HSIDIV        CLK_CKDIVR_bit.HSIDIV
  2094.  
  2095. #define CLK_CSSR_CSSEN           CLK_CSSR_bit.CSSEN
  2096. #define CLK_CSSR_AUX             CLK_CSSR_bit.AUX
  2097. #define CLK_CSSR_CSSD            CLK_CSSR_bit.CSSD
  2098. #define CLK_CSSR_CSSDIE          CLK_CSSR_bit.CSSDIE
  2099.  
  2100. #define CLK_CCOR_CCOEN           CLK_CCOR_bit.CCOEN
  2101. #define CLK_CCOR_CCOSEL          CLK_CCOR_bit.CCOSEL
  2102. #define CLK_CCOR_CCORDY          CLK_CCOR_bit.CCORDY
  2103. #define CLK_CCOR_CC0BSY          CLK_CCOR_bit.CC0BSY
  2104.  
  2105. #define CLK_CANCCR_CANDIV        CLK_CANCCR_bit.CANDIV
  2106.  
  2107. #define CLK_HSITRIMR_HSITRIM     CLK_HSITRIMR_bit.HSITRIM
  2108.  
  2109. #define CLK_SWIMCCR_SWIMCLK      CLK_SWIMCCR_bit.SWIMCLK
  2110.  
  2111. #endif
  2112.  
  2113. /*-------------------------------------------------------------------------
  2114.  *      CLK bit masks
  2115.  *-----------------------------------------------------------------------*/
  2116. #define MASK_CLK_ICKR_HSIEN      0x01
  2117. #define MASK_CLK_ICKR_HSIRDY     0x02
  2118. #define MASK_CLK_ICKR_FHW        0x04
  2119. #define MASK_CLK_ICKR_LSIEN      0x08
  2120. #define MASK_CLK_ICKR_LSIRDY     0x10
  2121. #define MASK_CLK_ICKR_REGAH      0x20
  2122.  
  2123. #define MASK_CLK_ECKR_HSEEN      0x01
  2124. #define MASK_CLK_ECKR_HSERDY     0x02
  2125.  
  2126. #define MASK_CLK_SWCR_SWBSY      0x01
  2127. #define MASK_CLK_SWCR_SWEN       0x02
  2128. #define MASK_CLK_SWCR_SWIEM      0x04
  2129. #define MASK_CLK_SWCR_SWIF       0x08
  2130.  
  2131. #define MASK_CLK_CKDIVR_CPUDIV   0x07
  2132. #define MASK_CLK_CKDIVR_HSIDIV   0x18
  2133.  
  2134. #define MASK_CLK_CSSR_CSSEN      0x01
  2135. #define MASK_CLK_CSSR_AUX        0x02
  2136. #define MASK_CLK_CSSR_CSSD       0x04
  2137. #define MASK_CLK_CSSR_CSSDIE     0x08
  2138.  
  2139. #define MASK_CLK_CCOR_CCOEN      0x01
  2140. #define MASK_CLK_CCOR_CCOSEL     0x1E
  2141. #define MASK_CLK_CCOR_CCORDY     0x20
  2142. #define MASK_CLK_CCOR_CC0BSY     0x40
  2143.  
  2144. #define MASK_CLK_CANCCR_CANDIV   0x07
  2145.  
  2146. #define MASK_CLK_HSITRIMR_HSITRIM 0x0F
  2147.  
  2148. #define MASK_CLK_SWIMCCR_SWIMCLK 0x01
  2149.  
  2150.  
  2151. /*-------------------------------------------------------------------------
  2152.  *      WWDG register definitions
  2153.  *-----------------------------------------------------------------------*/
  2154. /* WWDG control register */
  2155. #ifdef __IAR_SYSTEMS_ICC__
  2156. typedef struct
  2157. {
  2158.   unsigned char T0          : 1;
  2159.   unsigned char T1          : 1;
  2160.   unsigned char T2          : 1;
  2161.   unsigned char T3          : 1;
  2162.   unsigned char T4          : 1;
  2163.   unsigned char T5          : 1;
  2164.   unsigned char T6          : 1;
  2165.   unsigned char WDGA        : 1;
  2166. } __BITS_WWDG_CR;
  2167. #endif
  2168. __IO_REG8_BIT(WWDG_CR,     0x50D1, __READ_WRITE, __BITS_WWDG_CR);
  2169.  
  2170. /* WWDR window register */
  2171. #ifdef __IAR_SYSTEMS_ICC__
  2172. typedef struct
  2173. {
  2174.   unsigned char W0          : 1;
  2175.   unsigned char W1          : 1;
  2176.   unsigned char W2          : 1;
  2177.   unsigned char W3          : 1;
  2178.   unsigned char W4          : 1;
  2179.   unsigned char W5          : 1;
  2180.   unsigned char W6          : 1;
  2181. } __BITS_WWDG_WR;
  2182. #endif
  2183. __IO_REG8_BIT(WWDG_WR,     0x50D2, __READ_WRITE, __BITS_WWDG_WR);
  2184.  
  2185.  
  2186. /*-------------------------------------------------------------------------
  2187.  *      WWDG bit fields
  2188.  *-----------------------------------------------------------------------*/
  2189. #ifdef __IAR_SYSTEMS_ICC__
  2190.  
  2191. #define WWDG_CR_T0               WWDG_CR_bit.T0
  2192. #define WWDG_CR_T1               WWDG_CR_bit.T1
  2193. #define WWDG_CR_T2               WWDG_CR_bit.T2
  2194. #define WWDG_CR_T3               WWDG_CR_bit.T3
  2195. #define WWDG_CR_T4               WWDG_CR_bit.T4
  2196. #define WWDG_CR_T5               WWDG_CR_bit.T5
  2197. #define WWDG_CR_T6               WWDG_CR_bit.T6
  2198. #define WWDG_CR_WDGA             WWDG_CR_bit.WDGA
  2199.  
  2200. #define WWDG_WR_W0               WWDG_WR_bit.W0
  2201. #define WWDG_WR_W1               WWDG_WR_bit.W1
  2202. #define WWDG_WR_W2               WWDG_WR_bit.W2
  2203. #define WWDG_WR_W3               WWDG_WR_bit.W3
  2204. #define WWDG_WR_W4               WWDG_WR_bit.W4
  2205. #define WWDG_WR_W5               WWDG_WR_bit.W5
  2206. #define WWDG_WR_W6               WWDG_WR_bit.W6
  2207.  
  2208. #endif
  2209.  
  2210. /*-------------------------------------------------------------------------
  2211.  *      WWDG bit masks
  2212.  *-----------------------------------------------------------------------*/
  2213. #define MASK_WWDG_CR_T0          0x01
  2214. #define MASK_WWDG_CR_T1          0x02
  2215. #define MASK_WWDG_CR_T2          0x04
  2216. #define MASK_WWDG_CR_T3          0x08
  2217. #define MASK_WWDG_CR_T4          0x10
  2218. #define MASK_WWDG_CR_T5          0x20
  2219. #define MASK_WWDG_CR_T6          0x40
  2220. #define MASK_WWDG_CR_WDGA        0x80
  2221.  
  2222. #define MASK_WWDG_WR_W0          0x01
  2223. #define MASK_WWDG_WR_W1          0x02
  2224. #define MASK_WWDG_WR_W2          0x04
  2225. #define MASK_WWDG_WR_W3          0x08
  2226. #define MASK_WWDG_WR_W4          0x10
  2227. #define MASK_WWDG_WR_W5          0x20
  2228. #define MASK_WWDG_WR_W6          0x40
  2229.  
  2230.  
  2231. /*-------------------------------------------------------------------------
  2232.  *      IWDG register definitions
  2233.  *-----------------------------------------------------------------------*/
  2234. /* IWDG key register */
  2235. __IO_REG8    (IWDG_KR,     0x50E0, __WRITE);
  2236. /* IWDG prescaler register */
  2237. #ifdef __IAR_SYSTEMS_ICC__
  2238. typedef struct
  2239. {
  2240.   unsigned char PR          : 3;
  2241. } __BITS_IWDG_PR;
  2242. #endif
  2243. __IO_REG8_BIT(IWDG_PR,     0x50E1, __READ_WRITE, __BITS_IWDG_PR);
  2244.  
  2245. /* IWDG reload register */
  2246. __IO_REG8    (IWDG_RLR,    0x50E2, __READ_WRITE);
  2247.  
  2248. /*-------------------------------------------------------------------------
  2249.  *      IWDG bit fields
  2250.  *-----------------------------------------------------------------------*/
  2251. #ifdef __IAR_SYSTEMS_ICC__
  2252.  
  2253. #define IWDG_PR_PR               IWDG_PR_bit.PR
  2254.  
  2255. #endif
  2256.  
  2257. /*-------------------------------------------------------------------------
  2258.  *      IWDG bit masks
  2259.  *-----------------------------------------------------------------------*/
  2260. #define MASK_IWDG_PR_PR          0x07
  2261.  
  2262.  
  2263. /*-------------------------------------------------------------------------
  2264.  *      AWU register definitions
  2265.  *-----------------------------------------------------------------------*/
  2266. /* AWU control/status register 1 */
  2267. #ifdef __IAR_SYSTEMS_ICC__
  2268. typedef struct
  2269. {
  2270.   unsigned char MSR         : 1;
  2271.   unsigned char             : 3;
  2272.   unsigned char AWUEN       : 1;
  2273.   unsigned char AWUF        : 1;
  2274. } __BITS_AWU_CSR1;
  2275. #endif
  2276. __IO_REG8_BIT(AWU_CSR1,    0x50F0, __READ_WRITE, __BITS_AWU_CSR1);
  2277.  
  2278. /* AWU asynchronous prescaler buffer register */
  2279. #ifdef __IAR_SYSTEMS_ICC__
  2280. typedef struct
  2281. {
  2282.   unsigned char APR         : 6;
  2283. } __BITS_AWU_APR;
  2284. #endif
  2285. __IO_REG8_BIT(AWU_APR,     0x50F1, __READ_WRITE, __BITS_AWU_APR);
  2286.  
  2287. /* AWU timebase selection register */
  2288. #ifdef __IAR_SYSTEMS_ICC__
  2289. typedef struct
  2290. {
  2291.   unsigned char AWUTB       : 4;
  2292. } __BITS_AWU_TBR;
  2293. #endif
  2294. __IO_REG8_BIT(AWU_TBR,     0x50F2, __READ_WRITE, __BITS_AWU_TBR);
  2295.  
  2296.  
  2297. /*-------------------------------------------------------------------------
  2298.  *      AWU bit fields
  2299.  *-----------------------------------------------------------------------*/
  2300. #ifdef __IAR_SYSTEMS_ICC__
  2301.  
  2302. #define AWU_CSR1_MSR             AWU_CSR1_bit.MSR
  2303. #define AWU_CSR1_AWUEN           AWU_CSR1_bit.AWUEN
  2304. #define AWU_CSR1_AWUF            AWU_CSR1_bit.AWUF
  2305.  
  2306. #define AWU_APR_APR              AWU_APR_bit.APR
  2307.  
  2308. #define AWU_TBR_AWUTB            AWU_TBR_bit.AWUTB
  2309.  
  2310. #endif
  2311.  
  2312. /*-------------------------------------------------------------------------
  2313.  *      AWU bit masks
  2314.  *-----------------------------------------------------------------------*/
  2315. #define MASK_AWU_CSR1_MSR        0x01
  2316. #define MASK_AWU_CSR1_AWUEN      0x10
  2317. #define MASK_AWU_CSR1_AWUF       0x20
  2318.  
  2319. #define MASK_AWU_APR_APR         0x3F
  2320.  
  2321. #define MASK_AWU_TBR_AWUTB       0x0F
  2322.  
  2323.  
  2324. /*-------------------------------------------------------------------------
  2325.  *      BEEP register definitions
  2326.  *-----------------------------------------------------------------------*/
  2327. /* BEEP control/status register */
  2328. #ifdef __IAR_SYSTEMS_ICC__
  2329. typedef struct
  2330. {
  2331.   unsigned char BEEPDIV     : 5;
  2332.   unsigned char BEEPEN      : 1;
  2333.   unsigned char BEEPSEL     : 2;
  2334. } __BITS_BEEP_CSR;
  2335. #endif
  2336. __IO_REG8_BIT(BEEP_CSR,    0x50F3, __READ_WRITE, __BITS_BEEP_CSR);
  2337.  
  2338.  
  2339. /*-------------------------------------------------------------------------
  2340.  *      BEEP bit fields
  2341.  *-----------------------------------------------------------------------*/
  2342. #ifdef __IAR_SYSTEMS_ICC__
  2343.  
  2344. #define BEEP_CSR_BEEPDIV         BEEP_CSR_bit.BEEPDIV
  2345. #define BEEP_CSR_BEEPEN          BEEP_CSR_bit.BEEPEN
  2346. #define BEEP_CSR_BEEPSEL         BEEP_CSR_bit.BEEPSEL
  2347.  
  2348. #endif
  2349.  
  2350. /*-------------------------------------------------------------------------
  2351.  *      BEEP bit masks
  2352.  *-----------------------------------------------------------------------*/
  2353. #define MASK_BEEP_CSR_BEEPDIV    0x1F
  2354. #define MASK_BEEP_CSR_BEEPEN     0x20
  2355. #define MASK_BEEP_CSR_BEEPSEL    0xC0
  2356.  
  2357.  
  2358. /*-------------------------------------------------------------------------
  2359.  *      SPI register definitions
  2360.  *-----------------------------------------------------------------------*/
  2361. /* SPI control register 1 */
  2362. #ifdef __IAR_SYSTEMS_ICC__
  2363. typedef struct
  2364. {
  2365.   unsigned char CPHA        : 1;
  2366.   unsigned char CPOL        : 1;
  2367.   unsigned char MSTR        : 1;
  2368.   unsigned char BR          : 3;
  2369.   unsigned char SPE         : 1;
  2370.   unsigned char LSBFIRST    : 1;
  2371. } __BITS_SPI_CR1;
  2372. #endif
  2373. __IO_REG8_BIT(SPI_CR1,     0x5200, __READ_WRITE, __BITS_SPI_CR1);
  2374.  
  2375. /* SPI control register 2 */
  2376. #ifdef __IAR_SYSTEMS_ICC__
  2377. typedef struct
  2378. {
  2379.   unsigned char SSI         : 1;
  2380.   unsigned char SSM         : 1;
  2381.   unsigned char RXONLY      : 1;
  2382.   unsigned char             : 1;
  2383.   unsigned char CRCNEXT     : 1;
  2384.   unsigned char CECEN       : 1;
  2385.   unsigned char BDOE        : 1;
  2386.   unsigned char BDM         : 1;
  2387. } __BITS_SPI_CR2;
  2388. #endif
  2389. __IO_REG8_BIT(SPI_CR2,     0x5201, __READ_WRITE, __BITS_SPI_CR2);
  2390.  
  2391. /* SPI interrupt control register */
  2392. #ifdef __IAR_SYSTEMS_ICC__
  2393. typedef struct
  2394. {
  2395.   unsigned char             : 4;
  2396.   unsigned char WKIE        : 1;
  2397.   unsigned char ERRIE       : 1;
  2398.   unsigned char RXIE        : 1;
  2399.   unsigned char TXIE        : 1;
  2400. } __BITS_SPI_ICR;
  2401. #endif
  2402. __IO_REG8_BIT(SPI_ICR,     0x5202, __READ_WRITE, __BITS_SPI_ICR);
  2403.  
  2404. /* SPI status register */
  2405. #ifdef __IAR_SYSTEMS_ICC__
  2406. typedef struct
  2407. {
  2408.   unsigned char RXNE        : 1;
  2409.   unsigned char TXE         : 1;
  2410.   unsigned char             : 1;
  2411.   unsigned char WKUP        : 1;
  2412.   unsigned char CRCERR      : 1;
  2413.   unsigned char MODF        : 1;
  2414.   unsigned char OVR         : 1;
  2415.   unsigned char BSY         : 1;
  2416. } __BITS_SPI_SR;
  2417. #endif
  2418. __IO_REG8_BIT(SPI_SR,      0x5203, __READ_WRITE, __BITS_SPI_SR);
  2419.  
  2420. /* SPI data register */
  2421. __IO_REG8    (SPI_DR,      0x5204, __READ_WRITE);
  2422. /* SPI CRC polynomial register */
  2423. __IO_REG8    (SPI_CRCPR,   0x5205, __READ_WRITE);
  2424. /* SPI Rx CRC register */
  2425. __IO_REG8    (SPI_RXCRCR,  0x5206, __READ);
  2426. /* SPI Tx CRC register */
  2427. __IO_REG8    (SPI_TXCRCR,  0x5207, __READ);
  2428.  
  2429. /*-------------------------------------------------------------------------
  2430.  *      SPI bit fields
  2431.  *-----------------------------------------------------------------------*/
  2432. #ifdef __IAR_SYSTEMS_ICC__
  2433.  
  2434. #define SPI_CR1_CPHA             SPI_CR1_bit.CPHA
  2435. #define SPI_CR1_CPOL             SPI_CR1_bit.CPOL
  2436. #define SPI_CR1_MSTR             SPI_CR1_bit.MSTR
  2437. #define SPI_CR1_BR               SPI_CR1_bit.BR
  2438. #define SPI_CR1_SPE              SPI_CR1_bit.SPE
  2439. #define SPI_CR1_LSBFIRST         SPI_CR1_bit.LSBFIRST
  2440.  
  2441. #define SPI_CR2_SSI              SPI_CR2_bit.SSI
  2442. #define SPI_CR2_SSM              SPI_CR2_bit.SSM
  2443. #define SPI_CR2_RXONLY           SPI_CR2_bit.RXONLY
  2444. #define SPI_CR2_CRCNEXT          SPI_CR2_bit.CRCNEXT
  2445. #define SPI_CR2_CECEN            SPI_CR2_bit.CECEN
  2446. #define SPI_CR2_BDOE             SPI_CR2_bit.BDOE
  2447. #define SPI_CR2_BDM              SPI_CR2_bit.BDM
  2448.  
  2449. #define SPI_ICR_WKIE             SPI_ICR_bit.WKIE
  2450. #define SPI_ICR_ERRIE            SPI_ICR_bit.ERRIE
  2451. #define SPI_ICR_RXIE             SPI_ICR_bit.RXIE
  2452. #define SPI_ICR_TXIE             SPI_ICR_bit.TXIE
  2453.  
  2454. #define SPI_SR_RXNE              SPI_SR_bit.RXNE
  2455. #define SPI_SR_TXE               SPI_SR_bit.TXE
  2456. #define SPI_SR_WKUP              SPI_SR_bit.WKUP
  2457. #define SPI_SR_CRCERR            SPI_SR_bit.CRCERR
  2458. #define SPI_SR_MODF              SPI_SR_bit.MODF
  2459. #define SPI_SR_OVR               SPI_SR_bit.OVR
  2460. #define SPI_SR_BSY               SPI_SR_bit.BSY
  2461.  
  2462. #endif
  2463.  
  2464. /*-------------------------------------------------------------------------
  2465.  *      SPI bit masks
  2466.  *-----------------------------------------------------------------------*/
  2467. #define MASK_SPI_CR1_CPHA        0x01
  2468. #define MASK_SPI_CR1_CPOL        0x02
  2469. #define MASK_SPI_CR1_MSTR        0x04
  2470. #define MASK_SPI_CR1_BR          0x38
  2471. #define MASK_SPI_CR1_SPE         0x40
  2472. #define MASK_SPI_CR1_LSBFIRST    0x80
  2473.  
  2474. #define MASK_SPI_CR2_SSI         0x01
  2475. #define MASK_SPI_CR2_SSM         0x02
  2476. #define MASK_SPI_CR2_RXONLY      0x04
  2477. #define MASK_SPI_CR2_CRCNEXT     0x10
  2478. #define MASK_SPI_CR2_CECEN       0x20
  2479. #define MASK_SPI_CR2_BDOE        0x40
  2480. #define MASK_SPI_CR2_BDM         0x80
  2481.  
  2482. #define MASK_SPI_ICR_WKIE        0x10
  2483. #define MASK_SPI_ICR_ERRIE       0x20
  2484. #define MASK_SPI_ICR_RXIE        0x40
  2485. #define MASK_SPI_ICR_TXIE        0x80
  2486.  
  2487. #define MASK_SPI_SR_RXNE         0x01
  2488. #define MASK_SPI_SR_TXE          0x02
  2489. #define MASK_SPI_SR_WKUP         0x08
  2490. #define MASK_SPI_SR_CRCERR       0x10
  2491. #define MASK_SPI_SR_MODF         0x20
  2492. #define MASK_SPI_SR_OVR          0x40
  2493. #define MASK_SPI_SR_BSY          0x80
  2494.  
  2495.  
  2496. /*-------------------------------------------------------------------------
  2497.  *      I2C register definitions
  2498.  *-----------------------------------------------------------------------*/
  2499. /* I2C control register 1 */
  2500. #ifdef __IAR_SYSTEMS_ICC__
  2501. typedef struct
  2502. {
  2503.   unsigned char PE          : 1;
  2504.   unsigned char             : 5;
  2505.   unsigned char ENGC        : 1;
  2506.   unsigned char NOSTRETCH   : 1;
  2507. } __BITS_I2C_CR1;
  2508. #endif
  2509. __IO_REG8_BIT(I2C_CR1,     0x5210, __READ_WRITE, __BITS_I2C_CR1);
  2510.  
  2511. /* I2C control register 2 */
  2512. #ifdef __IAR_SYSTEMS_ICC__
  2513. typedef struct
  2514. {
  2515.   unsigned char START       : 1;
  2516.   unsigned char STOP        : 1;
  2517.   unsigned char ACK         : 1;
  2518.   unsigned char POS         : 1;
  2519.   unsigned char             : 3;
  2520.   unsigned char SWRST       : 1;
  2521. } __BITS_I2C_CR2;
  2522. #endif
  2523. __IO_REG8_BIT(I2C_CR2,     0x5211, __READ_WRITE, __BITS_I2C_CR2);
  2524.  
  2525. /* I2C frequency register */
  2526. #ifdef __IAR_SYSTEMS_ICC__
  2527. typedef struct
  2528. {
  2529.   unsigned char FREQ        : 6;
  2530. } __BITS_I2C_FREQR;
  2531. #endif
  2532. __IO_REG8_BIT(I2C_FREQR,   0x5212, __READ_WRITE, __BITS_I2C_FREQR);
  2533.  
  2534. /* I2C Own address register low */
  2535. #ifdef __IAR_SYSTEMS_ICC__
  2536. typedef struct
  2537. {
  2538.   unsigned char ADD0        : 1;
  2539.   unsigned char ADD         : 7;
  2540. } __BITS_I2C_OARL;
  2541. #endif
  2542. __IO_REG8_BIT(I2C_OARL,    0x5213, __READ_WRITE, __BITS_I2C_OARL);
  2543.  
  2544. /* I2C own address register high */
  2545. #ifdef __IAR_SYSTEMS_ICC__
  2546. typedef struct
  2547. {
  2548.   unsigned char             : 1;
  2549.   unsigned char ADD         : 2;
  2550.   unsigned char             : 3;
  2551.   unsigned char ADDCONF     : 1;
  2552.   unsigned char ADDMODE     : 1;
  2553. } __BITS_I2C_OARH;
  2554. #endif
  2555. __IO_REG8_BIT(I2C_OARH,    0x5214, __READ_WRITE, __BITS_I2C_OARH);
  2556.  
  2557. /* I2C data register */
  2558. __IO_REG8    (I2C_DR,      0x5216, __READ_WRITE);
  2559. /* I2C status register 1 */
  2560. #ifdef __IAR_SYSTEMS_ICC__
  2561. typedef struct
  2562. {
  2563.   unsigned char SB          : 1;
  2564.   unsigned char ADDR        : 1;
  2565.   unsigned char BTF         : 1;
  2566.   unsigned char ADD10       : 1;
  2567.   unsigned char STOPF       : 1;
  2568.   unsigned char             : 1;
  2569.   unsigned char RXNE        : 1;
  2570.   unsigned char TXE         : 1;
  2571. } __BITS_I2C_SR1;
  2572. #endif
  2573. __IO_REG8_BIT(I2C_SR1,     0x5217, __READ, __BITS_I2C_SR1);
  2574.  
  2575. /* I2C status register 2 */
  2576. #ifdef __IAR_SYSTEMS_ICC__
  2577. typedef struct
  2578. {
  2579.   unsigned char BERR        : 1;
  2580.   unsigned char ARLO        : 1;
  2581.   unsigned char AF          : 1;
  2582.   unsigned char OVR         : 1;
  2583.   unsigned char             : 1;
  2584.   unsigned char WUFH        : 1;
  2585. } __BITS_I2C_SR2;
  2586. #endif
  2587. __IO_REG8_BIT(I2C_SR2,     0x5218, __READ_WRITE, __BITS_I2C_SR2);
  2588.  
  2589. /* I2C status register 3 */
  2590. #ifdef __IAR_SYSTEMS_ICC__
  2591. typedef struct
  2592. {
  2593.   unsigned char MSL         : 1;
  2594.   unsigned char BUSY        : 1;
  2595.   unsigned char TRA         : 1;
  2596.   unsigned char             : 1;
  2597.   unsigned char GENCALL     : 1;
  2598. } __BITS_I2C_SR3;
  2599. #endif
  2600. __IO_REG8_BIT(I2C_SR3,     0x5219, __READ, __BITS_I2C_SR3);
  2601.  
  2602. /* I2C interrupt control register */
  2603. #ifdef __IAR_SYSTEMS_ICC__
  2604. typedef struct
  2605. {
  2606.   unsigned char ITERREN     : 1;
  2607.   unsigned char ITEVTEN     : 1;
  2608.   unsigned char ITBUFEN     : 1;
  2609. } __BITS_I2C_ITR;
  2610. #endif
  2611. __IO_REG8_BIT(I2C_ITR,     0x521A, __READ_WRITE, __BITS_I2C_ITR);
  2612.  
  2613. /* I2C clock control register low */
  2614. __IO_REG8    (I2C_CCRL,    0x521B, __READ_WRITE);
  2615. /* I2C clock control register high */
  2616. #ifdef __IAR_SYSTEMS_ICC__
  2617. typedef struct
  2618. {
  2619.   unsigned char CCR         : 4;
  2620.   unsigned char             : 2;
  2621.   unsigned char DUTY        : 1;
  2622.   unsigned char F_S         : 1;
  2623. } __BITS_I2C_CCRH;
  2624. #endif
  2625. __IO_REG8_BIT(I2C_CCRH,    0x521C, __READ_WRITE, __BITS_I2C_CCRH);
  2626.  
  2627. /* I2C TRISE register */
  2628. #ifdef __IAR_SYSTEMS_ICC__
  2629. typedef struct
  2630. {
  2631.   unsigned char TRISE       : 6;
  2632. } __BITS_I2C_TRISER;
  2633. #endif
  2634. __IO_REG8_BIT(I2C_TRISER,  0x521D, __READ_WRITE, __BITS_I2C_TRISER);
  2635.  
  2636. /* I2C packet error checking register */
  2637. __IO_REG8    (I2C_PECR,    0x521E, __READ_WRITE);
  2638.  
  2639. /*-------------------------------------------------------------------------
  2640.  *      I2C bit fields
  2641.  *-----------------------------------------------------------------------*/
  2642. #ifdef __IAR_SYSTEMS_ICC__
  2643.  
  2644. #define I2C_CR1_PE               I2C_CR1_bit.PE
  2645. #define I2C_CR1_ENGC             I2C_CR1_bit.ENGC
  2646. #define I2C_CR1_NOSTRETCH        I2C_CR1_bit.NOSTRETCH
  2647.  
  2648. #define I2C_CR2_START            I2C_CR2_bit.START
  2649. #define I2C_CR2_STOP             I2C_CR2_bit.STOP
  2650. #define I2C_CR2_ACK              I2C_CR2_bit.ACK
  2651. #define I2C_CR2_POS              I2C_CR2_bit.POS
  2652. #define I2C_CR2_SWRST            I2C_CR2_bit.SWRST
  2653.  
  2654. #define I2C_FREQR_FREQ           I2C_FREQR_bit.FREQ
  2655.  
  2656. #define I2C_OARL_ADD0            I2C_OARL_bit.ADD0
  2657. #define I2C_OARL_ADD             I2C_OARL_bit.ADD
  2658.  
  2659. #define I2C_OARH_ADD             I2C_OARH_bit.ADD
  2660. #define I2C_OARH_ADDCONF         I2C_OARH_bit.ADDCONF
  2661. #define I2C_OARH_ADDMODE         I2C_OARH_bit.ADDMODE
  2662.  
  2663. #define I2C_SR1_SB               I2C_SR1_bit.SB
  2664. #define I2C_SR1_ADDR             I2C_SR1_bit.ADDR
  2665. #define I2C_SR1_BTF              I2C_SR1_bit.BTF
  2666. #define I2C_SR1_ADD10            I2C_SR1_bit.ADD10
  2667. #define I2C_SR1_STOPF            I2C_SR1_bit.STOPF
  2668. #define I2C_SR1_RXNE             I2C_SR1_bit.RXNE
  2669. #define I2C_SR1_TXE              I2C_SR1_bit.TXE
  2670.  
  2671. #define I2C_SR2_BERR             I2C_SR2_bit.BERR
  2672. #define I2C_SR2_ARLO             I2C_SR2_bit.ARLO
  2673. #define I2C_SR2_AF               I2C_SR2_bit.AF
  2674. #define I2C_SR2_OVR              I2C_SR2_bit.OVR
  2675. #define I2C_SR2_WUFH             I2C_SR2_bit.WUFH
  2676.  
  2677. #define I2C_SR3_MSL              I2C_SR3_bit.MSL
  2678. #define I2C_SR3_BUSY             I2C_SR3_bit.BUSY
  2679. #define I2C_SR3_TRA              I2C_SR3_bit.TRA
  2680. #define I2C_SR3_GENCALL          I2C_SR3_bit.GENCALL
  2681.  
  2682. #define I2C_ITR_ITERREN          I2C_ITR_bit.ITERREN
  2683. #define I2C_ITR_ITEVTEN          I2C_ITR_bit.ITEVTEN
  2684. #define I2C_ITR_ITBUFEN          I2C_ITR_bit.ITBUFEN
  2685.  
  2686. #define I2C_CCRH_CCR             I2C_CCRH_bit.CCR
  2687. #define I2C_CCRH_DUTY            I2C_CCRH_bit.DUTY
  2688. #define I2C_CCRH_F_S             I2C_CCRH_bit.F_S
  2689.  
  2690. #define I2C_TRISER_TRISE         I2C_TRISER_bit.TRISE
  2691.  
  2692. #endif
  2693.  
  2694. /*-------------------------------------------------------------------------
  2695.  *      I2C bit masks
  2696.  *-----------------------------------------------------------------------*/
  2697. #define MASK_I2C_CR1_PE          0x01
  2698. #define MASK_I2C_CR1_ENGC        0x40
  2699. #define MASK_I2C_CR1_NOSTRETCH   0x80
  2700.  
  2701. #define MASK_I2C_CR2_START       0x01
  2702. #define MASK_I2C_CR2_STOP        0x02
  2703. #define MASK_I2C_CR2_ACK         0x04
  2704. #define MASK_I2C_CR2_POS         0x08
  2705. #define MASK_I2C_CR2_SWRST       0x80
  2706.  
  2707. #define MASK_I2C_FREQR_FREQ      0x3F
  2708.  
  2709. #define MASK_I2C_OARL_ADD0       0x01
  2710. #define MASK_I2C_OARL_ADD        0xFE
  2711.  
  2712. #define MASK_I2C_OARH_ADD        0x06
  2713. #define MASK_I2C_OARH_ADDCONF    0x40
  2714. #define MASK_I2C_OARH_ADDMODE    0x80
  2715.  
  2716. #define MASK_I2C_SR1_SB          0x01
  2717. #define MASK_I2C_SR1_ADDR        0x02
  2718. #define MASK_I2C_SR1_BTF         0x04
  2719. #define MASK_I2C_SR1_ADD10       0x08
  2720. #define MASK_I2C_SR1_STOPF       0x10
  2721. #define MASK_I2C_SR1_RXNE        0x40
  2722. #define MASK_I2C_SR1_TXE         0x80
  2723.  
  2724. #define MASK_I2C_SR2_BERR        0x01
  2725. #define MASK_I2C_SR2_ARLO        0x02
  2726. #define MASK_I2C_SR2_AF          0x04
  2727. #define MASK_I2C_SR2_OVR         0x08
  2728. #define MASK_I2C_SR2_WUFH        0x20
  2729.  
  2730. #define MASK_I2C_SR3_MSL         0x01
  2731. #define MASK_I2C_SR3_BUSY        0x02
  2732. #define MASK_I2C_SR3_TRA         0x04
  2733. #define MASK_I2C_SR3_GENCALL     0x10
  2734.  
  2735. #define MASK_I2C_ITR_ITERREN     0x01
  2736. #define MASK_I2C_ITR_ITEVTEN     0x02
  2737. #define MASK_I2C_ITR_ITBUFEN     0x04
  2738.  
  2739. #define MASK_I2C_CCRH_CCR        0x0F
  2740. #define MASK_I2C_CCRH_DUTY       0x40
  2741. #define MASK_I2C_CCRH_F_S        0x80
  2742.  
  2743. #define MASK_I2C_TRISER_TRISE    0x3F
  2744.  
  2745.  
  2746. /*-------------------------------------------------------------------------
  2747.  *      UART2 register definitions
  2748.  *-----------------------------------------------------------------------*/
  2749. /* UART2 status register */
  2750. #ifdef __IAR_SYSTEMS_ICC__
  2751. typedef struct
  2752. {
  2753.   unsigned char PE          : 1;
  2754.   unsigned char FE          : 1;
  2755.   unsigned char NF          : 1;
  2756.   unsigned char OR_LHE      : 1;
  2757.   unsigned char IDLE        : 1;
  2758.   unsigned char RXNE        : 1;
  2759.   unsigned char TC          : 1;
  2760.   unsigned char TXE         : 1;
  2761. } __BITS_UART2_SR;
  2762. #endif
  2763. __IO_REG8_BIT(UART2_SR,    0x5240, __READ_WRITE, __BITS_UART2_SR);
  2764.  
  2765. /* UART2 data register */
  2766. __IO_REG8    (UART2_DR,    0x5241, __READ_WRITE);
  2767. /* UART2 baud rate register 1 */
  2768. __IO_REG8    (UART2_BRR1,  0x5242, __READ_WRITE);
  2769. /* UART2 baud rate register 2 */
  2770. __IO_REG8    (UART2_BRR2,  0x5243, __READ_WRITE);
  2771. /* UART2 control register 1 */
  2772. #ifdef __IAR_SYSTEMS_ICC__
  2773. typedef struct
  2774. {
  2775.   unsigned char PIEN        : 1;
  2776.   unsigned char PS          : 1;
  2777.   unsigned char PCEN        : 1;
  2778.   unsigned char WAKE        : 1;
  2779.   unsigned char M           : 1;
  2780.   unsigned char UART0       : 1;
  2781.   unsigned char T8          : 1;
  2782.   unsigned char R8          : 1;
  2783. } __BITS_UART2_CR1;
  2784. #endif
  2785. __IO_REG8_BIT(UART2_CR1,   0x5244, __READ_WRITE, __BITS_UART2_CR1);
  2786.  
  2787. /* UART2 control register 2 */
  2788. #ifdef __IAR_SYSTEMS_ICC__
  2789. typedef struct
  2790. {
  2791.   unsigned char SBK         : 1;
  2792.   unsigned char RWU         : 1;
  2793.   unsigned char REN         : 1;
  2794.   unsigned char TEN         : 1;
  2795.   unsigned char ILIEN       : 1;
  2796.   unsigned char RIEN        : 1;
  2797.   unsigned char TCIEN       : 1;
  2798.   unsigned char TIEN        : 1;
  2799. } __BITS_UART2_CR2;
  2800. #endif
  2801. __IO_REG8_BIT(UART2_CR2,   0x5245, __READ_WRITE, __BITS_UART2_CR2);
  2802.  
  2803. /* UART2 control register 3 */
  2804. #ifdef __IAR_SYSTEMS_ICC__
  2805. typedef struct
  2806. {
  2807.   unsigned char LBCL        : 1;
  2808.   unsigned char CPHA        : 1;
  2809.   unsigned char CPOL        : 1;
  2810.   unsigned char CKEN        : 1;
  2811.   unsigned char STOP        : 2;
  2812.   unsigned char             : 1;
  2813.   unsigned char LINEN       : 1;
  2814. } __BITS_UART2_CR3;
  2815. #endif
  2816. __IO_REG8_BIT(UART2_CR3,   0x5246, __READ_WRITE, __BITS_UART2_CR3);
  2817.  
  2818. /* UART2 control register 4 */
  2819. #ifdef __IAR_SYSTEMS_ICC__
  2820. typedef struct
  2821. {
  2822.   unsigned char ADD         : 4;
  2823.   unsigned char LBDF        : 1;
  2824.   unsigned char LBDL        : 1;
  2825.   unsigned char LBDIEN      : 1;
  2826. } __BITS_UART2_CR4;
  2827. #endif
  2828. __IO_REG8_BIT(UART2_CR4,   0x5247, __READ_WRITE, __BITS_UART2_CR4);
  2829.  
  2830. /* UART2 control register 6 */
  2831. #ifdef __IAR_SYSTEMS_ICC__
  2832. typedef struct
  2833. {
  2834.   unsigned char LSF         : 1;
  2835.   unsigned char LHDF        : 1;
  2836.   unsigned char LHDIEN      : 1;
  2837.   unsigned char             : 1;
  2838.   unsigned char LASE        : 1;
  2839.   unsigned char LSLV        : 1;
  2840.   unsigned char             : 1;
  2841.   unsigned char LDUM        : 1;
  2842. } __BITS_UART2_CR6;
  2843. #endif
  2844. __IO_REG8_BIT(UART2_CR6,   0x5249, __READ_WRITE, __BITS_UART2_CR6);
  2845.  
  2846. /* UART2 guard time register */
  2847. __IO_REG8    (UART2_GTR,   0x524A, __READ_WRITE);
  2848. /* UART2 prescaler register */
  2849. __IO_REG8    (UART2_PSCR,  0x524B, __READ_WRITE);
  2850.  
  2851. /*-------------------------------------------------------------------------
  2852.  *      UART2 bit fields
  2853.  *-----------------------------------------------------------------------*/
  2854. #ifdef __IAR_SYSTEMS_ICC__
  2855.  
  2856. #define UART2_SR_PE              UART2_SR_bit.PE
  2857. #define UART2_SR_FE              UART2_SR_bit.FE
  2858. #define UART2_SR_NF              UART2_SR_bit.NF
  2859. #define UART2_SR_OR_LHE          UART2_SR_bit.OR_LHE
  2860. #define UART2_SR_IDLE            UART2_SR_bit.IDLE
  2861. #define UART2_SR_RXNE            UART2_SR_bit.RXNE
  2862. #define UART2_SR_TC              UART2_SR_bit.TC
  2863. #define UART2_SR_TXE             UART2_SR_bit.TXE
  2864.  
  2865. #define UART2_CR1_PIEN           UART2_CR1_bit.PIEN
  2866. #define UART2_CR1_PS             UART2_CR1_bit.PS
  2867. #define UART2_CR1_PCEN           UART2_CR1_bit.PCEN
  2868. #define UART2_CR1_WAKE           UART2_CR1_bit.WAKE
  2869. #define UART2_CR1_M              UART2_CR1_bit.M
  2870. #define UART2_CR1_UART0          UART2_CR1_bit.UART0
  2871. #define UART2_CR1_T8             UART2_CR1_bit.T8
  2872. #define UART2_CR1_R8             UART2_CR1_bit.R8
  2873.  
  2874. #define UART2_CR2_SBK            UART2_CR2_bit.SBK
  2875. #define UART2_CR2_RWU            UART2_CR2_bit.RWU
  2876. #define UART2_CR2_REN            UART2_CR2_bit.REN
  2877. #define UART2_CR2_TEN            UART2_CR2_bit.TEN
  2878. #define UART2_CR2_ILIEN          UART2_CR2_bit.ILIEN
  2879. #define UART2_CR2_RIEN           UART2_CR2_bit.RIEN
  2880. #define UART2_CR2_TCIEN          UART2_CR2_bit.TCIEN
  2881. #define UART2_CR2_TIEN           UART2_CR2_bit.TIEN
  2882.  
  2883. #define UART2_CR3_LBCL           UART2_CR3_bit.LBCL
  2884. #define UART2_CR3_CPHA           UART2_CR3_bit.CPHA
  2885. #define UART2_CR3_CPOL           UART2_CR3_bit.CPOL
  2886. #define UART2_CR3_CKEN           UART2_CR3_bit.CKEN
  2887. #define UART2_CR3_STOP           UART2_CR3_bit.STOP
  2888. #define UART2_CR3_LINEN          UART2_CR3_bit.LINEN
  2889.  
  2890. #define UART2_CR4_ADD            UART2_CR4_bit.ADD
  2891. #define UART2_CR4_LBDF           UART2_CR4_bit.LBDF
  2892. #define UART2_CR4_LBDL           UART2_CR4_bit.LBDL
  2893. #define UART2_CR4_LBDIEN         UART2_CR4_bit.LBDIEN
  2894.  
  2895. #define UART2_CR6_LSF            UART2_CR6_bit.LSF
  2896. #define UART2_CR6_LHDF           UART2_CR6_bit.LHDF
  2897. #define UART2_CR6_LHDIEN         UART2_CR6_bit.LHDIEN
  2898. #define UART2_CR6_LASE           UART2_CR6_bit.LASE
  2899. #define UART2_CR6_LSLV           UART2_CR6_bit.LSLV
  2900. #define UART2_CR6_LDUM           UART2_CR6_bit.LDUM
  2901.  
  2902. #endif
  2903.  
  2904. /*-------------------------------------------------------------------------
  2905.  *      UART2 bit masks
  2906.  *-----------------------------------------------------------------------*/
  2907. #define MASK_UART2_SR_PE         0x01
  2908. #define MASK_UART2_SR_FE         0x02
  2909. #define MASK_UART2_SR_NF         0x04
  2910. #define MASK_UART2_SR_OR_LHE     0x08
  2911. #define MASK_UART2_SR_IDLE       0x10
  2912. #define MASK_UART2_SR_RXNE       0x20
  2913. #define MASK_UART2_SR_TC         0x40
  2914. #define MASK_UART2_SR_TXE        0x80
  2915.  
  2916. #define MASK_UART2_CR1_PIEN      0x01
  2917. #define MASK_UART2_CR1_PS        0x02
  2918. #define MASK_UART2_CR1_PCEN      0x04
  2919. #define MASK_UART2_CR1_WAKE      0x08
  2920. #define MASK_UART2_CR1_M         0x10
  2921. #define MASK_UART2_CR1_UART0     0x20
  2922. #define MASK_UART2_CR1_T8        0x40
  2923. #define MASK_UART2_CR1_R8        0x80
  2924.  
  2925. #define MASK_UART2_CR2_SBK       0x01
  2926. #define MASK_UART2_CR2_RWU       0x02
  2927. #define MASK_UART2_CR2_REN       0x04
  2928. #define MASK_UART2_CR2_TEN       0x08
  2929. #define MASK_UART2_CR2_ILIEN     0x10
  2930. #define MASK_UART2_CR2_RIEN      0x20
  2931. #define MASK_UART2_CR2_TCIEN     0x40
  2932. #define MASK_UART2_CR2_TIEN      0x80
  2933.  
  2934. #define MASK_UART2_CR3_LBCL      0x01
  2935. #define MASK_UART2_CR3_CPHA      0x02
  2936. #define MASK_UART2_CR3_CPOL      0x04
  2937. #define MASK_UART2_CR3_CKEN      0x08
  2938. #define MASK_UART2_CR3_STOP      0x30
  2939. #define MASK_UART2_CR3_LINEN     0x80
  2940.  
  2941. #define MASK_UART2_CR4_ADD       0x0F
  2942. #define MASK_UART2_CR4_LBDF      0x10
  2943. #define MASK_UART2_CR4_LBDL      0x20
  2944. #define MASK_UART2_CR4_LBDIEN    0x40
  2945.  
  2946. #define MASK_UART2_CR6_LSF       0x01
  2947. #define MASK_UART2_CR6_LHDF      0x02
  2948. #define MASK_UART2_CR6_LHDIEN    0x04
  2949. #define MASK_UART2_CR6_LASE      0x10
  2950. #define MASK_UART2_CR6_LSLV      0x20
  2951. #define MASK_UART2_CR6_LDUM      0x80
  2952.  
  2953.  
  2954. /*-------------------------------------------------------------------------
  2955.  *      TIM1 register definitions
  2956.  *-----------------------------------------------------------------------*/
  2957. /* TIM1 control register 1 */
  2958. #ifdef __IAR_SYSTEMS_ICC__
  2959. typedef struct
  2960. {
  2961.   unsigned char CEN         : 1;
  2962.   unsigned char UDIS        : 1;
  2963.   unsigned char URS         : 1;
  2964.   unsigned char OPM         : 1;
  2965.   unsigned char DIR         : 1;
  2966.   unsigned char CMS         : 2;
  2967.   unsigned char ARPE        : 1;
  2968. } __BITS_TIM1_CR1;
  2969. #endif
  2970. __IO_REG8_BIT(TIM1_CR1,    0x5250, __READ_WRITE, __BITS_TIM1_CR1);
  2971.  
  2972. /* TIM1 control register 2 */
  2973. #ifdef __IAR_SYSTEMS_ICC__
  2974. typedef struct
  2975. {
  2976.   unsigned char CCPG        : 1;
  2977.   unsigned char             : 1;
  2978.   unsigned char COMS        : 1;
  2979.   unsigned char             : 1;
  2980.   unsigned char MMS         : 3;
  2981. } __BITS_TIM1_CR2;
  2982. #endif
  2983. __IO_REG8_BIT(TIM1_CR2,    0x5251, __READ_WRITE, __BITS_TIM1_CR2);
  2984.  
  2985. /* TIM1 slave mode control register */
  2986. #ifdef __IAR_SYSTEMS_ICC__
  2987. typedef struct
  2988. {
  2989.   unsigned char SMS         : 3;
  2990.   unsigned char             : 1;
  2991.   unsigned char TS          : 3;
  2992.   unsigned char MSM         : 1;
  2993. } __BITS_TIM1_SMCR;
  2994. #endif
  2995. __IO_REG8_BIT(TIM1_SMCR,   0x5252, __READ_WRITE, __BITS_TIM1_SMCR);
  2996.  
  2997. /* TIM1 external trigger register */
  2998. #ifdef __IAR_SYSTEMS_ICC__
  2999. typedef struct
  3000. {
  3001.   unsigned char ETF         : 4;
  3002.   unsigned char ETPS        : 2;
  3003.   unsigned char ECE         : 1;
  3004.   unsigned char ETP         : 1;
  3005. } __BITS_TIM1_ETR;
  3006. #endif
  3007. __IO_REG8_BIT(TIM1_ETR,    0x5253, __READ_WRITE, __BITS_TIM1_ETR);
  3008.  
  3009. /* TIM1 interrupt enable register */
  3010. #ifdef __IAR_SYSTEMS_ICC__
  3011. typedef struct
  3012. {
  3013.   unsigned char UIE         : 1;
  3014.   unsigned char CC1IE       : 1;
  3015.   unsigned char CC2IE       : 1;
  3016.   unsigned char CC3IE       : 1;
  3017.   unsigned char CC4IE       : 1;
  3018.   unsigned char COMIE       : 1;
  3019.   unsigned char TIE         : 1;
  3020.   unsigned char BIE         : 1;
  3021. } __BITS_TIM1_IER;
  3022. #endif
  3023. __IO_REG8_BIT(TIM1_IER,    0x5254, __READ_WRITE, __BITS_TIM1_IER);
  3024.  
  3025. /* TIM1 status register 1 */
  3026. #ifdef __IAR_SYSTEMS_ICC__
  3027. typedef struct
  3028. {
  3029.   unsigned char UIF         : 1;
  3030.   unsigned char CC1IF       : 1;
  3031.   unsigned char CC2IF       : 1;
  3032.   unsigned char CC3IF       : 1;
  3033.   unsigned char CC4IF       : 1;
  3034.   unsigned char COMIF       : 1;
  3035.   unsigned char TIF         : 1;
  3036.   unsigned char BIF         : 1;
  3037. } __BITS_TIM1_SR1;
  3038. #endif
  3039. __IO_REG8_BIT(TIM1_SR1,    0x5255, __READ_WRITE, __BITS_TIM1_SR1);
  3040.  
  3041. /* TIM1 status register 2 */
  3042. #ifdef __IAR_SYSTEMS_ICC__
  3043. typedef struct
  3044. {
  3045.   unsigned char             : 1;
  3046.   unsigned char CC1OF       : 1;
  3047.   unsigned char CC2OF       : 1;
  3048.   unsigned char CC3OF       : 1;
  3049.   unsigned char CC4OF       : 1;
  3050. } __BITS_TIM1_SR2;
  3051. #endif
  3052. __IO_REG8_BIT(TIM1_SR2,    0x5256, __READ_WRITE, __BITS_TIM1_SR2);
  3053.  
  3054. /* TIM1 event generation register */
  3055. #ifdef __IAR_SYSTEMS_ICC__
  3056. typedef struct
  3057. {
  3058.   unsigned char UG          : 1;
  3059.   unsigned char CC1G        : 1;
  3060.   unsigned char CC2G        : 1;
  3061.   unsigned char CC3G        : 1;
  3062.   unsigned char CC4G        : 1;
  3063.   unsigned char COMG        : 1;
  3064.   unsigned char TG          : 1;
  3065.   unsigned char BG          : 1;
  3066. } __BITS_TIM1_EGR;
  3067. #endif
  3068. __IO_REG8_BIT(TIM1_EGR,    0x5257, __WRITE, __BITS_TIM1_EGR);
  3069.  
  3070. /* TIM1 capture/compare mode register 1 */
  3071. #ifdef __IAR_SYSTEMS_ICC__
  3072. typedef struct
  3073. {
  3074.   unsigned char CC1S        : 2;
  3075.   unsigned char OC1FE       : 1;
  3076.   unsigned char OC1PE       : 1;
  3077.   unsigned char OC1M        : 3;
  3078.   unsigned char OC1CE       : 1;
  3079. } __BITS_TIM1_CCMR1;
  3080. #endif
  3081. __IO_REG8_BIT(TIM1_CCMR1,  0x5258, __READ_WRITE, __BITS_TIM1_CCMR1);
  3082.  
  3083. /* TIM1 capture/compare mode register 2 */
  3084. #ifdef __IAR_SYSTEMS_ICC__
  3085. typedef struct
  3086. {
  3087.   unsigned char CC2S        : 2;
  3088.   unsigned char OC2FE       : 1;
  3089.   unsigned char OC2PE       : 1;
  3090.   unsigned char OC2M        : 3;
  3091.   unsigned char OC2CE       : 1;
  3092. } __BITS_TIM1_CCMR2;
  3093. #endif
  3094. __IO_REG8_BIT(TIM1_CCMR2,  0x5259, __READ_WRITE, __BITS_TIM1_CCMR2);
  3095.  
  3096. /* TIM1 capture/compare mode register 3 */
  3097. #ifdef __IAR_SYSTEMS_ICC__
  3098. typedef struct
  3099. {
  3100.   unsigned char CC3S        : 2;
  3101.   unsigned char OC3FE       : 1;
  3102.   unsigned char OC3PE       : 1;
  3103.   unsigned char OC3M        : 3;
  3104.   unsigned char OC3CE       : 1;
  3105. } __BITS_TIM1_CCMR3;
  3106. #endif
  3107. __IO_REG8_BIT(TIM1_CCMR3,  0x525A, __READ_WRITE, __BITS_TIM1_CCMR3);
  3108.  
  3109. /* TIM1 capture/compare mode register 4 */
  3110. #ifdef __IAR_SYSTEMS_ICC__
  3111. typedef struct
  3112. {
  3113.   unsigned char CC4S        : 2;
  3114.   unsigned char OC4FE       : 1;
  3115.   unsigned char OC4PE       : 1;
  3116.   unsigned char OC4M        : 3;
  3117.   unsigned char OC4CE       : 1;
  3118. } __BITS_TIM1_CCMR4;
  3119. #endif
  3120. __IO_REG8_BIT(TIM1_CCMR4,  0x525B, __READ_WRITE, __BITS_TIM1_CCMR4);
  3121.  
  3122. /* TIM1 capture/compare enable register 1 */
  3123. #ifdef __IAR_SYSTEMS_ICC__
  3124. typedef struct
  3125. {
  3126.   unsigned char CC1E        : 1;
  3127.   unsigned char CC1P        : 1;
  3128.   unsigned char CC1NE       : 1;
  3129.   unsigned char CC1NP       : 1;
  3130.   unsigned char CC2E        : 1;
  3131.   unsigned char CC2P        : 1;
  3132.   unsigned char CC2NE       : 1;
  3133.   unsigned char CC2NP       : 1;
  3134. } __BITS_TIM1_CCER1;
  3135. #endif
  3136. __IO_REG8_BIT(TIM1_CCER1,  0x525C, __READ_WRITE, __BITS_TIM1_CCER1);
  3137.  
  3138. /* TIM1 capture/compare enable register 2 */
  3139. #ifdef __IAR_SYSTEMS_ICC__
  3140. typedef struct
  3141. {
  3142.   unsigned char CC3E        : 1;
  3143.   unsigned char CC3P        : 1;
  3144.   unsigned char CC3NE       : 1;
  3145.   unsigned char CC3NP       : 1;
  3146.   unsigned char CC4E        : 1;
  3147.   unsigned char CC4P        : 1;
  3148. } __BITS_TIM1_CCER2;
  3149. #endif
  3150. __IO_REG8_BIT(TIM1_CCER2,  0x525D, __READ_WRITE, __BITS_TIM1_CCER2);
  3151.  
  3152. /* TIM1 counter high */
  3153. __IO_REG8    (TIM1_CNTRH,  0x525E, __READ_WRITE);
  3154. /* TIM1 counter low */
  3155. __IO_REG8    (TIM1_CNTRL,  0x525F, __READ_WRITE);
  3156. /* TIM1 prescaler register high */
  3157. __IO_REG8    (TIM1_PSCRH,  0x5260, __READ_WRITE);
  3158. /* TIM1 prescaler register low */
  3159. __IO_REG8    (TIM1_PSCRL,  0x5261, __READ_WRITE);
  3160. /* TIM1 auto-reload register high */
  3161. __IO_REG8    (TIM1_ARRH,   0x5262, __READ_WRITE);
  3162. /* TIM1 auto-reload register low */
  3163. __IO_REG8    (TIM1_ARRL,   0x5263, __READ_WRITE);
  3164. /* TIM1 repetition counter register */
  3165. __IO_REG8    (TIM1_RCR,    0x5264, __READ_WRITE);
  3166. /* TIM1 capture/compare register 1 high */
  3167. __IO_REG8    (TIM1_CCR1H,  0x5265, __READ_WRITE);
  3168. /* TIM1 capture/compare register 1 low */
  3169. __IO_REG8    (TIM1_CCR1L,  0x5266, __READ_WRITE);
  3170. /* TIM1 capture/compare register 2 high */
  3171. __IO_REG8    (TIM1_CCR2H,  0x5267, __READ_WRITE);
  3172. /* TIM1 capture/compare register 2 low */
  3173. __IO_REG8    (TIM1_CCR2L,  0x5268, __READ_WRITE);
  3174. /* TIM1 capture/compare register 3 high */
  3175. __IO_REG8    (TIM1_CCR3H,  0x5269, __READ_WRITE);
  3176. /* TIM1 capture/compare register 3 low */
  3177. __IO_REG8    (TIM1_CCR3L,  0x526A, __READ_WRITE);
  3178. /* TIM1 capture/compare register 4 high */
  3179. __IO_REG8    (TIM1_CCR4H,  0x526B, __READ_WRITE);
  3180. /* TIM1 capture/compare register 4 low */
  3181. __IO_REG8    (TIM1_CCR4L,  0x526C, __READ_WRITE);
  3182. /* TIM1 break register */
  3183. #ifdef __IAR_SYSTEMS_ICC__
  3184. typedef struct
  3185. {
  3186.   unsigned char LOCK        : 2;
  3187.   unsigned char OSSI        : 1;
  3188.   unsigned char OSSR        : 1;
  3189.   unsigned char BKE         : 1;
  3190.   unsigned char BKP         : 1;
  3191.   unsigned char AOE         : 1;
  3192.   unsigned char MOE         : 1;
  3193. } __BITS_TIM1_BKR;
  3194. #endif
  3195. __IO_REG8_BIT(TIM1_BKR,    0x526D, __READ_WRITE, __BITS_TIM1_BKR);
  3196.  
  3197. /* TIM1 dead-time register */
  3198. __IO_REG8    (TIM1_DTR,    0x526E, __READ_WRITE);
  3199. /* TIM1 output idle state register */
  3200. #ifdef __IAR_SYSTEMS_ICC__
  3201. typedef struct
  3202. {
  3203.   unsigned char OIS1        : 1;
  3204.   unsigned char OIS1N       : 1;
  3205.   unsigned char OIS2        : 1;
  3206.   unsigned char OIS2N       : 1;
  3207.   unsigned char OIS3        : 1;
  3208.   unsigned char OIS3N       : 1;
  3209.   unsigned char OIS4        : 1;
  3210. } __BITS_TIM1_OISR;
  3211. #endif
  3212. __IO_REG8_BIT(TIM1_OISR,   0x526F, __READ_WRITE, __BITS_TIM1_OISR);
  3213.  
  3214.  
  3215. /*-------------------------------------------------------------------------
  3216.  *      TIM1 bit fields
  3217.  *-----------------------------------------------------------------------*/
  3218. #ifdef __IAR_SYSTEMS_ICC__
  3219.  
  3220. #define TIM1_CR1_CEN             TIM1_CR1_bit.CEN
  3221. #define TIM1_CR1_UDIS            TIM1_CR1_bit.UDIS
  3222. #define TIM1_CR1_URS             TIM1_CR1_bit.URS
  3223. #define TIM1_CR1_OPM             TIM1_CR1_bit.OPM
  3224. #define TIM1_CR1_DIR             TIM1_CR1_bit.DIR
  3225. #define TIM1_CR1_CMS             TIM1_CR1_bit.CMS
  3226. #define TIM1_CR1_ARPE            TIM1_CR1_bit.ARPE
  3227.  
  3228. #define TIM1_CR2_CCPG            TIM1_CR2_bit.CCPG
  3229. #define TIM1_CR2_COMS            TIM1_CR2_bit.COMS
  3230. #define TIM1_CR2_MMS             TIM1_CR2_bit.MMS
  3231.  
  3232. #define TIM1_SMCR_SMS            TIM1_SMCR_bit.SMS
  3233. #define TIM1_SMCR_TS             TIM1_SMCR_bit.TS
  3234. #define TIM1_SMCR_MSM            TIM1_SMCR_bit.MSM
  3235.  
  3236. #define TIM1_ETR_ETF             TIM1_ETR_bit.ETF
  3237. #define TIM1_ETR_ETPS            TIM1_ETR_bit.ETPS
  3238. #define TIM1_ETR_ECE             TIM1_ETR_bit.ECE
  3239. #define TIM1_ETR_ETP             TIM1_ETR_bit.ETP
  3240.  
  3241. #define TIM1_IER_UIE             TIM1_IER_bit.UIE
  3242. #define TIM1_IER_CC1IE           TIM1_IER_bit.CC1IE
  3243. #define TIM1_IER_CC2IE           TIM1_IER_bit.CC2IE
  3244. #define TIM1_IER_CC3IE           TIM1_IER_bit.CC3IE
  3245. #define TIM1_IER_CC4IE           TIM1_IER_bit.CC4IE
  3246. #define TIM1_IER_COMIE           TIM1_IER_bit.COMIE
  3247. #define TIM1_IER_TIE             TIM1_IER_bit.TIE
  3248. #define TIM1_IER_BIE             TIM1_IER_bit.BIE
  3249.  
  3250. #define TIM1_SR1_UIF             TIM1_SR1_bit.UIF
  3251. #define TIM1_SR1_CC1IF           TIM1_SR1_bit.CC1IF
  3252. #define TIM1_SR1_CC2IF           TIM1_SR1_bit.CC2IF
  3253. #define TIM1_SR1_CC3IF           TIM1_SR1_bit.CC3IF
  3254. #define TIM1_SR1_CC4IF           TIM1_SR1_bit.CC4IF
  3255. #define TIM1_SR1_COMIF           TIM1_SR1_bit.COMIF
  3256. #define TIM1_SR1_TIF             TIM1_SR1_bit.TIF
  3257. #define TIM1_SR1_BIF             TIM1_SR1_bit.BIF
  3258.  
  3259. #define TIM1_SR2_CC1OF           TIM1_SR2_bit.CC1OF
  3260. #define TIM1_SR2_CC2OF           TIM1_SR2_bit.CC2OF
  3261. #define TIM1_SR2_CC3OF           TIM1_SR2_bit.CC3OF
  3262. #define TIM1_SR2_CC4OF           TIM1_SR2_bit.CC4OF
  3263.  
  3264. #define TIM1_EGR_UG              TIM1_EGR_bit.UG
  3265. #define TIM1_EGR_CC1G            TIM1_EGR_bit.CC1G
  3266. #define TIM1_EGR_CC2G            TIM1_EGR_bit.CC2G
  3267. #define TIM1_EGR_CC3G            TIM1_EGR_bit.CC3G
  3268. #define TIM1_EGR_CC4G            TIM1_EGR_bit.CC4G
  3269. #define TIM1_EGR_COMG            TIM1_EGR_bit.COMG
  3270. #define TIM1_EGR_TG              TIM1_EGR_bit.TG
  3271. #define TIM1_EGR_BG              TIM1_EGR_bit.BG
  3272.  
  3273. #define TIM1_CCMR1_CC1S          TIM1_CCMR1_bit.CC1S
  3274. #define TIM1_CCMR1_OC1FE         TIM1_CCMR1_bit.OC1FE
  3275. #define TIM1_CCMR1_OC1PE         TIM1_CCMR1_bit.OC1PE
  3276. #define TIM1_CCMR1_OC1M          TIM1_CCMR1_bit.OC1M
  3277. #define TIM1_CCMR1_OC1CE         TIM1_CCMR1_bit.OC1CE
  3278.  
  3279. #define TIM1_CCMR2_CC2S          TIM1_CCMR2_bit.CC2S
  3280. #define TIM1_CCMR2_OC2FE         TIM1_CCMR2_bit.OC2FE
  3281. #define TIM1_CCMR2_OC2PE         TIM1_CCMR2_bit.OC2PE
  3282. #define TIM1_CCMR2_OC2M          TIM1_CCMR2_bit.OC2M
  3283. #define TIM1_CCMR2_OC2CE         TIM1_CCMR2_bit.OC2CE
  3284.  
  3285. #define TIM1_CCMR3_CC3S          TIM1_CCMR3_bit.CC3S
  3286. #define TIM1_CCMR3_OC3FE         TIM1_CCMR3_bit.OC3FE
  3287. #define TIM1_CCMR3_OC3PE         TIM1_CCMR3_bit.OC3PE
  3288. #define TIM1_CCMR3_OC3M          TIM1_CCMR3_bit.OC3M
  3289. #define TIM1_CCMR3_OC3CE         TIM1_CCMR3_bit.OC3CE
  3290.  
  3291. #define TIM1_CCMR4_CC4S          TIM1_CCMR4_bit.CC4S
  3292. #define TIM1_CCMR4_OC4FE         TIM1_CCMR4_bit.OC4FE
  3293. #define TIM1_CCMR4_OC4PE         TIM1_CCMR4_bit.OC4PE
  3294. #define TIM1_CCMR4_OC4M          TIM1_CCMR4_bit.OC4M
  3295. #define TIM1_CCMR4_OC4CE         TIM1_CCMR4_bit.OC4CE
  3296.  
  3297. #define TIM1_CCER1_CC1E          TIM1_CCER1_bit.CC1E
  3298. #define TIM1_CCER1_CC1P          TIM1_CCER1_bit.CC1P
  3299. #define TIM1_CCER1_CC1NE         TIM1_CCER1_bit.CC1NE
  3300. #define TIM1_CCER1_CC1NP         TIM1_CCER1_bit.CC1NP
  3301. #define TIM1_CCER1_CC2E          TIM1_CCER1_bit.CC2E
  3302. #define TIM1_CCER1_CC2P          TIM1_CCER1_bit.CC2P
  3303. #define TIM1_CCER1_CC2NE         TIM1_CCER1_bit.CC2NE
  3304. #define TIM1_CCER1_CC2NP         TIM1_CCER1_bit.CC2NP
  3305.  
  3306. #define TIM1_CCER2_CC3E          TIM1_CCER2_bit.CC3E
  3307. #define TIM1_CCER2_CC3P          TIM1_CCER2_bit.CC3P
  3308. #define TIM1_CCER2_CC3NE         TIM1_CCER2_bit.CC3NE
  3309. #define TIM1_CCER2_CC3NP         TIM1_CCER2_bit.CC3NP
  3310. #define TIM1_CCER2_CC4E          TIM1_CCER2_bit.CC4E
  3311. #define TIM1_CCER2_CC4P          TIM1_CCER2_bit.CC4P
  3312.  
  3313. #define TIM1_BKR_LOCK            TIM1_BKR_bit.LOCK
  3314. #define TIM1_BKR_OSSI            TIM1_BKR_bit.OSSI
  3315. #define TIM1_BKR_OSSR            TIM1_BKR_bit.OSSR
  3316. #define TIM1_BKR_BKE             TIM1_BKR_bit.BKE
  3317. #define TIM1_BKR_BKP             TIM1_BKR_bit.BKP
  3318. #define TIM1_BKR_AOE             TIM1_BKR_bit.AOE
  3319. #define TIM1_BKR_MOE             TIM1_BKR_bit.MOE
  3320.  
  3321. #define TIM1_OISR_OIS1           TIM1_OISR_bit.OIS1
  3322. #define TIM1_OISR_OIS1N          TIM1_OISR_bit.OIS1N
  3323. #define TIM1_OISR_OIS2           TIM1_OISR_bit.OIS2
  3324. #define TIM1_OISR_OIS2N          TIM1_OISR_bit.OIS2N
  3325. #define TIM1_OISR_OIS3           TIM1_OISR_bit.OIS3
  3326. #define TIM1_OISR_OIS3N          TIM1_OISR_bit.OIS3N
  3327. #define TIM1_OISR_OIS4           TIM1_OISR_bit.OIS4
  3328.  
  3329. #endif
  3330.  
  3331. /*-------------------------------------------------------------------------
  3332.  *      TIM1 bit masks
  3333.  *-----------------------------------------------------------------------*/
  3334. #define MASK_TIM1_CR1_CEN        0x01
  3335. #define MASK_TIM1_CR1_UDIS       0x02
  3336. #define MASK_TIM1_CR1_URS        0x04
  3337. #define MASK_TIM1_CR1_OPM        0x08
  3338. #define MASK_TIM1_CR1_DIR        0x10
  3339. #define MASK_TIM1_CR1_CMS        0x60
  3340. #define MASK_TIM1_CR1_ARPE       0x80
  3341.  
  3342. #define MASK_TIM1_CR2_CCPG       0x01
  3343. #define MASK_TIM1_CR2_COMS       0x04
  3344. #define MASK_TIM1_CR2_MMS        0x70
  3345.  
  3346. #define MASK_TIM1_SMCR_SMS       0x07
  3347. #define MASK_TIM1_SMCR_TS        0x70
  3348. #define MASK_TIM1_SMCR_MSM       0x80
  3349.  
  3350. #define MASK_TIM1_ETR_ETF        0x0F
  3351. #define MASK_TIM1_ETR_ETPS       0x30
  3352. #define MASK_TIM1_ETR_ECE        0x40
  3353. #define MASK_TIM1_ETR_ETP        0x80
  3354.  
  3355. #define MASK_TIM1_IER_UIE        0x01
  3356. #define MASK_TIM1_IER_CC1IE      0x02
  3357. #define MASK_TIM1_IER_CC2IE      0x04
  3358. #define MASK_TIM1_IER_CC3IE      0x08
  3359. #define MASK_TIM1_IER_CC4IE      0x10
  3360. #define MASK_TIM1_IER_COMIE      0x20
  3361. #define MASK_TIM1_IER_TIE        0x40
  3362. #define MASK_TIM1_IER_BIE        0x80
  3363.  
  3364. #define MASK_TIM1_SR1_UIF        0x01
  3365. #define MASK_TIM1_SR1_CC1IF      0x02
  3366. #define MASK_TIM1_SR1_CC2IF      0x04
  3367. #define MASK_TIM1_SR1_CC3IF      0x08
  3368. #define MASK_TIM1_SR1_CC4IF      0x10
  3369. #define MASK_TIM1_SR1_COMIF      0x20
  3370. #define MASK_TIM1_SR1_TIF        0x40
  3371. #define MASK_TIM1_SR1_BIF        0x80
  3372.  
  3373. #define MASK_TIM1_SR2_CC1OF      0x02
  3374. #define MASK_TIM1_SR2_CC2OF      0x04
  3375. #define MASK_TIM1_SR2_CC3OF      0x08
  3376. #define MASK_TIM1_SR2_CC4OF      0x10
  3377.  
  3378. #define MASK_TIM1_EGR_UG         0x01
  3379. #define MASK_TIM1_EGR_CC1G       0x02
  3380. #define MASK_TIM1_EGR_CC2G       0x04
  3381. #define MASK_TIM1_EGR_CC3G       0x08
  3382. #define MASK_TIM1_EGR_CC4G       0x10
  3383. #define MASK_TIM1_EGR_COMG       0x20
  3384. #define MASK_TIM1_EGR_TG         0x40
  3385. #define MASK_TIM1_EGR_BG         0x80
  3386.  
  3387. #define MASK_TIM1_CCMR1_CC1S     0x03
  3388. #define MASK_TIM1_CCMR1_OC1FE    0x04
  3389. #define MASK_TIM1_CCMR1_OC1PE    0x08
  3390. #define MASK_TIM1_CCMR1_OC1M     0x70
  3391. #define MASK_TIM1_CCMR1_OC1CE    0x80
  3392.  
  3393. #define MASK_TIM1_CCMR2_CC2S     0x03
  3394. #define MASK_TIM1_CCMR2_OC2FE    0x04
  3395. #define MASK_TIM1_CCMR2_OC2PE    0x08
  3396. #define MASK_TIM1_CCMR2_OC2M     0x70
  3397. #define MASK_TIM1_CCMR2_OC2CE    0x80
  3398.  
  3399. #define MASK_TIM1_CCMR3_CC3S     0x03
  3400. #define MASK_TIM1_CCMR3_OC3FE    0x04
  3401. #define MASK_TIM1_CCMR3_OC3PE    0x08
  3402. #define MASK_TIM1_CCMR3_OC3M     0x70
  3403. #define MASK_TIM1_CCMR3_OC3CE    0x80
  3404.  
  3405. #define MASK_TIM1_CCMR4_CC4S     0x03
  3406. #define MASK_TIM1_CCMR4_OC4FE    0x04
  3407. #define MASK_TIM1_CCMR4_OC4PE    0x08
  3408. #define MASK_TIM1_CCMR4_OC4M     0x70
  3409. #define MASK_TIM1_CCMR4_OC4CE    0x80
  3410.  
  3411. #define MASK_TIM1_CCER1_CC1E     0x01
  3412. #define MASK_TIM1_CCER1_CC1P     0x02
  3413. #define MASK_TIM1_CCER1_CC1NE    0x04
  3414. #define MASK_TIM1_CCER1_CC1NP    0x08
  3415. #define MASK_TIM1_CCER1_CC2E     0x10
  3416. #define MASK_TIM1_CCER1_CC2P     0x20
  3417. #define MASK_TIM1_CCER1_CC2NE    0x40
  3418. #define MASK_TIM1_CCER1_CC2NP    0x80
  3419.  
  3420. #define MASK_TIM1_CCER2_CC3E     0x01
  3421. #define MASK_TIM1_CCER2_CC3P     0x02
  3422. #define MASK_TIM1_CCER2_CC3NE    0x04
  3423. #define MASK_TIM1_CCER2_CC3NP    0x08
  3424. #define MASK_TIM1_CCER2_CC4E     0x10
  3425. #define MASK_TIM1_CCER2_CC4P     0x20
  3426.  
  3427. #define MASK_TIM1_BKR_LOCK       0x03
  3428. #define MASK_TIM1_BKR_OSSI       0x04
  3429. #define MASK_TIM1_BKR_OSSR       0x08
  3430. #define MASK_TIM1_BKR_BKE        0x10
  3431. #define MASK_TIM1_BKR_BKP        0x20
  3432. #define MASK_TIM1_BKR_AOE        0x40
  3433. #define MASK_TIM1_BKR_MOE        0x80
  3434.  
  3435. #define MASK_TIM1_OISR_OIS1      0x01
  3436. #define MASK_TIM1_OISR_OIS1N     0x02
  3437. #define MASK_TIM1_OISR_OIS2      0x04
  3438. #define MASK_TIM1_OISR_OIS2N     0x08
  3439. #define MASK_TIM1_OISR_OIS3      0x10
  3440. #define MASK_TIM1_OISR_OIS3N     0x20
  3441. #define MASK_TIM1_OISR_OIS4      0x40
  3442.  
  3443.  
  3444. /*-------------------------------------------------------------------------
  3445.  *      TIM2 register definitions
  3446.  *-----------------------------------------------------------------------*/
  3447. /* TIM2 control register 1 */
  3448. #ifdef __IAR_SYSTEMS_ICC__
  3449. typedef struct
  3450. {
  3451.   unsigned char CEN         : 1;
  3452.   unsigned char UDIS        : 1;
  3453.   unsigned char URS         : 1;
  3454.   unsigned char OPM         : 1;
  3455.   unsigned char             : 3;
  3456.   unsigned char ARPE        : 1;
  3457. } __BITS_TIM2_CR1;
  3458. #endif
  3459. __IO_REG8_BIT(TIM2_CR1,    0x5300, __READ_WRITE, __BITS_TIM2_CR1);
  3460.  
  3461. /* TIM2 interrupt enable register */
  3462. #ifdef __IAR_SYSTEMS_ICC__
  3463. typedef struct
  3464. {
  3465.   unsigned char UIE         : 1;
  3466.   unsigned char CC1IE       : 1;
  3467.   unsigned char CC2IE       : 1;
  3468.   unsigned char CC3IE       : 1;
  3469.   unsigned char             : 2;
  3470.   unsigned char TIE         : 1;
  3471. } __BITS_TIM2_IER;
  3472. #endif
  3473. __IO_REG8_BIT(TIM2_IER,    0x5301, __READ_WRITE, __BITS_TIM2_IER);
  3474.  
  3475. /* TIM2 status register 1 */
  3476. #ifdef __IAR_SYSTEMS_ICC__
  3477. typedef struct
  3478. {
  3479.   unsigned char UIF         : 1;
  3480.   unsigned char CC1IF       : 1;
  3481.   unsigned char CC2IF       : 1;
  3482.   unsigned char CC3IF       : 1;
  3483.   unsigned char             : 2;
  3484.   unsigned char TIF         : 1;
  3485. } __BITS_TIM2_SR1;
  3486. #endif
  3487. __IO_REG8_BIT(TIM2_SR1,    0x5302, __READ_WRITE, __BITS_TIM2_SR1);
  3488.  
  3489. /* TIM2 status register 2 */
  3490. #ifdef __IAR_SYSTEMS_ICC__
  3491. typedef struct
  3492. {
  3493.   unsigned char             : 1;
  3494.   unsigned char CC1OF       : 1;
  3495.   unsigned char CC2OF       : 1;
  3496.   unsigned char CC3OF       : 1;
  3497. } __BITS_TIM2_SR2;
  3498. #endif
  3499. __IO_REG8_BIT(TIM2_SR2,    0x5303, __READ_WRITE, __BITS_TIM2_SR2);
  3500.  
  3501. /* TIM2 event generation register */
  3502. #ifdef __IAR_SYSTEMS_ICC__
  3503. typedef struct
  3504. {
  3505.   unsigned char UG          : 1;
  3506.   unsigned char CC1G        : 1;
  3507.   unsigned char CC2G        : 1;
  3508.   unsigned char CC3G        : 1;
  3509.   unsigned char             : 2;
  3510.   unsigned char TG          : 1;
  3511. } __BITS_TIM2_EGR;
  3512. #endif
  3513. __IO_REG8_BIT(TIM2_EGR,    0x5304, __WRITE, __BITS_TIM2_EGR);
  3514.  
  3515. /* TIM2 capture/compare mode register 1 */
  3516. #ifdef __IAR_SYSTEMS_ICC__
  3517. typedef struct
  3518. {
  3519.   unsigned char CC1S        : 2;
  3520.   unsigned char             : 1;
  3521.   unsigned char OC1PE       : 1;
  3522.   unsigned char OC1M        : 3;
  3523. } __BITS_TIM2_CCMR1;
  3524. #endif
  3525. __IO_REG8_BIT(TIM2_CCMR1,  0x5305, __READ_WRITE, __BITS_TIM2_CCMR1);
  3526.  
  3527. /* TIM2 capture/compare mode register 2 */
  3528. #ifdef __IAR_SYSTEMS_ICC__
  3529. typedef struct
  3530. {
  3531.   unsigned char CC2S        : 2;
  3532.   unsigned char             : 1;
  3533.   unsigned char OC2PE       : 1;
  3534.   unsigned char OC2M        : 3;
  3535. } __BITS_TIM2_CCMR2;
  3536. #endif
  3537. __IO_REG8_BIT(TIM2_CCMR2,  0x5306, __READ_WRITE, __BITS_TIM2_CCMR2);
  3538.  
  3539. /* TIM2 capture/compare mode register 3 */
  3540. #ifdef __IAR_SYSTEMS_ICC__
  3541. typedef struct
  3542. {
  3543.   unsigned char CC3S        : 2;
  3544.   unsigned char             : 1;
  3545.   unsigned char OC3PE       : 1;
  3546.   unsigned char OC3M        : 3;
  3547. } __BITS_TIM2_CCMR3;
  3548. #endif
  3549. __IO_REG8_BIT(TIM2_CCMR3,  0x5307, __READ_WRITE, __BITS_TIM2_CCMR3);
  3550.  
  3551. /* TIM2 capture/compare enable register 1 */
  3552. #ifdef __IAR_SYSTEMS_ICC__
  3553. typedef struct
  3554. {
  3555.   unsigned char CC1E        : 1;
  3556.   unsigned char CC1P        : 1;
  3557.   unsigned char             : 2;
  3558.   unsigned char CC2E        : 1;
  3559.   unsigned char CC2P        : 1;
  3560. } __BITS_TIM2_CCER1;
  3561. #endif
  3562. __IO_REG8_BIT(TIM2_CCER1,  0x5308, __READ_WRITE, __BITS_TIM2_CCER1);
  3563.  
  3564. /* TIM2 capture/compare enable register 2 */
  3565. #ifdef __IAR_SYSTEMS_ICC__
  3566. typedef struct
  3567. {
  3568.   unsigned char CC3E        : 1;
  3569.   unsigned char CC3P        : 1;
  3570. } __BITS_TIM2_CCER2;
  3571. #endif
  3572. __IO_REG8_BIT(TIM2_CCER2,  0x5309, __READ_WRITE, __BITS_TIM2_CCER2);
  3573.  
  3574. /* TIM2 counter high */
  3575. __IO_REG8    (TIM2_CNTRH,  0x530A, __READ_WRITE);
  3576. /* TIM2 counter low */
  3577. __IO_REG8    (TIM2_CNTRL,  0x530B, __READ_WRITE);
  3578. /* TIM2 prescaler register */
  3579. #ifdef __IAR_SYSTEMS_ICC__
  3580. typedef struct
  3581. {
  3582.   unsigned char PSC         : 4;
  3583. } __BITS_TIM2_PSCR;
  3584. #endif
  3585. __IO_REG8_BIT(TIM2_PSCR,   0x530C, __READ_WRITE, __BITS_TIM2_PSCR);
  3586.  
  3587. /* TIM2 auto-reload register high */
  3588. __IO_REG8    (TIM2_ARRH,   0x530D, __READ_WRITE);
  3589. /* TIM2 auto-reload register low */
  3590. __IO_REG8    (TIM2_ARRL,   0x530E, __READ_WRITE);
  3591. /* TIM2 capture/compare register 1 high */
  3592. __IO_REG8    (TIM2_CCR1H,  0x530F, __READ_WRITE);
  3593. /* TIM2 capture/compare register 1 low */
  3594. __IO_REG8    (TIM2_CCR1L,  0x5310, __READ_WRITE);
  3595. /* TIM2 capture/compare reg */
  3596. __IO_REG8    (TIM2_CCR2H,  0x5311, __READ_WRITE);
  3597. /* TIM2 capture/compare register 2 low */
  3598. __IO_REG8    (TIM2_CCR2L,  0x5312, __READ_WRITE);
  3599. /* TIM2 capture/compare register 3 high */
  3600. __IO_REG8    (TIM2_CCR3H,  0x5313, __READ_WRITE);
  3601. /* TIM2 capture/compare register 3 low */
  3602. __IO_REG8    (TIM2_CCR3L,  0x5314, __READ_WRITE);
  3603.  
  3604. /*-------------------------------------------------------------------------
  3605.  *      TIM2 bit fields
  3606.  *-----------------------------------------------------------------------*/
  3607. #ifdef __IAR_SYSTEMS_ICC__
  3608.  
  3609. #define TIM2_CR1_CEN             TIM2_CR1_bit.CEN
  3610. #define TIM2_CR1_UDIS            TIM2_CR1_bit.UDIS
  3611. #define TIM2_CR1_URS             TIM2_CR1_bit.URS
  3612. #define TIM2_CR1_OPM             TIM2_CR1_bit.OPM
  3613. #define TIM2_CR1_ARPE            TIM2_CR1_bit.ARPE
  3614.  
  3615. #define TIM2_IER_UIE             TIM2_IER_bit.UIE
  3616. #define TIM2_IER_CC1IE           TIM2_IER_bit.CC1IE
  3617. #define TIM2_IER_CC2IE           TIM2_IER_bit.CC2IE
  3618. #define TIM2_IER_CC3IE           TIM2_IER_bit.CC3IE
  3619. #define TIM2_IER_TIE             TIM2_IER_bit.TIE
  3620.  
  3621. #define TIM2_SR1_UIF             TIM2_SR1_bit.UIF
  3622. #define TIM2_SR1_CC1IF           TIM2_SR1_bit.CC1IF
  3623. #define TIM2_SR1_CC2IF           TIM2_SR1_bit.CC2IF
  3624. #define TIM2_SR1_CC3IF           TIM2_SR1_bit.CC3IF
  3625. #define TIM2_SR1_TIF             TIM2_SR1_bit.TIF
  3626.  
  3627. #define TIM2_SR2_CC1OF           TIM2_SR2_bit.CC1OF
  3628. #define TIM2_SR2_CC2OF           TIM2_SR2_bit.CC2OF
  3629. #define TIM2_SR2_CC3OF           TIM2_SR2_bit.CC3OF
  3630.  
  3631. #define TIM2_EGR_UG              TIM2_EGR_bit.UG
  3632. #define TIM2_EGR_CC1G            TIM2_EGR_bit.CC1G
  3633. #define TIM2_EGR_CC2G            TIM2_EGR_bit.CC2G
  3634. #define TIM2_EGR_CC3G            TIM2_EGR_bit.CC3G
  3635. #define TIM2_EGR_TG              TIM2_EGR_bit.TG
  3636.  
  3637. #define TIM2_CCMR1_CC1S          TIM2_CCMR1_bit.CC1S
  3638. #define TIM2_CCMR1_OC1PE         TIM2_CCMR1_bit.OC1PE
  3639. #define TIM2_CCMR1_OC1M          TIM2_CCMR1_bit.OC1M
  3640.  
  3641. #define TIM2_CCMR2_CC2S          TIM2_CCMR2_bit.CC2S
  3642. #define TIM2_CCMR2_OC2PE         TIM2_CCMR2_bit.OC2PE
  3643. #define TIM2_CCMR2_OC2M          TIM2_CCMR2_bit.OC2M
  3644.  
  3645. #define TIM2_CCMR3_CC3S          TIM2_CCMR3_bit.CC3S
  3646. #define TIM2_CCMR3_OC3PE         TIM2_CCMR3_bit.OC3PE
  3647. #define TIM2_CCMR3_OC3M          TIM2_CCMR3_bit.OC3M
  3648.  
  3649. #define TIM2_CCER1_CC1E          TIM2_CCER1_bit.CC1E
  3650. #define TIM2_CCER1_CC1P          TIM2_CCER1_bit.CC1P
  3651. #define TIM2_CCER1_CC2E          TIM2_CCER1_bit.CC2E
  3652. #define TIM2_CCER1_CC2P          TIM2_CCER1_bit.CC2P
  3653.  
  3654. #define TIM2_CCER2_CC3E          TIM2_CCER2_bit.CC3E
  3655. #define TIM2_CCER2_CC3P          TIM2_CCER2_bit.CC3P
  3656.  
  3657. #define TIM2_PSCR_PSC            TIM2_PSCR_bit.PSC
  3658.  
  3659. #endif
  3660.  
  3661. /*-------------------------------------------------------------------------
  3662.  *      TIM2 bit masks
  3663.  *-----------------------------------------------------------------------*/
  3664. #define MASK_TIM2_CR1_CEN        0x01
  3665. #define MASK_TIM2_CR1_UDIS       0x02
  3666. #define MASK_TIM2_CR1_URS        0x04
  3667. #define MASK_TIM2_CR1_OPM        0x08
  3668. #define MASK_TIM2_CR1_ARPE       0x80
  3669.  
  3670. #define MASK_TIM2_IER_UIE        0x01
  3671. #define MASK_TIM2_IER_CC1IE      0x02
  3672. #define MASK_TIM2_IER_CC2IE      0x04
  3673. #define MASK_TIM2_IER_CC3IE      0x08
  3674. #define MASK_TIM2_IER_TIE        0x40
  3675.  
  3676. #define MASK_TIM2_SR1_UIF        0x01
  3677. #define MASK_TIM2_SR1_CC1IF      0x02
  3678. #define MASK_TIM2_SR1_CC2IF      0x04
  3679. #define MASK_TIM2_SR1_CC3IF      0x08
  3680. #define MASK_TIM2_SR1_TIF        0x40
  3681.  
  3682. #define MASK_TIM2_SR2_CC1OF      0x02
  3683. #define MASK_TIM2_SR2_CC2OF      0x04
  3684. #define MASK_TIM2_SR2_CC3OF      0x08
  3685.  
  3686. #define MASK_TIM2_EGR_UG         0x01
  3687. #define MASK_TIM2_EGR_CC1G       0x02
  3688. #define MASK_TIM2_EGR_CC2G       0x04
  3689. #define MASK_TIM2_EGR_CC3G       0x08
  3690. #define MASK_TIM2_EGR_TG         0x40
  3691.  
  3692. #define MASK_TIM2_CCMR1_CC1S     0x03
  3693. #define MASK_TIM2_CCMR1_OC1PE    0x08
  3694. #define MASK_TIM2_CCMR1_OC1M     0x70
  3695.  
  3696. #define MASK_TIM2_CCMR2_CC2S     0x03
  3697. #define MASK_TIM2_CCMR2_OC2PE    0x08
  3698. #define MASK_TIM2_CCMR2_OC2M     0x70
  3699.  
  3700. #define MASK_TIM2_CCMR3_CC3S     0x03
  3701. #define MASK_TIM2_CCMR3_OC3PE    0x08
  3702. #define MASK_TIM2_CCMR3_OC3M     0x70
  3703.  
  3704. #define MASK_TIM2_CCER1_CC1E     0x01
  3705. #define MASK_TIM2_CCER1_CC1P     0x02
  3706. #define MASK_TIM2_CCER1_CC2E     0x10
  3707. #define MASK_TIM2_CCER1_CC2P     0x20
  3708.  
  3709. #define MASK_TIM2_CCER2_CC3E     0x01
  3710. #define MASK_TIM2_CCER2_CC3P     0x02
  3711.  
  3712. #define MASK_TIM2_PSCR_PSC       0x0F
  3713.  
  3714.  
  3715. /*-------------------------------------------------------------------------
  3716.  *      TIM3 register definitions
  3717.  *-----------------------------------------------------------------------*/
  3718. /* TIM3 control register 1 */
  3719. #ifdef __IAR_SYSTEMS_ICC__
  3720. typedef struct
  3721. {
  3722.   unsigned char CEN         : 1;
  3723.   unsigned char UDIS        : 1;
  3724.   unsigned char URS         : 1;
  3725.   unsigned char OPM         : 1;
  3726.   unsigned char             : 3;
  3727.   unsigned char ARPE        : 1;
  3728. } __BITS_TIM3_CR1;
  3729. #endif
  3730. __IO_REG8_BIT(TIM3_CR1,    0x5320, __READ_WRITE, __BITS_TIM3_CR1);
  3731.  
  3732. /* TIM3 interrupt enable register */
  3733. #ifdef __IAR_SYSTEMS_ICC__
  3734. typedef struct
  3735. {
  3736.   unsigned char UIE         : 1;
  3737.   unsigned char CC1IE       : 1;
  3738.   unsigned char CC2IE       : 1;
  3739.   unsigned char CC3IE       : 1;
  3740.   unsigned char             : 2;
  3741.   unsigned char TIE         : 1;
  3742. } __BITS_TIM3_IER;
  3743. #endif
  3744. __IO_REG8_BIT(TIM3_IER,    0x5321, __READ_WRITE, __BITS_TIM3_IER);
  3745.  
  3746. /* TIM3 status register 1 */
  3747. #ifdef __IAR_SYSTEMS_ICC__
  3748. typedef struct
  3749. {
  3750.   unsigned char UIF         : 1;
  3751.   unsigned char CC1IF       : 1;
  3752.   unsigned char CC2IF       : 1;
  3753.   unsigned char CC3IF       : 1;
  3754.   unsigned char             : 2;
  3755.   unsigned char TIF         : 1;
  3756. } __BITS_TIM3_SR1;
  3757. #endif
  3758. __IO_REG8_BIT(TIM3_SR1,    0x5322, __READ_WRITE, __BITS_TIM3_SR1);
  3759.  
  3760. /* TIM3 status register 2 */
  3761. #ifdef __IAR_SYSTEMS_ICC__
  3762. typedef struct
  3763. {
  3764.   unsigned char             : 1;
  3765.   unsigned char CC1OF       : 1;
  3766.   unsigned char CC2OF       : 1;
  3767.   unsigned char CC3OF       : 1;
  3768. } __BITS_TIM3_SR2;
  3769. #endif
  3770. __IO_REG8_BIT(TIM3_SR2,    0x5323, __READ_WRITE, __BITS_TIM3_SR2);
  3771.  
  3772. /* TIM3 event generation register */
  3773. #ifdef __IAR_SYSTEMS_ICC__
  3774. typedef struct
  3775. {
  3776.   unsigned char UG          : 1;
  3777.   unsigned char CC1G        : 1;
  3778.   unsigned char CC2G        : 1;
  3779.   unsigned char CC3G        : 1;
  3780.   unsigned char             : 2;
  3781.   unsigned char TG          : 1;
  3782. } __BITS_TIM3_EGR;
  3783. #endif
  3784. __IO_REG8_BIT(TIM3_EGR,    0x5324, __WRITE, __BITS_TIM3_EGR);
  3785.  
  3786. /* TIM3 capture/compare mode register 1 */
  3787. #ifdef __IAR_SYSTEMS_ICC__
  3788. typedef struct
  3789. {
  3790.   unsigned char CC1S        : 2;
  3791.   unsigned char             : 1;
  3792.   unsigned char OC1PE       : 1;
  3793.   unsigned char OC1M        : 3;
  3794. } __BITS_TIM3_CCMR1;
  3795. #endif
  3796. __IO_REG8_BIT(TIM3_CCMR1,  0x5325, __READ_WRITE, __BITS_TIM3_CCMR1);
  3797.  
  3798. /* TIM3 capture/compare mode register 2 */
  3799. #ifdef __IAR_SYSTEMS_ICC__
  3800. typedef struct
  3801. {
  3802.   unsigned char CC2S        : 2;
  3803.   unsigned char             : 1;
  3804.   unsigned char OC2PE       : 1;
  3805.   unsigned char OC2M        : 3;
  3806. } __BITS_TIM3_CCMR2;
  3807. #endif
  3808. __IO_REG8_BIT(TIM3_CCMR2,  0x5326, __READ_WRITE, __BITS_TIM3_CCMR2);
  3809.  
  3810. /* TIM3 capture/compare enable register 1 */
  3811. #ifdef __IAR_SYSTEMS_ICC__
  3812. typedef struct
  3813. {
  3814.   unsigned char CC1E        : 1;
  3815.   unsigned char CC1P        : 1;
  3816.   unsigned char             : 2;
  3817.   unsigned char CC2E        : 1;
  3818.   unsigned char CC2P        : 1;
  3819. } __BITS_TIM3_CCER1;
  3820. #endif
  3821. __IO_REG8_BIT(TIM3_CCER1,  0x5327, __READ_WRITE, __BITS_TIM3_CCER1);
  3822.  
  3823. /* TIM3 counter high */
  3824. __IO_REG8    (TIM3_CNTRH,  0x5328, __READ_WRITE);
  3825. /* TIM3 counter low */
  3826. __IO_REG8    (TIM3_CNTRL,  0x5329, __READ_WRITE);
  3827. /* TIM3 prescaler register */
  3828. #ifdef __IAR_SYSTEMS_ICC__
  3829. typedef struct
  3830. {
  3831.   unsigned char PSC         : 4;
  3832. } __BITS_TIM3_PSCR;
  3833. #endif
  3834. __IO_REG8_BIT(TIM3_PSCR,   0x532A, __READ_WRITE, __BITS_TIM3_PSCR);
  3835.  
  3836. /* TIM3 auto-reload register high */
  3837. __IO_REG8    (TIM3_ARRH,   0x532B, __READ_WRITE);
  3838. /* TIM3 auto-reload register low */
  3839. __IO_REG8    (TIM3_ARRL,   0x532C, __READ_WRITE);
  3840. /* TIM3 capture/compare register 1 high */
  3841. __IO_REG8    (TIM3_CCR1H,  0x532D, __READ_WRITE);
  3842. /* TIM3 capture/compare register 1 low */
  3843. __IO_REG8    (TIM3_CCR1L,  0x532E, __READ_WRITE);
  3844. /* TIM3 capture/compare register 2 high */
  3845. __IO_REG8    (TIM3_CCR2H,  0x532F, __READ_WRITE);
  3846. /* TIM3 capture/compare register 2 low */
  3847. __IO_REG8    (TIM3_CCR2L,  0x5330, __READ_WRITE);
  3848.  
  3849. /*-------------------------------------------------------------------------
  3850.  *      TIM3 bit fields
  3851.  *-----------------------------------------------------------------------*/
  3852. #ifdef __IAR_SYSTEMS_ICC__
  3853.  
  3854. #define TIM3_CR1_CEN             TIM3_CR1_bit.CEN
  3855. #define TIM3_CR1_UDIS            TIM3_CR1_bit.UDIS
  3856. #define TIM3_CR1_URS             TIM3_CR1_bit.URS
  3857. #define TIM3_CR1_OPM             TIM3_CR1_bit.OPM
  3858. #define TIM3_CR1_ARPE            TIM3_CR1_bit.ARPE
  3859.  
  3860. #define TIM3_IER_UIE             TIM3_IER_bit.UIE
  3861. #define TIM3_IER_CC1IE           TIM3_IER_bit.CC1IE
  3862. #define TIM3_IER_CC2IE           TIM3_IER_bit.CC2IE
  3863. #define TIM3_IER_CC3IE           TIM3_IER_bit.CC3IE
  3864. #define TIM3_IER_TIE             TIM3_IER_bit.TIE
  3865.  
  3866. #define TIM3_SR1_UIF             TIM3_SR1_bit.UIF
  3867. #define TIM3_SR1_CC1IF           TIM3_SR1_bit.CC1IF
  3868. #define TIM3_SR1_CC2IF           TIM3_SR1_bit.CC2IF
  3869. #define TIM3_SR1_CC3IF           TIM3_SR1_bit.CC3IF
  3870. #define TIM3_SR1_TIF             TIM3_SR1_bit.TIF
  3871.  
  3872. #define TIM3_SR2_CC1OF           TIM3_SR2_bit.CC1OF
  3873. #define TIM3_SR2_CC2OF           TIM3_SR2_bit.CC2OF
  3874. #define TIM3_SR2_CC3OF           TIM3_SR2_bit.CC3OF
  3875.  
  3876. #define TIM3_EGR_UG              TIM3_EGR_bit.UG
  3877. #define TIM3_EGR_CC1G            TIM3_EGR_bit.CC1G
  3878. #define TIM3_EGR_CC2G            TIM3_EGR_bit.CC2G
  3879. #define TIM3_EGR_CC3G            TIM3_EGR_bit.CC3G
  3880. #define TIM3_EGR_TG              TIM3_EGR_bit.TG
  3881.  
  3882. #define TIM3_CCMR1_CC1S          TIM3_CCMR1_bit.CC1S
  3883. #define TIM3_CCMR1_OC1PE         TIM3_CCMR1_bit.OC1PE
  3884. #define TIM3_CCMR1_OC1M          TIM3_CCMR1_bit.OC1M
  3885.  
  3886. #define TIM3_CCMR2_CC2S          TIM3_CCMR2_bit.CC2S
  3887. #define TIM3_CCMR2_OC2PE         TIM3_CCMR2_bit.OC2PE
  3888. #define TIM3_CCMR2_OC2M          TIM3_CCMR2_bit.OC2M
  3889.  
  3890. #define TIM3_CCER1_CC1E          TIM3_CCER1_bit.CC1E
  3891. #define TIM3_CCER1_CC1P          TIM3_CCER1_bit.CC1P
  3892. #define TIM3_CCER1_CC2E          TIM3_CCER1_bit.CC2E
  3893. #define TIM3_CCER1_CC2P          TIM3_CCER1_bit.CC2P
  3894.  
  3895. #define TIM3_PSCR_PSC            TIM3_PSCR_bit.PSC
  3896.  
  3897. #endif
  3898.  
  3899. /*-------------------------------------------------------------------------
  3900.  *      TIM3 bit masks
  3901.  *-----------------------------------------------------------------------*/
  3902. #define MASK_TIM3_CR1_CEN        0x01
  3903. #define MASK_TIM3_CR1_UDIS       0x02
  3904. #define MASK_TIM3_CR1_URS        0x04
  3905. #define MASK_TIM3_CR1_OPM        0x08
  3906. #define MASK_TIM3_CR1_ARPE       0x80
  3907.  
  3908. #define MASK_TIM3_IER_UIE        0x01
  3909. #define MASK_TIM3_IER_CC1IE      0x02
  3910. #define MASK_TIM3_IER_CC2IE      0x04
  3911. #define MASK_TIM3_IER_CC3IE      0x08
  3912. #define MASK_TIM3_IER_TIE        0x40
  3913.  
  3914. #define MASK_TIM3_SR1_UIF        0x01
  3915. #define MASK_TIM3_SR1_CC1IF      0x02
  3916. #define MASK_TIM3_SR1_CC2IF      0x04
  3917. #define MASK_TIM3_SR1_CC3IF      0x08
  3918. #define MASK_TIM3_SR1_TIF        0x40
  3919.  
  3920. #define MASK_TIM3_SR2_CC1OF      0x02
  3921. #define MASK_TIM3_SR2_CC2OF      0x04
  3922. #define MASK_TIM3_SR2_CC3OF      0x08
  3923.  
  3924. #define MASK_TIM3_EGR_UG         0x01
  3925. #define MASK_TIM3_EGR_CC1G       0x02
  3926. #define MASK_TIM3_EGR_CC2G       0x04
  3927. #define MASK_TIM3_EGR_CC3G       0x08
  3928. #define MASK_TIM3_EGR_TG         0x40
  3929.  
  3930. #define MASK_TIM3_CCMR1_CC1S     0x03
  3931. #define MASK_TIM3_CCMR1_OC1PE    0x08
  3932. #define MASK_TIM3_CCMR1_OC1M     0x70
  3933.  
  3934. #define MASK_TIM3_CCMR2_CC2S     0x03
  3935. #define MASK_TIM3_CCMR2_OC2PE    0x08
  3936. #define MASK_TIM3_CCMR2_OC2M     0x70
  3937.  
  3938. #define MASK_TIM3_CCER1_CC1E     0x01
  3939. #define MASK_TIM3_CCER1_CC1P     0x02
  3940. #define MASK_TIM3_CCER1_CC2E     0x10
  3941. #define MASK_TIM3_CCER1_CC2P     0x20
  3942.  
  3943. #define MASK_TIM3_PSCR_PSC       0x0F
  3944.  
  3945.  
  3946. /*-------------------------------------------------------------------------
  3947.  *      TIM4 register definitions
  3948.  *-----------------------------------------------------------------------*/
  3949. /* TIM4 control register 1 */
  3950. #ifdef __IAR_SYSTEMS_ICC__
  3951. typedef struct
  3952. {
  3953.   unsigned char CEN         : 1;
  3954.   unsigned char UDIS        : 1;
  3955.   unsigned char URS         : 1;
  3956.   unsigned char OPM         : 1;
  3957.   unsigned char             : 3;
  3958.   unsigned char ARPE        : 1;
  3959. } __BITS_TIM4_CR1;
  3960. #endif
  3961. __IO_REG8_BIT(TIM4_CR1,    0x5340, __READ_WRITE, __BITS_TIM4_CR1);
  3962.  
  3963. /* TIM4 interrupt enable register */
  3964. #ifdef __IAR_SYSTEMS_ICC__
  3965. typedef struct
  3966. {
  3967.   unsigned char UIE         : 1;
  3968.   unsigned char             : 5;
  3969.   unsigned char TIE         : 1;
  3970. } __BITS_TIM4_IER;
  3971. #endif
  3972. __IO_REG8_BIT(TIM4_IER,    0x5341, __READ_WRITE, __BITS_TIM4_IER);
  3973.  
  3974. /* TIM4 status register */
  3975. #ifdef __IAR_SYSTEMS_ICC__
  3976. typedef struct
  3977. {
  3978.   unsigned char UIF         : 1;
  3979.   unsigned char             : 5;
  3980.   unsigned char TIF         : 1;
  3981. } __BITS_TIM4_SR;
  3982. #endif
  3983. __IO_REG8_BIT(TIM4_SR,     0x5342, __READ_WRITE, __BITS_TIM4_SR);
  3984.  
  3985. /* TIM4 event generation register */
  3986. #ifdef __IAR_SYSTEMS_ICC__
  3987. typedef struct
  3988. {
  3989.   unsigned char UG          : 1;
  3990.   unsigned char             : 5;
  3991.   unsigned char TG          : 1;
  3992. } __BITS_TIM4_EGR;
  3993. #endif
  3994. __IO_REG8_BIT(TIM4_EGR,    0x5343, __WRITE, __BITS_TIM4_EGR);
  3995.  
  3996. /* TIM4 counter */
  3997. __IO_REG8    (TIM4_CNTR,   0x5344, __READ_WRITE);
  3998. /* TIM4 prescaler register */
  3999. #ifdef __IAR_SYSTEMS_ICC__
  4000. typedef struct
  4001. {
  4002.   unsigned char PSC         : 3;
  4003. } __BITS_TIM4_PSCR;
  4004. #endif
  4005. __IO_REG8_BIT(TIM4_PSCR,   0x5345, __READ_WRITE, __BITS_TIM4_PSCR);
  4006.  
  4007. /* TIM4 auto-reload register */
  4008. __IO_REG8    (TIM4_ARR,    0x5346, __READ_WRITE);
  4009.  
  4010. /*-------------------------------------------------------------------------
  4011.  *      TIM4 bit fields
  4012.  *-----------------------------------------------------------------------*/
  4013. #ifdef __IAR_SYSTEMS_ICC__
  4014.  
  4015. #define TIM4_CR1_CEN             TIM4_CR1_bit.CEN
  4016. #define TIM4_CR1_UDIS            TIM4_CR1_bit.UDIS
  4017. #define TIM4_CR1_URS             TIM4_CR1_bit.URS
  4018. #define TIM4_CR1_OPM             TIM4_CR1_bit.OPM
  4019. #define TIM4_CR1_ARPE            TIM4_CR1_bit.ARPE
  4020.  
  4021. #define TIM4_IER_UIE             TIM4_IER_bit.UIE
  4022. #define TIM4_IER_TIE             TIM4_IER_bit.TIE
  4023.  
  4024. #define TIM4_SR_UIF              TIM4_SR_bit.UIF
  4025. #define TIM4_SR_TIF              TIM4_SR_bit.TIF
  4026.  
  4027. #define TIM4_EGR_UG              TIM4_EGR_bit.UG
  4028. #define TIM4_EGR_TG              TIM4_EGR_bit.TG
  4029.  
  4030. #define TIM4_PSCR_PSC            TIM4_PSCR_bit.PSC
  4031.  
  4032. #endif
  4033.  
  4034. /*-------------------------------------------------------------------------
  4035.  *      TIM4 bit masks
  4036.  *-----------------------------------------------------------------------*/
  4037. #define MASK_TIM4_CR1_CEN        0x01
  4038. #define MASK_TIM4_CR1_UDIS       0x02
  4039. #define MASK_TIM4_CR1_URS        0x04
  4040. #define MASK_TIM4_CR1_OPM        0x08
  4041. #define MASK_TIM4_CR1_ARPE       0x80
  4042.  
  4043. #define MASK_TIM4_IER_UIE        0x01
  4044. #define MASK_TIM4_IER_TIE        0x40
  4045.  
  4046. #define MASK_TIM4_SR_UIF         0x01
  4047. #define MASK_TIM4_SR_TIF         0x40
  4048.  
  4049. #define MASK_TIM4_EGR_UG         0x01
  4050. #define MASK_TIM4_EGR_TG         0x40
  4051.  
  4052. #define MASK_TIM4_PSCR_PSC       0x07
  4053.  
  4054.  
  4055. /*-------------------------------------------------------------------------
  4056.  *      ADC1 register definitions
  4057.  *-----------------------------------------------------------------------*/
  4058. /* ADC data buffer registers */
  4059. __IO_REG8    (ADC_DB0RH,   0x53E0, __READ);
  4060. /* ADC data buffer registers */
  4061. __IO_REG8    (ADC_DB0RL,   0x53E1, __READ);
  4062. /* ADC data buffer registers */
  4063. __IO_REG8    (ADC_DB1RH,   0x53E2, __READ);
  4064. /* ADC data buffer registers */
  4065. __IO_REG8    (ADC_DB1RL,   0x53E3, __READ);
  4066. /* ADC data buffer registers */
  4067. __IO_REG8    (ADC_DB2RH,   0x53E4, __READ);
  4068. /* ADC data buffer registers */
  4069. __IO_REG8    (ADC_DB2RL,   0x53E5, __READ);
  4070. /* ADC data buffer registers */
  4071. __IO_REG8    (ADC_DB3RH,   0x53E6, __READ);
  4072. /* ADC data buffer registers */
  4073. __IO_REG8    (ADC_DB3RL,   0x53E7, __READ);
  4074. /* ADC data buffer registers */
  4075. __IO_REG8    (ADC_DB4RH,   0x53E8, __READ);
  4076. /* ADC data buffer registers */
  4077. __IO_REG8    (ADC_DB4RL,   0x53E9, __READ);
  4078. /* ADC data buffer registers */
  4079. __IO_REG8    (ADC_DB5RH,   0x53EA, __READ);
  4080. /* ADC data buffer registers */
  4081. __IO_REG8    (ADC_DB5RL,   0x53EB, __READ);
  4082. /* ADC data buffer registers */
  4083. __IO_REG8    (ADC_DB6RH,   0x53EC, __READ);
  4084. /* ADC data buffer registers */
  4085. __IO_REG8    (ADC_DB6RL,   0x53ED, __READ);
  4086. /* ADC data buffer registers */
  4087. __IO_REG8    (ADC_DB7RH,   0x53EE, __READ);
  4088. /* ADC data buffer registers */
  4089. __IO_REG8    (ADC_DB7RL,   0x53EF, __READ);
  4090. /* ADC data buffer registers */
  4091. __IO_REG8    (ADC_DB8RH,   0x53F0, __READ);
  4092. /* ADC data buffer registers */
  4093. __IO_REG8    (ADC_DB8RL,   0x53F1, __READ);
  4094. /* ADC data buffer registers */
  4095. __IO_REG8    (ADC_DB9RH,   0x53F2, __READ);
  4096. /* ADC data buffer registers */
  4097. __IO_REG8    (ADC_DB9RL,   0x53F3, __READ);
  4098. /* ADC control/status register */
  4099. #ifdef __IAR_SYSTEMS_ICC__
  4100. typedef struct
  4101. {
  4102.   unsigned char CH          : 4;
  4103.   unsigned char AWDIE       : 1;
  4104.   unsigned char EOCIE       : 1;
  4105.   unsigned char AWD         : 1;
  4106.   unsigned char EOC         : 1;
  4107. } __BITS_ADC_CSR;
  4108. #endif
  4109. __IO_REG8_BIT(ADC_CSR,     0x5400, __READ_WRITE, __BITS_ADC_CSR);
  4110.  
  4111. /* ADC configuration register 1 */
  4112. #ifdef __IAR_SYSTEMS_ICC__
  4113. typedef struct
  4114. {
  4115.   unsigned char ADON        : 1;
  4116.   unsigned char CONT        : 1;
  4117.   unsigned char             : 2;
  4118.   unsigned char SPSEL       : 3;
  4119. } __BITS_ADC_CR1;
  4120. #endif
  4121. __IO_REG8_BIT(ADC_CR1,     0x5401, __READ_WRITE, __BITS_ADC_CR1);
  4122.  
  4123. /* ADC configuration register 2 */
  4124. #ifdef __IAR_SYSTEMS_ICC__
  4125. typedef struct
  4126. {
  4127.   unsigned char             : 1;
  4128.   unsigned char SCAN        : 1;
  4129.   unsigned char             : 1;
  4130.   unsigned char ALIGN       : 1;
  4131.   unsigned char EXTSEL      : 2;
  4132.   unsigned char EXTTRIG     : 1;
  4133. } __BITS_ADC_CR2;
  4134. #endif
  4135. __IO_REG8_BIT(ADC_CR2,     0x5402, __READ_WRITE, __BITS_ADC_CR2);
  4136.  
  4137. /* ADC configuration register 3 */
  4138. #ifdef __IAR_SYSTEMS_ICC__
  4139. typedef struct
  4140. {
  4141.   unsigned char             : 6;
  4142.   unsigned char OVR         : 1;
  4143.   unsigned char DBUF        : 1;
  4144. } __BITS_ADC_CR3;
  4145. #endif
  4146. __IO_REG8_BIT(ADC_CR3,     0x5403, __READ_WRITE, __BITS_ADC_CR3);
  4147.  
  4148. /* ADC data register high */
  4149. __IO_REG8    (ADC_DRH,     0x5404, __READ);
  4150. /* ADC data register low */
  4151. __IO_REG8    (ADC_DRL,     0x5405, __READ);
  4152. /* ADC Schmitt trigger disable register high */
  4153. __IO_REG8    (ADC_TDRH,    0x5406, __READ_WRITE);
  4154. /* ADC Schmitt trigger disable register low */
  4155. __IO_REG8    (ADC_TDRL,    0x5407, __READ_WRITE);
  4156. /* ADC high threshold register high */
  4157. __IO_REG8    (ADC_HTRH,    0x5408, __READ_WRITE);
  4158. /* ADC high threshold register low */
  4159. #ifdef __IAR_SYSTEMS_ICC__
  4160. typedef struct
  4161. {
  4162.   unsigned char HT          : 2;
  4163. } __BITS_ADC_HTRL;
  4164. #endif
  4165. __IO_REG8_BIT(ADC_HTRL,    0x5409, __READ_WRITE, __BITS_ADC_HTRL);
  4166.  
  4167. /* ADC low threshold register high */
  4168. __IO_REG8    (ADC_LTRH,    0x540A, __READ_WRITE);
  4169. /* ADC low threshold register low */
  4170. #ifdef __IAR_SYSTEMS_ICC__
  4171. typedef struct
  4172. {
  4173.   unsigned char LT          : 2;
  4174. } __BITS_ADC_LTRL;
  4175. #endif
  4176. __IO_REG8_BIT(ADC_LTRL,    0x540B, __READ_WRITE, __BITS_ADC_LTRL);
  4177.  
  4178. /* ADC analog watchdog status register high */
  4179. #ifdef __IAR_SYSTEMS_ICC__
  4180. typedef struct
  4181. {
  4182.   unsigned char AWS8        : 1;
  4183.   unsigned char AWS9        : 1;
  4184. } __BITS_ADC_AWSRH;
  4185. #endif
  4186. __IO_REG8_BIT(ADC_AWSRH,   0x540C, __READ_WRITE, __BITS_ADC_AWSRH);
  4187.  
  4188. /* ADC analog watchdog status register low */
  4189. #ifdef __IAR_SYSTEMS_ICC__
  4190. typedef struct
  4191. {
  4192.   unsigned char AWS0        : 1;
  4193.   unsigned char AWS1        : 1;
  4194.   unsigned char AWS2        : 1;
  4195.   unsigned char AWS3        : 1;
  4196.   unsigned char AWS4        : 1;
  4197.   unsigned char AWS5        : 1;
  4198.   unsigned char AWS6        : 1;
  4199.   unsigned char AWS7        : 1;
  4200. } __BITS_ADC_AWSRL;
  4201. #endif
  4202. __IO_REG8_BIT(ADC_AWSRL,   0x540D, __READ_WRITE, __BITS_ADC_AWSRL);
  4203.  
  4204. /* ADC analog watchdog control register high */
  4205. #ifdef __IAR_SYSTEMS_ICC__
  4206. typedef struct
  4207. {
  4208.   unsigned char AWEN8       : 1;
  4209.   unsigned char AWEN9       : 1;
  4210. } __BITS_ADC_AWCRH;
  4211. #endif
  4212. __IO_REG8_BIT(ADC_AWCRH,   0x540E, __READ_WRITE, __BITS_ADC_AWCRH);
  4213.  
  4214. /* ADC analog watchdog control register low */
  4215. #ifdef __IAR_SYSTEMS_ICC__
  4216. typedef struct
  4217. {
  4218.   unsigned char AWEN0       : 1;
  4219.   unsigned char AWEN1       : 1;
  4220.   unsigned char AWEN2       : 1;
  4221.   unsigned char AWEN3       : 1;
  4222.   unsigned char AWEN4       : 1;
  4223.   unsigned char AWEN5       : 1;
  4224.   unsigned char AWEN6       : 1;
  4225.   unsigned char AWEN7       : 1;
  4226. } __BITS_ADC_AWCRL;
  4227. #endif
  4228. __IO_REG8_BIT(ADC_AWCRL,   0x540F, __READ_WRITE, __BITS_ADC_AWCRL);
  4229.  
  4230.  
  4231. /*-------------------------------------------------------------------------
  4232.  *      ADC1 bit fields
  4233.  *-----------------------------------------------------------------------*/
  4234. #ifdef __IAR_SYSTEMS_ICC__
  4235.  
  4236. #define ADC_CSR_CH               ADC_CSR_bit.CH
  4237. #define ADC_CSR_AWDIE            ADC_CSR_bit.AWDIE
  4238. #define ADC_CSR_EOCIE            ADC_CSR_bit.EOCIE
  4239. #define ADC_CSR_AWD              ADC_CSR_bit.AWD
  4240. #define ADC_CSR_EOC              ADC_CSR_bit.EOC
  4241.  
  4242. #define ADC_CR1_ADON             ADC_CR1_bit.ADON
  4243. #define ADC_CR1_CONT             ADC_CR1_bit.CONT
  4244. #define ADC_CR1_SPSEL            ADC_CR1_bit.SPSEL
  4245.  
  4246. #define ADC_CR2_SCAN             ADC_CR2_bit.SCAN
  4247. #define ADC_CR2_ALIGN            ADC_CR2_bit.ALIGN
  4248. #define ADC_CR2_EXTSEL           ADC_CR2_bit.EXTSEL
  4249. #define ADC_CR2_EXTTRIG          ADC_CR2_bit.EXTTRIG
  4250.  
  4251. #define ADC_CR3_OVR              ADC_CR3_bit.OVR
  4252. #define ADC_CR3_DBUF             ADC_CR3_bit.DBUF
  4253.  
  4254. #define ADC_HTRL_HT              ADC_HTRL_bit.HT
  4255.  
  4256. #define ADC_LTRL_LT              ADC_LTRL_bit.LT
  4257.  
  4258. #define ADC_AWSRH_AWS8           ADC_AWSRH_bit.AWS8
  4259. #define ADC_AWSRH_AWS9           ADC_AWSRH_bit.AWS9
  4260.  
  4261. #define ADC_AWSRL_AWS0           ADC_AWSRL_bit.AWS0
  4262. #define ADC_AWSRL_AWS1           ADC_AWSRL_bit.AWS1
  4263. #define ADC_AWSRL_AWS2           ADC_AWSRL_bit.AWS2
  4264. #define ADC_AWSRL_AWS3           ADC_AWSRL_bit.AWS3
  4265. #define ADC_AWSRL_AWS4           ADC_AWSRL_bit.AWS4
  4266. #define ADC_AWSRL_AWS5           ADC_AWSRL_bit.AWS5
  4267. #define ADC_AWSRL_AWS6           ADC_AWSRL_bit.AWS6
  4268. #define ADC_AWSRL_AWS7           ADC_AWSRL_bit.AWS7
  4269.  
  4270. #define ADC_AWCRH_AWEN8          ADC_AWCRH_bit.AWEN8
  4271. #define ADC_AWCRH_AWEN9          ADC_AWCRH_bit.AWEN9
  4272.  
  4273. #define ADC_AWCRL_AWEN0          ADC_AWCRL_bit.AWEN0
  4274. #define ADC_AWCRL_AWEN1          ADC_AWCRL_bit.AWEN1
  4275. #define ADC_AWCRL_AWEN2          ADC_AWCRL_bit.AWEN2
  4276. #define ADC_AWCRL_AWEN3          ADC_AWCRL_bit.AWEN3
  4277. #define ADC_AWCRL_AWEN4          ADC_AWCRL_bit.AWEN4
  4278. #define ADC_AWCRL_AWEN5          ADC_AWCRL_bit.AWEN5
  4279. #define ADC_AWCRL_AWEN6          ADC_AWCRL_bit.AWEN6
  4280. #define ADC_AWCRL_AWEN7          ADC_AWCRL_bit.AWEN7
  4281.  
  4282. #endif
  4283.  
  4284. /*-------------------------------------------------------------------------
  4285.  *      ADC1 bit masks
  4286.  *-----------------------------------------------------------------------*/
  4287. #define MASK_ADC_CSR_CH          0x0F
  4288. #define MASK_ADC_CSR_AWDIE       0x10
  4289. #define MASK_ADC_CSR_EOCIE       0x20
  4290. #define MASK_ADC_CSR_AWD         0x40
  4291. #define MASK_ADC_CSR_EOC         0x80
  4292.  
  4293. #define MASK_ADC_CR1_ADON        0x01
  4294. #define MASK_ADC_CR1_CONT        0x02
  4295. #define MASK_ADC_CR1_SPSEL       0x70
  4296.  
  4297. #define MASK_ADC_CR2_SCAN        0x02
  4298. #define MASK_ADC_CR2_ALIGN       0x08
  4299. #define MASK_ADC_CR2_EXTSEL      0x30
  4300. #define MASK_ADC_CR2_EXTTRIG     0x40
  4301.  
  4302. #define MASK_ADC_CR3_OVR         0x40
  4303. #define MASK_ADC_CR3_DBUF        0x80
  4304.  
  4305. #define MASK_ADC_HTRL_HT         0x03
  4306.  
  4307. #define MASK_ADC_LTRL_LT         0x03
  4308.  
  4309. #define MASK_ADC_AWSRH_AWS8      0x01
  4310. #define MASK_ADC_AWSRH_AWS9      0x02
  4311.  
  4312. #define MASK_ADC_AWSRL_AWS0      0x01
  4313. #define MASK_ADC_AWSRL_AWS1      0x02
  4314. #define MASK_ADC_AWSRL_AWS2      0x04
  4315. #define MASK_ADC_AWSRL_AWS3      0x08
  4316. #define MASK_ADC_AWSRL_AWS4      0x10
  4317. #define MASK_ADC_AWSRL_AWS5      0x20
  4318. #define MASK_ADC_AWSRL_AWS6      0x40
  4319. #define MASK_ADC_AWSRL_AWS7      0x80
  4320.  
  4321. #define MASK_ADC_AWCRH_AWEN8     0x01
  4322. #define MASK_ADC_AWCRH_AWEN9     0x02
  4323.  
  4324. #define MASK_ADC_AWCRL_AWEN0     0x01
  4325. #define MASK_ADC_AWCRL_AWEN1     0x02
  4326. #define MASK_ADC_AWCRL_AWEN2     0x04
  4327. #define MASK_ADC_AWCRL_AWEN3     0x08
  4328. #define MASK_ADC_AWCRL_AWEN4     0x10
  4329. #define MASK_ADC_AWCRL_AWEN5     0x20
  4330. #define MASK_ADC_AWCRL_AWEN6     0x40
  4331. #define MASK_ADC_AWCRL_AWEN7     0x80
  4332.  
  4333.  
  4334. /*-------------------------------------------------------------------------
  4335.  *      CPU register definitions
  4336.  *-----------------------------------------------------------------------*/
  4337. /* Accumulator */
  4338. __IO_REG8    (CPU_A,       0x7F00, __READ_WRITE);
  4339. /* Program counter extended */
  4340. __IO_REG8    (CPU_PCE,     0x7F01, __READ_WRITE);
  4341. /* Program counter high */
  4342. __IO_REG8    (CPU_PCH,     0x7F02, __READ_WRITE);
  4343. /* Program counter low */
  4344. __IO_REG8    (CPU_PCL,     0x7F03, __READ_WRITE);
  4345. /* X index register high */
  4346. __IO_REG8    (CPU_XH,      0x7F04, __READ_WRITE);
  4347. /* X index register low */
  4348. __IO_REG8    (CPU_XL,      0x7F05, __READ_WRITE);
  4349. /* Y index register high */
  4350. __IO_REG8    (CPU_YH,      0x7F06, __READ_WRITE);
  4351. /* Y index register low */
  4352. __IO_REG8    (CPU_YL,      0x7F07, __READ_WRITE);
  4353. /* Stack pointer high */
  4354. __IO_REG8    (CPU_SPH,     0x7F08, __READ_WRITE);
  4355. /* Stack pointer low */
  4356. __IO_REG8    (CPU_SPL,     0x7F09, __READ_WRITE);
  4357. /* Condition code register */
  4358. #ifdef __IAR_SYSTEMS_ICC__
  4359. typedef struct
  4360. {
  4361.   unsigned char C           : 1;
  4362.   unsigned char Z           : 1;
  4363.   unsigned char NF          : 1;
  4364.   unsigned char I0          : 1;
  4365.   unsigned char H           : 1;
  4366.   unsigned char I1          : 1;
  4367.   unsigned char             : 1;
  4368.   unsigned char V           : 1;
  4369. } __BITS_CPU_CCR;
  4370. #endif
  4371. __IO_REG8_BIT(CPU_CCR,     0x7F0A, __READ_WRITE, __BITS_CPU_CCR);
  4372.  
  4373. /* Global configuration register */
  4374. #ifdef __IAR_SYSTEMS_ICC__
  4375. typedef struct
  4376. {
  4377.   unsigned char SWO         : 1;
  4378.   unsigned char AL          : 1;
  4379. } __BITS_CPU_CFG_GCR;
  4380. #endif
  4381. __IO_REG8_BIT(CPU_CFG_GCR, 0x7F60, __READ_WRITE, __BITS_CPU_CFG_GCR);
  4382.  
  4383.  
  4384. /*-------------------------------------------------------------------------
  4385.  *      CPU bit fields
  4386.  *-----------------------------------------------------------------------*/
  4387. #ifdef __IAR_SYSTEMS_ICC__
  4388.  
  4389. #define CPU_CCR_C                CPU_CCR_bit.C
  4390. #define CPU_CCR_Z                CPU_CCR_bit.Z
  4391. #define CPU_CCR_NF               CPU_CCR_bit.NF
  4392. #define CPU_CCR_I0               CPU_CCR_bit.I0
  4393. #define CPU_CCR_H                CPU_CCR_bit.H
  4394. #define CPU_CCR_I1               CPU_CCR_bit.I1
  4395. #define CPU_CCR_V                CPU_CCR_bit.V
  4396.  
  4397. #define CPU_CFG_GCR_SWO          CPU_CFG_GCR_bit.SWO
  4398. #define CPU_CFG_GCR_AL           CPU_CFG_GCR_bit.AL
  4399.  
  4400. #endif
  4401.  
  4402. /*-------------------------------------------------------------------------
  4403.  *      CPU bit masks
  4404.  *-----------------------------------------------------------------------*/
  4405. #define MASK_CPU_CCR_C           0x01
  4406. #define MASK_CPU_CCR_Z           0x02
  4407. #define MASK_CPU_CCR_NF          0x04
  4408. #define MASK_CPU_CCR_I0          0x08
  4409. #define MASK_CPU_CCR_H           0x10
  4410. #define MASK_CPU_CCR_I1          0x20
  4411. #define MASK_CPU_CCR_V           0x80
  4412.  
  4413. #define MASK_CPU_CFG_GCR_SWO     0x01
  4414. #define MASK_CPU_CFG_GCR_AL      0x02
  4415.  
  4416.  
  4417. /*-------------------------------------------------------------------------
  4418.  *      ITC - SPR register definitions
  4419.  *-----------------------------------------------------------------------*/
  4420. /* Interrupt software priority register 1 */
  4421. #ifdef __IAR_SYSTEMS_ICC__
  4422. typedef struct
  4423. {
  4424.   unsigned char VECT0SPR    : 2;
  4425.   unsigned char VECT1SPR    : 2;
  4426.   unsigned char VECT2SPR    : 2;
  4427.   unsigned char VECT3SPR    : 2;
  4428. } __BITS_ITC_SPR1;
  4429. #endif
  4430. __IO_REG8_BIT(ITC_SPR1,    0x7F70, __READ_WRITE, __BITS_ITC_SPR1);
  4431.  
  4432. /* Interrupt software priority register 2 */
  4433. #ifdef __IAR_SYSTEMS_ICC__
  4434. typedef struct
  4435. {
  4436.   unsigned char VECT4SPR    : 2;
  4437.   unsigned char VECT5SPR    : 2;
  4438.   unsigned char VECT6SPR    : 2;
  4439.   unsigned char VECT7SPR    : 2;
  4440. } __BITS_ITC_SPR2;
  4441. #endif
  4442. __IO_REG8_BIT(ITC_SPR2,    0x7F71, __READ_WRITE, __BITS_ITC_SPR2);
  4443.  
  4444. /* Interrupt software priority register 3 */
  4445. #ifdef __IAR_SYSTEMS_ICC__
  4446. typedef struct
  4447. {
  4448.   unsigned char VECT8SPR    : 2;
  4449.   unsigned char VECT9SPR    : 2;
  4450.   unsigned char VECT10SPR   : 2;
  4451.   unsigned char VECT11SPR   : 2;
  4452. } __BITS_ITC_SPR3;
  4453. #endif
  4454. __IO_REG8_BIT(ITC_SPR3,    0x7F72, __READ_WRITE, __BITS_ITC_SPR3);
  4455.  
  4456. /* Interrupt software priority register 4 */
  4457. #ifdef __IAR_SYSTEMS_ICC__
  4458. typedef struct
  4459. {
  4460.   unsigned char VECT12SPR   : 2;
  4461.   unsigned char VECT13SPR   : 2;
  4462.   unsigned char VECT14SPR   : 2;
  4463.   unsigned char VECT15SPR   : 2;
  4464. } __BITS_ITC_SPR4;
  4465. #endif
  4466. __IO_REG8_BIT(ITC_SPR4,    0x7F73, __READ_WRITE, __BITS_ITC_SPR4);
  4467.  
  4468. /* Interrupt software priority register 5 */
  4469. #ifdef __IAR_SYSTEMS_ICC__
  4470. typedef struct
  4471. {
  4472.   unsigned char VECT16SPR   : 2;
  4473.   unsigned char VECT17SPR   : 2;
  4474.   unsigned char VECT18SPR   : 2;
  4475.   unsigned char VECT19SPR   : 2;
  4476. } __BITS_ITC_SPR5;
  4477. #endif
  4478. __IO_REG8_BIT(ITC_SPR5,    0x7F74, __READ_WRITE, __BITS_ITC_SPR5);
  4479.  
  4480. /* Interrupt software priority register 6 */
  4481. #ifdef __IAR_SYSTEMS_ICC__
  4482. typedef struct
  4483. {
  4484.   unsigned char VECT20SPR   : 2;
  4485.   unsigned char VECT21SPR   : 2;
  4486.   unsigned char VECT22SPR   : 2;
  4487.   unsigned char VECT23SPR   : 2;
  4488. } __BITS_ITC_SPR6;
  4489. #endif
  4490. __IO_REG8_BIT(ITC_SPR6,    0x7F75, __READ_WRITE, __BITS_ITC_SPR6);
  4491.  
  4492. /* Interrupt software priority register 7 */
  4493. #ifdef __IAR_SYSTEMS_ICC__
  4494. typedef struct
  4495. {
  4496.   unsigned char VECT24SPR   : 2;
  4497.   unsigned char VECT25SPR   : 2;
  4498.   unsigned char VECT26SPR   : 2;
  4499.   unsigned char VECT27SPR   : 2;
  4500. } __BITS_ITC_SPR7;
  4501. #endif
  4502. __IO_REG8_BIT(ITC_SPR7,    0x7F76, __READ_WRITE, __BITS_ITC_SPR7);
  4503.  
  4504. /* Interrupt software priority register 8 */
  4505. #ifdef __IAR_SYSTEMS_ICC__
  4506. typedef struct
  4507. {
  4508.   unsigned char VECT28SPR   : 2;
  4509.   unsigned char VECT29SPR   : 2;
  4510. } __BITS_ITC_SPR8;
  4511. #endif
  4512. __IO_REG8_BIT(ITC_SPR8,    0x7F77, __READ_WRITE, __BITS_ITC_SPR8);
  4513.  
  4514.  
  4515. /*-------------------------------------------------------------------------
  4516.  *      ITC - SPR bit fields
  4517.  *-----------------------------------------------------------------------*/
  4518. #ifdef __IAR_SYSTEMS_ICC__
  4519.  
  4520. #define ITC_SPR1_VECT0SPR        ITC_SPR1_bit.VECT0SPR
  4521. #define ITC_SPR1_VECT1SPR        ITC_SPR1_bit.VECT1SPR
  4522. #define ITC_SPR1_VECT2SPR        ITC_SPR1_bit.VECT2SPR
  4523. #define ITC_SPR1_VECT3SPR        ITC_SPR1_bit.VECT3SPR
  4524.  
  4525. #define ITC_SPR2_VECT4SPR        ITC_SPR2_bit.VECT4SPR
  4526. #define ITC_SPR2_VECT5SPR        ITC_SPR2_bit.VECT5SPR
  4527. #define ITC_SPR2_VECT6SPR        ITC_SPR2_bit.VECT6SPR
  4528. #define ITC_SPR2_VECT7SPR        ITC_SPR2_bit.VECT7SPR
  4529.  
  4530. #define ITC_SPR3_VECT8SPR        ITC_SPR3_bit.VECT8SPR
  4531. #define ITC_SPR3_VECT9SPR        ITC_SPR3_bit.VECT9SPR
  4532. #define ITC_SPR3_VECT10SPR       ITC_SPR3_bit.VECT10SPR
  4533. #define ITC_SPR3_VECT11SPR       ITC_SPR3_bit.VECT11SPR
  4534.  
  4535. #define ITC_SPR4_VECT12SPR       ITC_SPR4_bit.VECT12SPR
  4536. #define ITC_SPR4_VECT13SPR       ITC_SPR4_bit.VECT13SPR
  4537. #define ITC_SPR4_VECT14SPR       ITC_SPR4_bit.VECT14SPR
  4538. #define ITC_SPR4_VECT15SPR       ITC_SPR4_bit.VECT15SPR
  4539.  
  4540. #define ITC_SPR5_VECT16SPR       ITC_SPR5_bit.VECT16SPR
  4541. #define ITC_SPR5_VECT17SPR       ITC_SPR5_bit.VECT17SPR
  4542. #define ITC_SPR5_VECT18SPR       ITC_SPR5_bit.VECT18SPR
  4543. #define ITC_SPR5_VECT19SPR       ITC_SPR5_bit.VECT19SPR
  4544.  
  4545. #define ITC_SPR6_VECT20SPR       ITC_SPR6_bit.VECT20SPR
  4546. #define ITC_SPR6_VECT21SPR       ITC_SPR6_bit.VECT21SPR
  4547. #define ITC_SPR6_VECT22SPR       ITC_SPR6_bit.VECT22SPR
  4548. #define ITC_SPR6_VECT23SPR       ITC_SPR6_bit.VECT23SPR
  4549.  
  4550. #define ITC_SPR7_VECT24SPR       ITC_SPR7_bit.VECT24SPR
  4551. #define ITC_SPR7_VECT25SPR       ITC_SPR7_bit.VECT25SPR
  4552. #define ITC_SPR7_VECT26SPR       ITC_SPR7_bit.VECT26SPR
  4553. #define ITC_SPR7_VECT27SPR       ITC_SPR7_bit.VECT27SPR
  4554.  
  4555. #define ITC_SPR8_VECT28SPR       ITC_SPR8_bit.VECT28SPR
  4556. #define ITC_SPR8_VECT29SPR       ITC_SPR8_bit.VECT29SPR
  4557.  
  4558. #endif
  4559.  
  4560. /*-------------------------------------------------------------------------
  4561.  *      ITC - SPR bit masks
  4562.  *-----------------------------------------------------------------------*/
  4563. #define MASK_ITC_SPR1_VECT0SPR   0x03
  4564. #define MASK_ITC_SPR1_VECT1SPR   0x0C
  4565. #define MASK_ITC_SPR1_VECT2SPR   0x30
  4566. #define MASK_ITC_SPR1_VECT3SPR   0xC0
  4567.  
  4568. #define MASK_ITC_SPR2_VECT4SPR   0x03
  4569. #define MASK_ITC_SPR2_VECT5SPR   0x0C
  4570. #define MASK_ITC_SPR2_VECT6SPR   0x30
  4571. #define MASK_ITC_SPR2_VECT7SPR   0xC0
  4572.  
  4573. #define MASK_ITC_SPR3_VECT8SPR   0x03
  4574. #define MASK_ITC_SPR3_VECT9SPR   0x0C
  4575. #define MASK_ITC_SPR3_VECT10SPR  0x30
  4576. #define MASK_ITC_SPR3_VECT11SPR  0xC0
  4577.  
  4578. #define MASK_ITC_SPR4_VECT12SPR  0x03
  4579. #define MASK_ITC_SPR4_VECT13SPR  0x0C
  4580. #define MASK_ITC_SPR4_VECT14SPR  0x30
  4581. #define MASK_ITC_SPR4_VECT15SPR  0xC0
  4582.  
  4583. #define MASK_ITC_SPR5_VECT16SPR  0x03
  4584. #define MASK_ITC_SPR5_VECT17SPR  0x0C
  4585. #define MASK_ITC_SPR5_VECT18SPR  0x30
  4586. #define MASK_ITC_SPR5_VECT19SPR  0xC0
  4587.  
  4588. #define MASK_ITC_SPR6_VECT20SPR  0x03
  4589. #define MASK_ITC_SPR6_VECT21SPR  0x0C
  4590. #define MASK_ITC_SPR6_VECT22SPR  0x30
  4591. #define MASK_ITC_SPR6_VECT23SPR  0xC0
  4592.  
  4593. #define MASK_ITC_SPR7_VECT24SPR  0x03
  4594. #define MASK_ITC_SPR7_VECT25SPR  0x0C
  4595. #define MASK_ITC_SPR7_VECT26SPR  0x30
  4596. #define MASK_ITC_SPR7_VECT27SPR  0xC0
  4597.  
  4598. #define MASK_ITC_SPR8_VECT28SPR  0x03
  4599. #define MASK_ITC_SPR8_VECT29SPR  0x0C
  4600.  
  4601.  
  4602. /*-------------------------------------------------------------------------
  4603.  *      SWIM register definitions
  4604.  *-----------------------------------------------------------------------*/
  4605. /* SWIM control status register */
  4606. __IO_REG8    (SWIM_CSR,    0x7F80, __READ_WRITE);
  4607.  
  4608.  
  4609. /*-------------------------------------------------------------------------
  4610.  *      DM register definitions
  4611.  *-----------------------------------------------------------------------*/
  4612. /* DM breakpoint 1 register extended byte */
  4613. __IO_REG8    (DM_BK1RE,    0x7F90, __READ_WRITE);
  4614. /* DM breakpoint 1 register high byte */
  4615. __IO_REG8    (DM_BK1RH,    0x7F91, __READ_WRITE);
  4616. /* DM breakpoint 1 register low byte */
  4617. __IO_REG8    (DM_BK1RL,    0x7F92, __READ_WRITE);
  4618. /* DM breakpoint 2 register extended byte */
  4619. __IO_REG8    (DM_BK2RE,    0x7F93, __READ_WRITE);
  4620. /* DM breakpoint 2 register high byte */
  4621. __IO_REG8    (DM_BK2RH,    0x7F94, __READ_WRITE);
  4622. /* DM breakpoint 2 register low byte */
  4623. __IO_REG8    (DM_BK2RL,    0x7F95, __READ_WRITE);
  4624. /* DM debug module control register 1 */
  4625. __IO_REG8    (DM_CR1,      0x7F96, __READ_WRITE);
  4626. /* DM debug module control register 2 */
  4627. __IO_REG8    (DM_CR2,      0x7F97, __READ_WRITE);
  4628. /* DM debug module control/status register 1 */
  4629. __IO_REG8    (DM_CSR1,     0x7F98, __READ_WRITE);
  4630. /* DM debug module control/status register 2 */
  4631. __IO_REG8    (DM_CSR2,     0x7F99, __READ_WRITE);
  4632. /* DM enable function register */
  4633. __IO_REG8    (DM_ENFCTR,   0x7F9A, __READ_WRITE);
  4634.  
  4635.  
  4636. /*-------------------------------------------------------------------------
  4637.  *      Interrupt vector numbers
  4638.  *-----------------------------------------------------------------------*/
  4639. #define SPI_TXE_vector                       0x0C
  4640. #define SPI_RXNE_vector                      0x0C
  4641. #define SPI_WKUP_vector                      0x0C
  4642. #define SPI_MODF_vector                      0x0C
  4643. #define SPI_CRCERR_vector                    0x0C
  4644. #define SPI_OVR_vector                       0x0C
  4645. #define TIM1_OVR_TIF_vector                  0x0D
  4646. #define TIM1_OVR_BIF_vector                  0x0D
  4647. #define TIM1_OVR_UIF_vector                  0x0D
  4648. #define TIM1_CAPCOM_CC1IF_vector             0x0E
  4649. #define TIM1_CAPCOM_CC2IF_vector             0x0E
  4650. #define TIM1_CAPCOM_COMIF_vector             0x0E
  4651. #define TIM1_CAPCOM_CC4IF_vector             0x0E
  4652. #define TIM1_CAPCOM_CC3IF_vector             0x0E
  4653. #define TIM2_OVR_UIF_vector                  0x0F
  4654. #define TIM3_OVR_UIF_vector                  0x11
  4655. #define TIM2_CAPCOM_CC3IF_vector             0x10
  4656. #define TIM3_CAPCOM_CC3IF_vector             0x12
  4657. #define TIM2_CAPCOM_CC1IF_vector             0x10
  4658. #define TIM2_CAPCOM_TIF_vector               0x10
  4659. #define TIM3_CAPCOM_TIF_vector               0x12
  4660. #define TIM3_CAPCOM_CC1IF_vector             0x12
  4661. #define TIM3_CAPCOM_CC2IF_vector             0x12
  4662. #define TIM2_CAPCOM_CC2IF_vector             0x10
  4663. #define I2C_SB_vector                        0x15
  4664. #define I2C_ADDR_vector                      0x15
  4665. #define I2C_ADD10_vector                     0x15
  4666. #define I2C_STOPF_vector                     0x15
  4667. #define I2C_BTF_vector                       0x15
  4668. #define I2C_OVR_vector                       0x15
  4669. #define I2C_RXNE_vector                      0x15
  4670. #define I2C_TXE_vector                       0x15
  4671. #define I2C_BERR_vector                      0x15
  4672. #define I2C_ARLO_vector                      0x15
  4673. #define I2C_AF_vector                        0x15
  4674. #define I2C_WUFH_vector                      0x15
  4675. #define UART2_T_TXE_vector                   0x16
  4676. #define UART2_T_TC_vector                    0x16
  4677. #define UART2_R_OR_vector                    0x17
  4678. #define UART2_R_RXNE_vector                  0x17
  4679. #define UART2_R_IDLE_vector                  0x17
  4680. #define UART2_R_PE_vector                    0x17
  4681. #define UART2_R_LBDF_vector                  0x17
  4682. #define ADC1_AWS2_vector                     0x18
  4683. #define ADC1_AWS1_vector                     0x18
  4684. #define ADC1_AWS0_vector                     0x18
  4685. #define ADC1_AWS3_vector                     0x18
  4686. #define ADC1_EOC_vector                      0x18
  4687. #define ADC1_AWS5_vector                     0x18
  4688. #define ADC1_AWS6_vector                     0x18
  4689. #define ADC1_AWS7_vector                     0x18
  4690. #define ADC1_AWS8_vector                     0x18
  4691. #define ADC1_AWS9_vector                     0x18
  4692. #define ADC1_AWDG_vector                     0x18
  4693. #define ADC1_AWS4_vector                     0x18
  4694. #define TIM4_OVR_UIF_vector                  0x19
  4695. #define FLASH_EOP_vector                     0x1A
  4696. #define FLASH_WR_PG_DIS_vector               0x1A
  4697.  
  4698. #ifdef __IAR_SYSTEMS_ICC__
  4699. #pragma language=restore
  4700. #endif
  4701.  
  4702. #endif    /* __IOSTM8S105C6_H__ */
  4703.  
  4704. /*----------------------------------------------
  4705.  *      End of file
  4706.  *--------------------------------------------*/
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!