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stankovic96

[PSDS] booths_algorithm_TB

Nov 8th, 2018
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VHDL 1.03 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4.  
  5. entity tb_sqrt is
  6.   generic(WIDTH:natural:=8);
  7. --  Port ( );
  8. end tb_sqrt;
  9.  
  10. architecture Behavioral of tb_sqrt is
  11.   signal clk_s,reset_s,start_s,ready_s:std_logic;
  12.   signal a_in_s,b_in_s:std_logic_vector(WIDTH-1 downto 0);
  13.   signal res_s:std_logic_vector(2*WIDTH-1 downto 0);
  14. begin
  15.   duv:entity work.booths_algorithm(Behavioral)
  16.     port map(
  17.       clk=>clk_s,
  18.       reset=>reset_s,
  19.       start=>start_s,
  20.       ready=>ready_s,
  21.       a_in=>a_in_s,
  22.       b_in=>b_in_s,
  23.       res=>res_s
  24.       );
  25.   clk_gen:process is
  26.   begin
  27.     clk_s<='0','1' after 100 ns;
  28.     wait for 200 ns;
  29.   end process;
  30.  
  31.   stim_gen:process is
  32.   begin
  33.     wait until falling_edge(clk_s);
  34.     reset_s<='1';
  35.     wait until falling_edge(clk_s);
  36.     reset_s<='0';
  37.     start_s<='0','1' after 200 ns;
  38.     a_in_s<=x"03",x"05" after 4800 ns,x"78" after 9400 ns; --120
  39.     b_in_s<=x"FC",x"FD" after 4800 ns,x"81" after 9400 ns; --  -127 ->   120*(-127)= -15240
  40.     wait;
  41.   end process;
  42.  
  43.  
  44. end Behavioral;
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