LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY test_bench IS
END ENTITY test_bench;

ARCHITECTURE a OF test_bench IS
signal tbclk,tbrst : std_logic;
signal tbcoded : std_logic_vector(7 downto 0);
signal syncro : std_logic;
component lab81 IS
    port( clk : in STD_LOGIC;
        srst : in STD_LOGIC;
        dout : out STD_LOGIC_VECTOR (7 downto 0));
END component;
BEGIN
generate_clk : process begin
    loop
        tbclk <= '0';
        wait for 25 ns;
        tbclk <= '1';
        wait for 25 ns;
        end loop;
end process;
generate_rst : process begin
    tbrst <= '1', '0' after 175 ns;
    wait;
end process;
process(tbclk) begin
    if rising_edge(tbclk) then
        syncro <= tbrst;
    end if;
end process;
b : lab81
port map ( clk => tbclk,
    srst => syncro,
    dout => tbcoded);
END ARCHITECTURE a;