library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;

entity lab101 is
    Port ( clk : in std_logic;
        x1 : in STD_LOGIC_VECTOR (15 downto 0);
        x2 : in STD_LOGIC_VECTOR (7 downto 0);
        dout : out STD_LOGIC_VECTOR (20 downto 0));
end lab101;

architecture Behavioral of lab101 is
signal x11 : std_logic_vector (20 downto 0);
signal x22 : std_logic_vector (20 downto 0);
signal sdout : std_logic_vector (20 downto 0);
begin
x11 <= x1(15) & x1(15) & x1(14 downto 8) & x1(15) & x1(15) & x1(15) & x1(15) & x1(7 downto 0);
x22 <= sxt(x2,21);
process(clk) begin
    if rising_edge(clk) then
        sdout <= signed(x11) + signed(x22);
    end if;
end process;
dout <= sdout;
end Behavioral;