Dragon12_SPI

/***********************************************************************************

  York University CSE3215
  Main.c
  Jan 09, 2006

***********************************************************************************/
#include <hidef.h>            /* common defines and macros */
#include <mc9s12dp256.h>      /* MicroController derivative information */


#pragma LINK_INFO DERIVATIVE "mc9s12dp256b"

void main(void) {

volatile byte data;

//PLL_init();  // set system clock frequency to 24 MHz

  EnableInterrupts;
  // SPI communication initialization as a master
  SPI0BR  = 0b00000011;    // Baud rate = 24MHz/16 = 1.5MHz 0x53;
  SPI0CR2 = 0b00010000;  // SPI0CR2_SPISWAI=1 : Stop SPI clocks when in wait mode
  SPI0CR1 = 0b01010110;  // Enable SPI ; Master mode ; CPHA = 1 ;

  WOMS = 0;

                                                 // SSOE=1 (SS input with MODF feature)
  /*DDRS |= 0x61;   // 0b 0 1 1 0 0 0 0 1 : PS7(SS) and PS4(MISO) are input and PS6(SCK)

                               // and PS5(MOSI) are output, PS0 is output for setting and clearing slave's SS

  PTS &= (~0x01);                  // Low slave's SS*/


  for( ; ; ){

    //PTS &= (~0x01);              // Low slave's SS

    // Send a byte to the slave
    while( SPI0SR_SPTEF == 0); // Wait until SPIDR becomes empty.
    SPI0DR = 0x04;                         //  Clear the flag SPI0SR_STEF

    while( SPI0SR_SPIF == 0 );   // Wait until the end of an SPI transfer.
    data = SPI0DR;                        // Read or write to clear SPI0SR_SPIF flag


  }
}