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Nov 9th, 2017
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  1. void InitCAN_0(uint8_t bootloadMessageID) {              /* General init. No MB IDs initialized */
  2.     uint8_t i;
  3.  
  4.     CAN_0.MCR.B.MDIS = 1;       /* Disable module before selecting clock source*/
  5.     //0-FXOSR 1-BUS CLOCK
  6. //    CAN_0.CTRL1.B.CLKSRC=0;     /* Clock Source = oscillator clock (40 MHz) */
  7.  
  8.     CAN_0.MCR.B.FRZ = 1;
  9.  
  10.     CAN_0.MCR.B.MDIS = 0;       /* Enable module for config. (Sets FRZ, HALT)*/
  11.  
  12.     while (!CAN_0.MCR.B.FRZACK) {} /* Wait for freeze acknowledge to set */
  13.  
  14.     //CAN_0.CTRL1.R = 0x04DB0086;  /* CAN bus: 40 MHz clksrc, 500K bps with 16 tq */
  15.                               /* PRESDIV+1 = Fclksrc/Ftq = 40 MHz/8MHz = 5 */
  16.                               /*    so PRESDIV = 4 */
  17.                               /* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */
  18.                               /* PSEG1 = PSEG2 = 3 */
  19.                               /* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */
  20.                               /* RJW = Resync Jump Width - 1 = 4 = 1 */
  21.                               /* SMP = 1: use 3 bits per CAN sample */
  22.                               /* CLKSRC=0 (unchanged): Fcanclk= Fxtal= 40 MHz*/
  23.  
  24.     for (i=0; i<64; i++) {
  25.     CAN_0.MB[i].CS.B.CODE = 0;   /* Inactivate all message buffers */
  26.     }
  27.     CAN_0.MB[1].CS.B.CODE = 8;     /* Message Buffer 0 set to TX INACTIVE */
  28.  
  29.     CAN_0.MB[0].CS.B.IDE = 0;      /* MB 4 will look for a standard ID */
  30.     CAN_0.MB[0].ID.B.ID_STD = bootloadMessageID; /* MB 4 will look for ID */
  31.     CAN_0.MB[0].CS.B.CODE = 4;     /* MB 4 set to RX EMPTY */
  32.     CAN_0.RXMGMASK.R = 0x1FFFFFFF; /* Global acceptance mask */
  33.  
  34.     CAN_0.CTRL1.B.CLKSRC=0;     /* Clock Source = oscillator clock (40 MHz) */
  35.  
  36.     // Set for baud rate to 1000 1Mbit
  37.     //Prescaler Division Factor: 5
  38.     CAN_0.CTRL1.B.PRESDIV = 4;
  39.     //Re-synchronization Jump Width: 1
  40.     CAN_0.CTRL1.B.RJW = 0;
  41.     //Phase Segment1: 3
  42.     CAN_0.CTRL1.B.PSEG1 = 2;
  43.     //Phase Segment2: 2
  44.     CAN_0.CTRL1.B.PSEG2 = 1;
  45.     //Propagation Segment: 2
  46.     CAN_0.CTRL1.B.PROPSEG = 1;
  47.     //Use 3 bits per CAN sample
  48.     CAN_0.CTRL1.B.SMP=1;
  49.  
  50.     /* Configure the CAN0_TX pin to transmit. */
  51.     SIUL2.MSCR[16].B.SSS = 1;    /* Pad PB0: Source signal is CAN0_TX  */
  52.     SIUL2.MSCR[16].B.OBE = 1;    /* Pad PB0: Output Buffer Enable */
  53.     SIUL2.MSCR[16].B.SRC = 3;    /* Pad PB0: Maximum slew rate */
  54.  
  55.     /* Configure the CAN0_RX pin. */
  56.     SIUL2.MSCR[17].B.IBE = 1;    /* Pad PB1: Enable pad for input - CAN0_RX */
  57.     SIUL2.IMCR[32].B.SSS = 2;   /* CAN0_RX: connected to pad PB1 */
  58.  
  59.     CAN_0.MCR.R = 0x0000003F;       /* Negate FlexCAN 0 halt state for 64 MB */
  60.  
  61.     while (CAN_0.MCR.B.FRZACK & CAN_0.MCR.B.NOTRDY) {} /* Wait to clear */
  62.                  /* Good practice: wait for FRZACK on freeze mode entry/exit */
  63. }
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