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-- Company:
-- Engineer:
--
-- Create Date:    13:32:57 07/14/2012
-- Design Name:
-- Module Name:    ConvBCD - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ConvBCD is
    Port ( InputBin : in  STD_LOGIC_VECTOR (3 downto 0);
           OutputBCD : out  STD_LOGIC_VECTOR (6 downto 0));
end ConvBCD;

architecture Behavioral of ConvBCD is

begin

with InputBin select
    OutputBCD<= "0000001" when "0000",
                    "1001111" when "0001",
                    "0010010" when "0010",
                    "0000110" when "0011",
                    "1001100" when "0100",
                    "0100100" when "0101",
                    "0100000" when "0110",
                    "0001111" when "0111",
                    "0000000" when "1000",
                    "0000100" when "1001",
                    "1111111" when others;

end Behavioral;