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  1. HLE: ! path: /dev_hdd0/game/
  2. LDR: ! Loading 'C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/USRDIR/BOOT.BIN'...
  3. LDR: !  
  4. LDR: ! Mount info:
  5. LDR: ! /dev_hdd0/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd0/
  6. LDR: ! /dev_hdd1/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd1/
  7. LDR: ! /dev_flash/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_flash/
  8. LDR: ! /dev_usb000/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_usb000/
  9. LDR: ! /dev_usb/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_usb000/
  10. LDR: ! /app_home/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
  11. LDR: ! /host_root/ ->
  12. LDR: ! USRDIR/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR
  13. LDR: ! //dev_hdd0/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd0/
  14. LDR: ! / -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
  15. LDR: ! shader/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR/shader/
  16. LDR: ! ps3texture/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR/ps3texture/
  17. LDR: ! /dev_bdvd/PS3_GAME/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
  18. LDR: ! /dev_bdvd/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//../
  19. LDR: !  
  20. MEM: ! Initing memory: m_base_addr = 0x180050000
  21. MEM: ! Memory initialized.
  22. LDR: W Unimplemented function 'cellFsSdataOpenByFd' in 'sys_fs' module
  23. LDR: W Unimplemented function 'cellFsFsync' in 'sys_fs' module
  24. LDR: W Unimplemented function 'sceNpMatching2DestroyContext' in 'sceNp2' module
  25. LDR: W Unimplemented function 'sceNpMatching2GetWorldInfoList' in 'sceNp2' module
  26. LDR: W Unimplemented function 'sceNpMatching2SearchRoom' in 'sceNp2' module
  27. LDR: W Unimplemented function 'sceNpMatching2SignalingGetConnectionStatus' in 'sceNp2' module
  28. LDR: W Unimplemented function 'sceNpMatching2LeaveRoom' in 'sceNp2' module
  29. LDR: W Unimplemented function 'sceNpMatching2SetRoomDataExternal' in 'sceNp2' module
  30. LDR: W Unimplemented function 'sceNpMatching2Term2' in 'sceNp2' module
  31. LDR: W Unimplemented function 'sceNpMatching2GetServerInfo' in 'sceNp2' module
  32. LDR: W Unimplemented function 'sceNpMatching2GetEventData' in 'sceNp2' module
  33. LDR: W Unimplemented function 'sceNp2Init' in 'sceNp2' module
  34. LDR: W Unimplemented function 'sceNpMatching2JoinRoom' in 'sceNp2' module
  35. LDR: W Unimplemented function 'sceNpMatching2GetRoomMemberDataInternalLocal' in 'sceNp2' module
  36. LDR: W Unimplemented function 'sceNpMatching2ContextStartAsync' in 'sceNp2' module
  37. LDR: W Unimplemented function 'sceNpMatching2RegisterContextCallback' in 'sceNp2' module
  38. LDR: W Unimplemented function 'sceNpMatching2SetRoomDataInternal' in 'sceNp2' module
  39. LDR: W Unimplemented function 'sceNpMatching2GetServerIdListLocal' in 'sceNp2' module
  40. LDR: W Unimplemented function 'sceNpMatching2CreateContext' in 'sceNp2' module
  41. LDR: W Unimplemented function 'sceNpMatching2RegisterSignalingCallback' in 'sceNp2' module
  42. LDR: W Unimplemented function 'sceNpMatching2ClearEventData' in 'sceNp2' module
  43. LDR: W Unimplemented function 'sceNp2Term' in 'sceNp2' module
  44. LDR: W Unimplemented function 'sceNpMatching2RegisterRoomEventCallback' in 'sceNp2' module
  45. LDR: W Unimplemented function 'sceNpMatching2GetRoomDataExternalList' in 'sceNp2' module
  46. LDR: W Unimplemented function 'sceNpMatching2CreateJoinRoom' in 'sceNp2' module
  47. LDR: W Unimplemented function 'sceNpMatching2Init2' in 'sceNp2' module
  48. LDR: W Unimplemented function 'sceNpMatching2RegisterRoomMessageCallback' in 'sceNp2' module
  49. LDR: W Unimplemented function 'inet_ntoa' in 'sys_net' module
  50. LDR: W Unimplemented function 'inet_aton' in 'sys_net' module
  51. LDR: W Unimplemented function 'socketselect' in 'sys_net' module
  52. LDR: W Unimplemented function 'cellOskDialogGetInputText' in 'cellSysutil' module
  53. LDR: W Unimplemented function 'cellOskDialogGetSize' in 'cellSysutil' module
  54. LDR: W Unimplemented function 'cellOskDialogUnloadAsync' in 'cellSysutil' module
  55. LDR: W Unimplemented function 'cellSaveDataUserAutoSave' in 'cellSysutil' module
  56. LDR: W Unimplemented function 'cellOskDialogLoadAsync' in 'cellSysutil' module
  57. LDR: W Unimplemented function 'cellOskDialogSetKeyLayoutOption' in 'cellSysutil' module
  58. LDR: W Unimplemented function 'cellOskDialogSetInitialKeyLayout' in 'cellSysutil' module
  59. LDR: W Unimplemented function 'cellSaveDataUserAutoLoad' in 'cellSysutil' module
  60. LDR: W Unimplemented function 'cellAudioAdd6chData' in 'cellAudio' module
  61. LDR: W Unimplemented function 'cellSailGraphicsAdapterGetFrame' in 'cellSail' module
  62. LDR: W Unimplemented function 'cellSailDescriptorCreateDatabase' in 'cellSail' module
  63. LDR: W Unimplemented function 'cellSailPlayerSetSoundAdapter' in 'cellSail' module
  64. LDR: W Unimplemented function 'cellSailGraphicsAdapterPtsToTimePosition' in 'cellSail' module
  65. LDR: W Unimplemented function 'cellSailPlayerFinalize' in 'cellSail' module
  66. LDR: W Unimplemented function 'cellSailPlayerSetGraphicsAdapter' in 'cellSail' module
  67. LDR: W Unimplemented function 'cellSailGraphicsAdapterInitialize' in 'cellSail' module
  68. LDR: W Unimplemented function 'cellSailSoundAdapterSetPreferredFormat' in 'cellSail' module
  69. LDR: W Unimplemented function 'cellSailPlayerInitialize2' in 'cellSail' module
  70. LDR: W Unimplemented function 'cellSailDescriptorDestroyDatabase' in 'cellSail' module
  71. LDR: W Unimplemented function 'cellSailGraphicsAdapterSetPreferredFormat' in 'cellSail' module
  72. LDR: W Unimplemented function 'cellSailMemAllocatorInitialize' in 'cellSail' module
  73. LDR: W Unimplemented function 'cellSailPlayerOpenStream' in 'cellSail' module
  74. LDR: W Unimplemented function 'cellSailSoundAdapterInitialize' in 'cellSail' module
  75. LDR: W Unimplemented function 'cellSailGraphicsAdapterUpdateAvSync' in 'cellSail' module
  76. LDR: W Unimplemented function 'cellSailSoundAdapterPtsToTimePosition' in 'cellSail' module
  77. LDR: W Unimplemented function 'cellSailFutureInitialize' in 'cellSail' module
  78. LDR: W Unimplemented function 'cellSailPlayerSetParameter' in 'cellSail' module
  79. LDR: W Unimplemented function 'cellSailAviMovieGetMovieInfo' in 'cellSail' module
  80. LDR: W Unimplemented function 'cellSailGraphicsAdapterFinalize' in 'cellSail' module
  81. LDR: W Unimplemented function 'cellSailPlayerAddDescriptor' in 'cellSail' module
  82. LDR: W Unimplemented function 'cellSailSoundAdapterGetFrame' in 'cellSail' module
  83. LDR: W Unimplemented function 'cellSailFutureFinalize' in 'cellSail' module
  84. LDR: W Unimplemented function 'cellSailPlayerBoot' in 'cellSail' module
  85. LDR: W Unimplemented function 'cellSailSoundAdapterFinalize' in 'cellSail' module
  86. LDR: W Unimplemented function 'cellSailPlayerCreateDescriptor' in 'cellSail' module
  87. LDR: W Unimplemented function 'cellSailPlayerStart' in 'cellSail' module
  88. LDR: W Unimplemented function 'cellSailSoundAdapterUpdateAvSync' in 'cellSail' module
  89. LDR: W Unimplemented function 'cellSailSoundAdapterGetFormat' in 'cellSail' module
  90. LDR: W Unimplemented function 'cellSailPlayerSetRepeatMode' in 'cellSail' module
  91. LDR: W Unimplemented function 'cellSailGraphicsAdapterGetFormat' in 'cellSail' module
  92. LDR: W Unimplemented function 'sceNpBasicSendMessageGui' in 'sceNp' module
  93. LDR: W Unimplemented function 'sceNpBasicGetFriendListEntry' in 'sceNp' module
  94. LDR: W Unimplemented function 'sceNpScoreGetRankingByRangeAsync' in 'sceNp' module
  95. LDR: W Unimplemented function 'sceNpScoreSetTimeout' in 'sceNp' module
  96. LDR: W Unimplemented function 'sceNpScoreSanitizeCommentAsync' in 'sceNp' module
  97. LDR: W Unimplemented function 'sceNpScoreInit' in 'sceNp' module
  98. LDR: W Unimplemented function 'sceNpScoreGetRankingByNpIdAsync' in 'sceNp' module
  99. LDR: W Unimplemented function 'sceNpBasicRegisterContextSensitiveHandler' in 'sceNp' module
  100. LDR: W Unimplemented function 'sceNpManagerGetCachedInfo' in 'sceNp' module
  101. LDR: W Unimplemented function 'sceNpManagerUnregisterCallback' in 'sceNp' module
  102. LDR: W Unimplemented function 'sceNpBasicSetPresenceDetails2' in 'sceNp' module
  103. LDR: W Unimplemented function 'sceNpLookupInit' in 'sceNp' module
  104. LDR: W Unimplemented function 'sceNpBasicRecvMessageAttachmentLoad' in 'sceNp' module
  105. LDR: W Unimplemented function 'sceNpManagerGetContentRatingFlag' in 'sceNp' module
  106. LDR: W Unimplemented function 'sceNpScoreCreateTransactionCtx' in 'sceNp' module
  107. LDR: W Unimplemented function 'sceNpBasicGetBlockListEntryCount' in 'sceNp' module
  108. LDR: W Unimplemented function 'sceNpLookupPollAsync' in 'sceNp' module
  109. LDR: W Unimplemented function 'sceNpBasicRecvMessageCustom' in 'sceNp' module
  110. LDR: W Unimplemented function 'sceNpLookupTerm' in 'sceNp' module
  111. LDR: W Unimplemented function 'sceNpLookupTitleSmallStorageAsync' in 'sceNp' module
  112. LDR: W Unimplemented function 'sceNpScorePollAsync' in 'sceNp' module
  113. LDR: W Unimplemented function 'sceNpBasicUnregisterHandler' in 'sceNp' module
  114. LDR: W Unimplemented function 'sceNpBasicGetFriendListEntryCount' in 'sceNp' module
  115. LDR: W Unimplemented function 'sceNpScoreCreateTitleCtx' in 'sceNp' module
  116. LDR: W Unimplemented function 'sceNpBasicAddPlayersHistoryAsync' in 'sceNp' module
  117. LDR: W Unimplemented function 'sceNpScoreDestroyTransactionCtx' in 'sceNp' module
  118. LDR: W Unimplemented function 'sceNpLookupCreateTitleCtx' in 'sceNp' module
  119. LDR: W Unimplemented function 'sceNpProfileCallGui' in 'sceNp' module
  120. LDR: W Unimplemented function 'sceNpUtilCmpNpId' in 'sceNp' module
  121. LDR: W Unimplemented function 'sceNpBasicGetEvent' in 'sceNp' module
  122. LDR: W Unimplemented function 'sceNpManagerRegisterCallback' in 'sceNp' module
  123. LDR: W Unimplemented function 'sceNpLookupCreateTransactionCtx' in 'sceNp' module
  124. LDR: W Unimplemented function 'sceNpManagerGetChatRestrictionFlag' in 'sceNp' module
  125. LDR: W Unimplemented function 'sceNpScoreRecordScoreAsync' in 'sceNp' module
  126. LDR: W Unimplemented function 'sceNpBasicGetBlockListEntry' in 'sceNp' module
  127. LDR: W Unimplemented function 'sceNpManagerGetOnlineName' in 'sceNp' module
  128. LDR: W Unimplemented function 'sceNpLookupDestroyTransactionCtx' in 'sceNp' module
  129. LDR: W Unimplemented function 'sceNpManagerGetNpId' in 'sceNp' module
  130. LDR: W Unknown module 'cellSysutilAvc2'
  131. LDR: W Unknown module 'sceNpCommerce2'
  132. LDR: W Unimplemented function 'cellMicOpenEx' in 'cellMic' module
  133. LDR: W Unimplemented function 'cellMicRead' in 'cellMic' module
  134. LDR: W Unimplemented function 'cellMicSetNotifyEventQueue' in 'cellMic' module
  135. LDR: W Unimplemented function 'cellMicClose' in 'cellMic' module
  136. LDR: W Unimplemented function 'cellMicStart' in 'cellMic' module
  137. LDR: W Unimplemented function 'cellMicStop' in 'cellMic' module
  138. LDR: W Unknown module 'cellSysutilAvconfExt'
  139. LDR: W Unimplemented function 'sys_prx_load_module_on_memcontainer_by_fd' in 'sysPrxForUser' module
  140. LDR: W Unimplemented function 'sys_prx_load_module_by_fd' in 'sysPrxForUser' module
  141. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 3
  142. HLE: W {PPU[1] Thread (CPUThread)[0x009d3c34]} memory warning: sys_memory_get_user_memory_size(mem_info_addr=0xd0010c04)
  143. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 4
  144. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 5
  145. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 6
  146. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 7
  147. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 8
  148. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 9
  149. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 10
  150. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 11
  151. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 12
  152. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_RTC)
  153. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_GCM_SYS)
  154. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_IO)
  155. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_USBD)
  156. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_FS)
  157. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_NET)
  158. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_AUDIO)
  159. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_ATRAC3PLUS)
  160. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP2)
  161. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_AVCHAT2)
  162. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_GAME)
  163. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_COMMERCE2)
  164. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_SAVEDATA)
  165. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_USERINFO)
  166. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_TROPHY)
  167. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SAIL)
  168. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_AVCONF_EXT)
  169. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_COMMERCE2)
  170. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 13
  171. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 14
  172. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 15
  173. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 16
  174. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 17
  175. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 18
  176. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 19
  177. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 20
  178. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 21
  179. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 22
  180. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 23
  181. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 24
  182. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [ps3HDDL] (attribute=0x12): sq_id = 25
  183. HLE: W {PPU[1] Thread (CPUThread)[0x009c3910]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  184. HLE: W {PPU[1] Thread (CPUThread)[0x009c3910]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  185. HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  186. HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  187. HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  188. HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  189. HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  190. HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  191. HLE: W {PPU[1] Thread (CPUThread)[0x009c38bc]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  192. HLE: W {PPU[1] Thread (CPUThread)[0x009c38bc]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  193. HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
  194. HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
  195. HLE: W {PPU[1] Thread (CPUThread)[0x007455d4]} sys_spu warning: sys_spu_initialize(max_usable_spu=5, max_raw_spu=1)
  196. HLE: W {PPU[1] Thread (CPUThread)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=0, func_addr=0xcacae0, userdata=0x0)
  197. HLE: E {PPU[1] Thread (CPUThread)[0x00f9b070]} TODO: sceNp2Init
  198. HLE: W {PPU[1] Thread (CPUThread)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd0010520, attributes_addr=0xd0010524, size_addr=0xd0010528, dirName_addr=0xd0010538)
  199. HLE: W {PPU[1] Thread (CPUThread)[0x00fb101c]} cellGame warning: cellGameGetParamInt(id=102, value_addr=0xd090e0)
  200. HLE: W {PPU[1] Thread (CPUThread)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd0010558, usrdirPath_addr=0xd00105d8)
  201. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable(k_licensee_addr=0xf55498, drm_path_addr=0xd000fb60)
  202. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Found DRM license file at /dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT
  203. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Using k_licensee 0xad4d54f97a88778baf7da0bbcad5c8be
  204. LDR: E {PPU[1] Thread (CPUThread)[0x00fa9118]} EDAT: File has invalid NPD header.
  205. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable(k_licensee_addr=0xf55498, drm_path_addr=0xd000fb60)
  206. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Found DRM license file at /dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT
  207. HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Using k_licensee 0xad4d54f97a88778baf7da0bbcad5c8be
  208. LDR: E {PPU[1] Thread (CPUThread)[0x00fa9118]} EDAT: File has invalid NPD header.
  209. HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT" opened: fd = 26
  210. HLE: E {PPU[1] Thread (CPUThread)[0x00c4b028]} sys_fs error: "/dev_hdd0/game/NPUB30817/USRDIR/Default.cfg" not found! flags: 0x00000000
  211. HLE: W {PPU[1] Thread (CPUThread)[0x00fa104c]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_LANG
  212. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_GCM_SYS)
  213. HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_RESC)
  214. HLE: W {PPU[1] Thread (CPUThread)[0x00504960]} sys_spu warning: sys_raw_spu_create(id_addr=0xed6364, attr_addr=0xd0010220)
  215. SPU: E {PPU[1] Thread (CPUThread)[0x00504d10]} RawSPUThread[0]: Read32(MFC_CMDStatus)
  216. SPU: E {PPU[1] Thread (CPUThread)[0x00504d10]} RawSPUThread[0]: Read32(MFC_CMDStatus)
  217. SPU: W {PPU[1] Thread (CPUThread)[0x0050500c]} RawSPUThread[0]: Write32(Prxy_QueryMask, 0x80000000)
  218. SPU: W {PPU[1] Thread (CPUThread)[0x00505010]} RawSPUThread[0]: Write32(Prxy_QueryType, 0x2)
  219. SPU: W {PPU[1] Thread (CPUThread)[0x00505010]} RawSPUThread[0]: Prxy Query Immediate.
  220. SPU: W {PPU[1] Thread (CPUThread)[0x00505020]} RawSPUThread[0]: Read32(MFC_QStatus)
  221. SPU: W {PPU[1] Thread (CPUThread)[0x00505060]} RawSPUThread[0]: Write32(SPU_NPC, 0xe0)
  222. SPU: W {PPU[1] Thread (CPUThread)[0x00504700]} RawSPUThread[0]: Write32(SPU_NPC, 0xe0)
  223. HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmInit(context_addr=0xf6629c,cmdSize=0x10000,ioSize=0xb00000,ioAddress=0x30200000)
  224. HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: *** local memory(addr=0xc0000000, size=0xf900000)
  225. HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmInit(): 256MB io address space used
  226. HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmMapEaIoAddress(ea=0x30200000, io=0x0, size=0xb00000)
  227. RSX: ! {RSXThread} RSX thread started
  228. HLE: W {PPU[1] Thread (CPUThread)[0x00c49070]} cellGcmSys warning: cellGcmSetDebugOutputLevel(level=2)
  229. HLE: E {PPU[1] Thread (CPUThread)[0x00c4916c]} cellGcmSys error: Unimplemented function: cellGcmSetGraphicsHandler
  230. RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
  231. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  232. HLE: W {PPU[1] Thread (CPUThread)[0x00c49094]} cellGcmSys warning: cellGcmMapEaIoAddress(ea=0x30f00000, io=0xe000000, size=0x100000)
  233. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=0)
  234. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=1)
  235. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=2)
  236. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=3)
  237. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=4)
  238. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=5)
  239. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=6)
  240. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=7)
  241. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=8)
  242. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=9)
  243. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=10)
  244. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=11)
  245. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=12)
  246. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=13)
  247. HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=14)
  248. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1
  249. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=0, location=0, offset=253231104, size=7864320, pitch=10240, comp=7, base=1, bank=0)
  250. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (7)
  251. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=0)
  252. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 3
  253. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=1, location=0, offset=245366784, size=7864320, pitch=10240, comp=7, base=121, bank=0)
  254. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (7)
  255. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=1)
  256. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 5
  257. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=2, location=0, offset=241434624, size=3932160, pitch=5120, comp=0, base=0, bank=0)
  258. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=2)
  259. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 7
  260. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=2, location=0, offset=237502464, size=7864320, pitch=5120, comp=0, base=0, bank=0)
  261. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=2)
  262. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 9
  263. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=3, location=0, offset=229638144, size=7864320, pitch=10240, comp=11, base=241, bank=3)
  264. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (11)
  265. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=3)
  266. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: b
  267. HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=0)
  268. HLE: W {PPU[1] Thread (CPUThread)[0x005624f4]} sys_semaphore warning: sys_semaphore_create(sem_addr=0xed6a28, attr_addr=0xd0010120, initial_count=1, max_count=2)
  269. HLE: ! {PPU[1] Thread (CPUThread)[0x005624f4]} *** semaphore created [] (protocol=0x2): id = 28
  270. HLE: W {PPU[1] Thread (CPUThread)[0x00c490f4]} cellGcmSys warning: cellGcmSetFlipHandler(handler_addr=13270752)
  271. HLE: W {PPU[1] Thread (CPUThread)[0x00c49130]} cellGcmSys warning: cellGcmSetVBlankHandler(handler_addr=0xca7f00)
  272. HLE: W {PPU[1] Thread (CPUThread)[0x00fa1010]} cellSysutil warning: cellVideoOutConfigure(videoOut=0, config_addr=0xd00100f0, option_addr=0x0, waitForEvent=0x0)
  273. HLE: W {PPU[1] Thread (CPUThread)[0x00c49064]} cellGcmSys warning: cellGcmSetFlipMode(mode=1)
  274. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  275. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  276. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  277. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  278. HLE: W {PPU[1] Thread (CPUThread)[0x005040cc]} sys_mutex warning: *** mutex created [] (protocol=0x2, recursive=false): id = 29
  279. HLE: W {PPU[1] Thread (CPUThread)[0x00504274]} sys_cond warning: *** condition created [] (mutex_id=29): id = 30
  280. HLE: W {PPU[1] Thread (CPUThread)[0x00c49064]} cellGcmSys warning: cellGcmSetFlipMode(mode=2)
  281. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  282. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  283. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  284. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  285. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  286. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  287. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  288. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  289. HLE: E {PPU[1] Thread (CPUThread)[0x00c4b028]} sys_fs error: "/dev_hdd0/game/NPUB30817/USRDIR/BuildInfo.txt" not found! flags: 0x00000000
  290. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  291. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  292. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  293. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  294. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  295. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  296. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  297. PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [XPlatform::SwitchPs3::Main] (flags=0x0, entry=0xcae990): id = 31
  298. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  299. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  300. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  301. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  302. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  303. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  304. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  305. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  306. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  307. RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
  308. RSX: E {RSXThread} NV4097_SET_POINT_PARAMS_ENABLE: 1
  309. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  310. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  311. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  312. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  313. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  314. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  315. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  316. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  317. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  318. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  319. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  320. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  321. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  322. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  323. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  324. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  325. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  326. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  327. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  328. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  329. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  330. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  331. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  332. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  333. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  334. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  335. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  336. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  337. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  338. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  339. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  340. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: d
  341. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=229376000, size=262144, pitch=2048, comp=0, base=0, bank=0)
  342. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
  343. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  344. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  345. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  346. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  347. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  348. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  349. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  350. RSX: W {RSXThread} FP not found in buffer!
  351. RSX: W {RSXThread} VP not found in buffer!
  352. RSX: ! {RSXThread} Add program (0):
  353. RSX: ! {RSXThread} *** prog id = 3
  354. RSX: ! {RSXThread} *** vp id = 2
  355. RSX: ! {RSXThread} *** fp id = 1
  356. RSX: ! {RSXThread} *** vp data size = 5680
  357. RSX: ! {RSXThread} *** fp data size = 224
  358. RSX: ! {RSXThread} *** vp shader =
  359. #version 330
  360.  
  361. uniform mat4 scaleOffsetMat = mat4(1.0);
  362. vec4 tmp0;
  363. vec4 tmp3;
  364. vec4 cc0 = vec4(0.0);
  365. vec4 tmp5;
  366. vec4 tmp4;
  367. vec4 tmp2;
  368. vec4 tmp1;
  369. vec4 tmp14;
  370. vec4 tmp8;
  371. vec4 tmp6;
  372. vec4 tmp7;
  373. vec4 tmp9;
  374. vec4 tmp10;
  375. vec4 tmp11;
  376. vec4 tmp12;
  377. vec4 tmp13;
  378. vec4 tmp15;
  379. vec4 tmp16;
  380. vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
  381. vec4 dst_reg1 = vec4(0.0);
  382. vec4 dst_reg3 = vec4(0.0);
  383. vec4 dst_reg5 = vec4(0.0);
  384. vec4 dst_reg6 = vec4(0.0);
  385. vec4 dst_reg10 = vec4(0.0);
  386. vec4 dst_reg9 = vec4(0.0);
  387. vec4 dst_reg8 = vec4(0.0);
  388. vec4 dst_reg7 = vec4(0.0);
  389. layout (location = 0) in vec4 in_pos;
  390. layout (location = 2) in vec4 in_normal;
  391. layout (location = 3) in vec4 in_diff_color;
  392. layout (location = 8) in vec4 in_tc0;
  393. layout (location = 9) in vec4 in_tc1;
  394. layout (location = 10) in vec4 in_tc2;
  395. layout (location = 11) in vec4 in_tc3;
  396. uniform vec4 vc[468];
  397. ivec4 a0 = ivec4(0);
  398. out vec4 diff_color;
  399. out vec4 front_diff_color;
  400. out vec4 fogc;
  401. out vec4 tc0;
  402. out vec4 tc1;
  403. out vec4 tc2;
  404. out vec4 tc3;
  405. out vec4 tc9;
  406.  
  407. void func0();
  408.  
  409. void main()
  410. {
  411.         func0();
  412.         gl_Position = dst_reg0;
  413.         diff_color = dst_reg1;
  414.         front_diff_color = dst_reg3;
  415.         fogc = vec4(dst_reg5.x);
  416.         gl_ClipDistance[0] = dst_reg5.y;
  417.         gl_ClipDistance[1] = dst_reg5.z;
  418.         gl_ClipDistance[2] = dst_reg5.w;
  419.         gl_PointSize = dst_reg6.x;
  420.         gl_ClipDistance[3] = dst_reg6.y;
  421.         gl_ClipDistance[4] = dst_reg6.z;
  422.         gl_ClipDistance[5] = dst_reg6.w;
  423.         tc0 = dst_reg7;
  424.         tc1 = dst_reg8;
  425.         tc2 = dst_reg9;
  426.         tc3 = dst_reg10;
  427.         tc9 = dst_reg6;
  428.         gl_Position = gl_Position * scaleOffsetMat;
  429. }
  430.  
  431. void func0()
  432. {
  433.         tmp0.w = vec4(dot(in_pos, vc[263])).w;
  434.         tmp0.z = vec4(dot(in_pos, vc[262])).z;
  435.         tmp0.y = vec4(dot(in_pos, vc[261])).y;
  436.         tmp0.x = vec4(dot(in_pos, vc[260])).x;
  437.         tmp3.w = vec4(dot(in_pos, vc[259])).w;
  438.         tmp3.y = vec4(dot(in_pos, vc[257])).y;
  439.         tmp3.x = vec4(dot(in_pos, vc[256])).x;
  440.         cc0.xy = vc[467].wxww.xy;
  441.         tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
  442.         tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
  443.         tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
  444.         tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
  445.         tmp2 = clamp(in_diff_color, 0.0, 1.0);
  446.         tmp1 = tmp2;
  447.         tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
  448.         tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
  449.         tmp3.z = tmp5.yyyy.z;
  450.         tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
  451.         tmp14.w = abs(tmp5.xxxx).w;
  452.         tmp14.xyz = tmp4.xyzx.xyz;
  453.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
  454.         if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  455.         {
  456.                 tmp1.xyz = vc[463].xxxx.xyz;
  457.                 tmp1.w = vc[463].xxxx.w;
  458.                 tmp4 = in_diff_color;
  459.                 cc0.x = vc[467].zzzz.x;
  460.                 tmp5.xyz = in_diff_color.xyzx.xyz;
  461.                 tmp2.x = vc[462].xxxx.x;
  462.                 cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
  463.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
  464.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
  465.                 if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  466.                 {
  467.                         do
  468.                         {
  469.                                 tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
  470.                                 a0.x = ivec4(tmp2.xxxx).x;
  471.                                 tmp8.z = vc[405].xxxx.z;
  472.                                 tmp2.xyz = vc[463].xxxx.xyz;
  473.                                 tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  474.                                 tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
  475.                                 tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
  476.                                 tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
  477.                                 tmp2.w = vc[463].xxxx.w;
  478.                                 cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  479.                                 cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
  480.                                 cc0.x = vc[411 + a0.x].xxxx.x;
  481.                                 tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
  482.                                 tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  483.                                 tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
  484.                                 tmp6.w = -tmp6.wwww.w;
  485.                                 if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
  486.                                 tmp2.w = tmp6.wwww.w;
  487.                                 tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
  488.                                 tmp6.w = log2(tmp6.wwww).w;
  489.                                 tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
  490.                                 cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
  491.                                 cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
  492.                                 tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  493.                                 tmp5.w = (1.0 / tmp5.wwww).w;
  494.                                 tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
  495.                                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  496.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
  497.                                 cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
  498.                                 tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
  499.                                 tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
  500.                                 tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
  501.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
  502.                                 tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
  503.                                 tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
  504.                                 tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
  505.                                 if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
  506.                                 tmp5.w = (1.0 / tmp2.xxxx).w;
  507.                                 tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
  508.                                 tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
  509.                                 tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
  510.                                 tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
  511.                                 tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
  512.                                 tmp2.w = (tmp2.wwww * tmp5.wwww).w;
  513.                                 tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
  514.                         } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  515.                 }
  516.                 cc0.x = vc[467].yyyy.x;
  517.                 tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  518.                 tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
  519.                 tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
  520.                 tmp1.w = tmp4.wwww.w;
  521.                 tmp2 = clamp(tmp1, 0.0, 1.0);
  522.                 tmp1 = tmp2;
  523.                 if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  524.                 {
  525.                         tmp2.x = vc[462].xxxx.x;
  526.                         cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
  527.                         tmp2.xyz = vc[463].xxxx.xyz;
  528.                         if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  529.                         {
  530.                         tmp2.w = vc[463].xxxx.w;
  531.                                 do
  532.                                 {
  533.                                         tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
  534.                                         a0.x = ivec4(tmp5.wwww).x;
  535.                                         tmp9.z = vc[405].xxxx.z;
  536.                                         tmp6.xyz = vc[463].xxxx.xyz;
  537.                                         tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  538.                                         tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
  539.                                         tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
  540.                                         tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  541.                                         tmp5.w = vc[463].xxxx.w;
  542.                                         cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
  543.                                         cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
  544.                                         cc0.x = vc[411 + a0.x].xxxx.x;
  545.                                         tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
  546.                                         tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  547.                                         tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
  548.                                         tmp8.y = -tmp7.wwww.y;
  549.                                         if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
  550.                                         tmp7.w = log2(tmp8.yyyy).w;
  551.                                         tmp5.w = tmp8.yyyy.w;
  552.                                         tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
  553.                                         tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
  554.                                         cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
  555.                                         cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
  556.                                         tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
  557.                                         tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
  558.                                         tmp6.w = (1.0 / tmp6.wwww).w;
  559.                                         tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
  560.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
  561.                                         cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
  562.                                         tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
  563.                                         tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
  564.                                         tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
  565.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
  566.                                         tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
  567.                                         tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
  568.                                         tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
  569.                                         if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
  570.                                         tmp6.w = (1.0 / tmp6.xxxx).w;
  571.                                         tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
  572.                                         tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
  573.                                         tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
  574.                                         tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
  575.                                         tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
  576.                                         tmp5.w = (tmp5.wwww * tmp6.wwww).w;
  577.                                         tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
  578.                                 } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  579.                         }
  580.                         tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
  581.                         tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  582.                         tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
  583.                         tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
  584.                 }
  585.         }
  586.         tmp4.x = vc[463].xxxx.x;
  587.         tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
  588.         tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
  589.         tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
  590.         cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
  591.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  592.         {
  593.         tmp4 = in_tc0;
  594.                 tmp9.x = vc[400].xxxx.x;
  595.                 tmp7.zw = vc[463].xxxz.zw;
  596.                 tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
  597.                 tmp5 = (tmp3.yyyy * vc[268]);
  598.                 tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
  599.                 tmp7.xy = vc[400].yzyy.xy;
  600.                 tmp4 = in_tc0;
  601.                 tmp6 = (in_pos.yyyy * vc[268]);
  602.                 tmp8.zw = vc[463].zzzw.zw;
  603.                 cc0 = vec4(equal(vc[401], tmp8.zzzz));
  604.                 tmp6 = (in_pos.xxxx * vc[267] + tmp6);
  605.                 tmp6 = (in_pos.zzzz * vc[269] + tmp6);
  606.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
  607.                 cc0 = vec4(equal(vc[401], tmp7.xxxx));
  608.                 tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
  609.                 tmp5 = (tmp3.xxxx * vc[267] + tmp5);
  610.                 tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
  611.                 tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
  612.                 tmp5 = (tmp3.zzzz * vc[269] + tmp5);
  613.                 tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
  614.                 tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
  615.                 tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
  616.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
  617.                 tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  618.                 cc0 = vec4(equal(vc[401], tmp7.yyyy));
  619.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  620.                 tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
  621.                 tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  622.                 tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  623.                 tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
  624.                 tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
  625.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  626.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
  627.                 cc0 = vec4(equal(vc[401], tmp9.xxxx));
  628.                 tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
  629.                 tmp5.w = vc[463].zzzz.w;
  630.                 tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
  631.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  632.                 cc0 = vec4(equal(vc[401], tmp8.wwww));
  633.                 tmp5.xyz = tmp14.xyzx.xyz;
  634.                 tmp5.w = vc[463].zzzz.w;
  635.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  636.         }
  637.         tmp5.x = vc[463].xxxx.x;
  638.         tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
  639.         tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
  640.         tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
  641.         cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
  642.         tmp5 = tmp4;
  643.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  644.         {
  645.         tmp6 = in_tc1;
  646.                 tmp9.zw = vc[463].xxxz.zw;
  647.                 tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  648.                 tmp7 = (tmp3.yyyy * vc[276]);
  649.                 tmp10.xyz = vc[400].xyzx.xyz;
  650.                 tmp6 = in_tc1;
  651.                 tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  652.                 tmp8 = (in_pos.yyyy * vc[276]);
  653.                 tmp11.zw = vc[463].zzzw.zw;
  654.                 cc0 = vec4(equal(vc[399], tmp11.zzzz));
  655.                 tmp8 = (in_pos.xxxx * vc[275] + tmp8);
  656.                 tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
  657.                 tmp8 = (in_pos.zzzz * vc[277] + tmp8);
  658.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
  659.                 cc0 = vec4(equal(vc[399], tmp10.yyyy));
  660.                 tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
  661.                 tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
  662.                 tmp7 = (tmp3.xxxx * vc[275] + tmp7);
  663.                 tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
  664.                 tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
  665.                 tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
  666.                 tmp7 = (tmp3.zzzz * vc[277] + tmp7);
  667.                 tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
  668.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
  669.                 tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  670.                 cc0 = vec4(equal(vc[399], tmp10.zzzz));
  671.                 tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
  672.                 tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
  673.                 tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  674.                 tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
  675.                 tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
  676.                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  677.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
  678.                 cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
  679.                 cc0 = vec4(equal(vc[399], tmp10.xxxx));
  680.                 tmp7.w = vc[463].zzzz.w;
  681.                 tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
  682.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  683.                 cc0 = vec4(equal(vc[399], tmp11.wwww));
  684.                 tmp7.xyz = tmp14.xyzx.xyz;
  685.                 tmp7.w = vc[463].zzzz.w;
  686.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  687.         }
  688.         tmp7.x = vc[463].xxxx.x;
  689.         tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
  690.         tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
  691.         tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
  692.         cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
  693.         tmp7 = tmp6;
  694.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  695.         {
  696.         tmp8 = in_tc2;
  697.                 tmp11.zw = vc[463].xxxz.zw;
  698.                 tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  699.                 tmp9 = (tmp3.yyyy * vc[284]);
  700.                 tmp12.xyz = vc[400].xyzx.xyz;
  701.                 tmp8 = in_tc2;
  702.                 tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  703.                 tmp10 = (in_pos.yyyy * vc[284]);
  704.                 tmp13.zw = vc[463].zzzw.zw;
  705.                 cc0 = vec4(equal(vc[398], tmp13.zzzz));
  706.                 tmp10 = (in_pos.xxxx * vc[283] + tmp10);
  707.                 tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
  708.                 tmp10 = (in_pos.zzzz * vc[285] + tmp10);
  709.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
  710.                 cc0 = vec4(equal(vc[398], tmp12.yyyy));
  711.                 tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
  712.                 tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
  713.                 tmp9 = (tmp3.xxxx * vc[283] + tmp9);
  714.                 tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
  715.                 tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
  716.                 tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
  717.                 tmp9 = (tmp3.zzzz * vc[285] + tmp9);
  718.                 tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
  719.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
  720.                 tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
  721.                 cc0 = vec4(equal(vc[398], tmp12.zzzz));
  722.                 tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
  723.                 tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
  724.                 tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  725.                 tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
  726.                 tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
  727.                 tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
  728.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
  729.                 cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
  730.                 cc0 = vec4(equal(vc[398], tmp12.xxxx));
  731.                 tmp9.w = vc[463].zzzz.w;
  732.                 tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
  733.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  734.                 cc0 = vec4(equal(vc[398], tmp13.wwww));
  735.                 tmp9.xyz = tmp14.xyzx.xyz;
  736.                 tmp9.w = vc[463].zzzz.w;
  737.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  738.         }
  739.         tmp9.x = vc[463].xxxx.x;
  740.         tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
  741.         tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
  742.         tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
  743.         cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
  744.         tmp9 = tmp8;
  745.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  746.         {
  747.         tmp10 = in_tc3;
  748.                 tmp13.zw = vc[463].xxxz.zw;
  749.                 tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  750.                 tmp11 = (tmp3.yyyy * vc[292]);
  751.                 tmp15.xyz = vc[400].xyzx.xyz;
  752.                 tmp10 = in_tc3;
  753.                 tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  754.                 tmp12 = (in_pos.yyyy * vc[292]);
  755.                 tmp16.zw = vc[463].zzzw.zw;
  756.                 cc0 = vec4(equal(vc[397], tmp16.zzzz));
  757.                 tmp12 = (in_pos.xxxx * vc[291] + tmp12);
  758.                 tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
  759.                 tmp12 = (in_pos.zzzz * vc[293] + tmp12);
  760.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
  761.                 cc0 = vec4(equal(vc[397], tmp15.yyyy));
  762.                 tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
  763.                 tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
  764.                 tmp11 = (tmp3.xxxx * vc[291] + tmp11);
  765.                 tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
  766.                 tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
  767.                 tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
  768.                 tmp11 = (tmp3.zzzz * vc[293] + tmp11);
  769.                 tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
  770.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
  771.                 tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
  772.                 cc0 = vec4(equal(vc[397], tmp15.zzzz));
  773.                 tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
  774.                 tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
  775.                 tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  776.                 tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
  777.                 tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
  778.                 tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  779.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
  780.                 cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
  781.                 cc0 = vec4(equal(vc[397], tmp15.xxxx));
  782.                 tmp11.w = vc[463].zzzz.w;
  783.                 tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
  784.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  785.                 cc0 = vec4(equal(vc[397], tmp16.wwww));
  786.                 tmp11.xyz = tmp14.xyzx.xyz;
  787.                 tmp11.w = vc[463].zzzz.w;
  788.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  789.         }
  790.         dst_reg0 = tmp0;
  791.         dst_reg1 = tmp1;
  792.         dst_reg3 = tmp2;
  793.         dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
  794.         dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
  795.         dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
  796.         dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
  797.         dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
  798.         dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
  799.         dst_reg5.x = tmp14.wwww.x;
  800.         tmp0.w = vec4(dot(tmp10, vc[298])).w;
  801.         tmp0.z = vec4(dot(tmp10, vc[297])).z;
  802.         tmp0.y = vec4(dot(tmp10, vc[296])).y;
  803.         tmp0.x = vec4(dot(tmp10, vc[295])).x;
  804.         dst_reg10 = tmp10;
  805.         dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
  806.         dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
  807.         dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
  808.         dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
  809.         dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
  810.         dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
  811.         dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
  812.         cc0.x = vc[396].xxxx.x;
  813.         dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
  814.         dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
  815.         dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
  816.         dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
  817.         dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
  818.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
  819.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
  820.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
  821.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
  822. }
  823.  
  824. RSX: ! {RSXThread} *** fp shader =
  825. #version 330
  826.  
  827. vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
  828. vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
  829. vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
  830. vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
  831. vec4 r4 = vec4(0.0, 0.0, 0.0, 0.0);
  832. in vec4 diff_color;
  833. layout (location = 0) out vec4 ocol0;
  834. layout (location = 2) out vec4 ocol2;
  835. layout (location = 3) out vec4 ocol3;
  836. layout (location = 4) out vec4 ocol4;
  837.  
  838. void main()
  839. {
  840.         h2 = diff_color;
  841.         r0 = h2;
  842.         r2 = h2;
  843.         r3 = h2;
  844.         h2 = diff_color;
  845.         r0 = h2;
  846.         r2 = h2;
  847.         r3 = h2;
  848.         r4 = h2;
  849.         ocol0 = r0;
  850.         ocol2 = r2;
  851.         ocol3 = r3;
  852.         ocol4 = r4;
  853. }
  854.  
  855. RSX: W {RSXThread} New FBO (1280x720)
  856. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  857. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  858. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  859. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  860. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  861. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  862. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  863. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  864. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  865. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: f
  866. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=229113856, size=524288, pitch=2048, comp=0, base=0, bank=0)
  867. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
  868. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  869. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  870. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  871. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  872. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  873. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  874. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  875. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  876. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  877. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  878. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  879. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  880. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  881. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  882. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  883. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  884. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 11
  885. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228851712, size=786432, pitch=2048, comp=0, base=0, bank=0)
  886. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
  887. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  888. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  889. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  890. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  891. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  892. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  893. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  894. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  895. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  896. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  897. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  898. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  899. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  900. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  901. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  902. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  903. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 13
  904. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228589568, size=1048576, pitch=2048, comp=0, base=0, bank=0)
  905. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
  906. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  907. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  908. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  909. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  910. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  911. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  912. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  913. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  914. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  915. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  916. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  917. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  918. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  919. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  920. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  921. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  922. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  923. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  924. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  925. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  926. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  927. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  928. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  929. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  930. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 15
  931. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228327424, size=1310720, pitch=2048, comp=0, base=0, bank=0)
  932. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
  933. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  934. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  935. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  936. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  937. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  938. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  939. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  940. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  941. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  942. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  943. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  944. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  945. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  946. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  947. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  948. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  949. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  950. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  951. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  952. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  953. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  954. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  955. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  956. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  957. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  958. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 17
  959. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=5, location=0, offset=224133120, size=4194304, pitch=4096, comp=10, base=361, bank=3)
  960. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
  961. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=5)
  962. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 19
  963. HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=1)
  964. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  965. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  966. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  967. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  968. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  969. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  970. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  971. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  972. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  973. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  974. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  975. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  976. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1b
  977. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=6, location=0, offset=220200960, size=3932160, pitch=5120, comp=10, base=425, bank=3)
  978. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
  979. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=6)
  980. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1d
  981. HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=2)
  982. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  983. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  984. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  985. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  986. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  987. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  988. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  989. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  990. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  991. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  992. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  993. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  994. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  995. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  996. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  997. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  998. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  999. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1000. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1001. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1002. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  1003. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1004. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1005. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1006. RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1f
  1007. HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=7, location=0, offset=219217920, size=983040, pitch=2560, comp=10, base=485, bank=3)
  1008. HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
  1009. HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=7)
  1010. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1011. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1012. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1013. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1014. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1015. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1016. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  1017. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1018. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1019. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1020. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1021. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1022. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1023. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  1024. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1025. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1026. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1027. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1028. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1029. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1030. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  1031. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1032. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1033. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1034. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1035. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1036. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1037. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  1038. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1039. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1040. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1041. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1042. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1043. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1044. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1045. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1046. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1047. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1048. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1049. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1050. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1051. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1052. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1053. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1054. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1055. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1056. HLE: W {PPU[1] Thread (CPUThread)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=2, func_addr=0xcb00a0, userdata=0x317a8f90)
  1057. HLE: W {PPU[1] Thread (CPUThread)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd000f548, attributes_addr=0xd000f544, size_addr=0xd000f550, dirName_addr=0xd000f560)
  1058. HLE: W {PPU[1] Thread (CPUThread)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd000f580, usrdirPath_addr=0xd000f600)
  1059. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1060. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1061. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1062. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1063. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd0040490, attributes_addr=0xd0040494, size_addr=0xd00404c8, dirName_addr=0xd0040508)
  1064. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd0040610, usrdirPath_addr=0xd0040590)
  1065. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab040]} sceNpTrophy warning: sceNpTrophyCreateContext(context_addr=0x317a9104, commID_addr=0xd0040af0, commSign_addr=0xd0040afc, options=0x0)
  1066. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab010]} sceNpTrophy warning: sceNpTrophyCreateHandle(handle_addr=0x317a9108)
  1067. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9d004]} sys_net warning: sys_net_initialize_network_ex(param_addr=0xd00409d8)
  1068. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9f028]} cellNetCtl error: Unimplemented function: cellNetCtlInit
  1069. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=1, func_addr=0xcafd30, userdata=0x317fb760)
  1070. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9b070]} TODO: sceNp2Init
  1071. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9058]} TODO: sceNpBasicRegisterContextSensitiveHandler
  1072. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9184]} TODO: sceNpManagerRegisterCallback
  1073. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf028]} cellUserInfo warning: cellUserInfoGetList(listNum_addr=0xd00409b8, listBuf_addr=0xd00409e4, currentUserId_addr=0xd00409b4)
  1074. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf004]} cellUserInfo warning: cellUserInfoGetStat(id=1, stat_addr=0xd0040a24)
  1075. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1076. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1077. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1078. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1079. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1080. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1081. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab01c]} sceNpTrophy warning: sceNpTrophyGetRequiredDiskSpace(context=0, handle=757935405, reqspace_addr=0x317a8ed8, options=0x0)
  1082. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} sceNpTrophy warning: sceNpTrophyRegisterContext(context=0, handle=757935405, statusCb_addr=0xcb08f0, arg_addr=0x0, options=0x0)
  1083. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROPCONF.SFM')
  1084. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\ICON0.PNG')
  1085. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\GR001.PNG')
  1086. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP000.PNG')
  1087. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP001.PNG')
  1088. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP002.PNG')
  1089. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP003.PNG')
  1090. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP004.PNG')
  1091. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1092. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1093. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1094. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1095. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1096. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1097. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1098. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1099. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1100. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1101. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1102. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1103. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1104. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1105. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1106. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1107. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1108. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1109. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1110. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1111. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1112. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1113. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1114. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1115. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP005.PNG')
  1116. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP006.PNG')
  1117. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP007.PNG')
  1118. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP008.PNG')
  1119. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP009.PNG')
  1120. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP010.PNG')
  1121. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP011.PNG')
  1122. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP012.PNG')
  1123. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP013.PNG')
  1124. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP014.PNG')
  1125. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP015.PNG')
  1126. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP016.PNG')
  1127. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP017.PNG')
  1128. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP018.PNG')
  1129. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP019.PNG')
  1130. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP020.PNG')
  1131. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP021.PNG')
  1132. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP022.PNG')
  1133. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP023.PNG')
  1134. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP024.PNG')
  1135. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP025.PNG')
  1136. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP026.PNG')
  1137. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP027.PNG')
  1138. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP028.PNG')
  1139. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP029.PNG')
  1140. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1141. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1142. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1143. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1144. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1145. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1146. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1147. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1148. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1149. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1150. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1151. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1152. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1153. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1154. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1155. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1156. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1157. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP030.PNG')
  1158. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP031.PNG')
  1159. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP032.PNG')
  1160. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP033.PNG')
  1161. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP034.PNG')
  1162. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1163. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1164. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1165. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1166. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1167. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1168. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1169. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1170. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1171. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1172. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1173. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1174. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1175. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1176. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1177. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1178. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1179. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1180. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1181. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1182. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1183. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1184. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1185. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1186. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1187. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1188. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1189. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1190. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1191. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1192. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1193. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1194. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1195. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1196. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1197. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1198. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1199. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1200. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1201. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1202. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1203. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1204. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1205. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1206. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1207. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1208. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1209. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1210. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1211. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1212. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1213. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1214. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1215. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1216. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1217. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1218. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1219. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1220. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1221. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1222. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1223. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1224. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1225. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1226. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1227. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf028]} cellUserInfo warning: cellUserInfoGetList(listNum_addr=0xd0040874, listBuf_addr=0xd00408b8, currentUserId_addr=0xd0040878)
  1228. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00600eb8]} Unknown syscall: 872 - 00000368
  1229. HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9064]} TODO: sceNpManagerGetCachedInfo
  1230. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1231. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1232. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1233. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1234. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1235. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1236. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1237. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1238. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1239. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1240. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1241. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1242. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1243. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1244. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1245. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1246. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1247. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1248. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1249. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1250. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1251. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1252. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1253. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1254. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1255. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1256. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1257. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1258. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1259. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1260. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1261. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1262. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1263. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1264. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1265. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1266. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1267. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1268. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1269. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1270. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1271. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1272. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1273. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1274. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1275. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1276. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1277. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1278. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1279. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1280. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1281. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1282. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1283. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1284. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1285. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1286. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1287. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1288. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1289. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1290. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1291. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1292. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1293. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1294. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1295. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1296. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1297. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1298. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1299. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1300. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1301. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1302. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1303. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1304. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1305. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1306. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1307. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1308. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1309. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1310. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1311. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1312. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1313. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1314. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1315. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1316. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1317. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1318. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1319. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1320. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1321. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1322. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1323. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1324. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1325. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1326. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1327. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1328. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1329. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1330. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1331. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1332. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1333. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1334. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1335. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1336. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1337. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1338. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1339. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1340. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1341. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1342. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1343. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1344. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1345. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1346. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1347. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1348. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1349. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1350. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1351. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1352. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1353. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1354. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1355. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1356. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1357. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1358. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1359. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1360. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1361. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1362. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1363. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1364. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1365. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1366. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1367. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1368. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1369. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1370. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1371. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1372. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1373. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1374. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1375. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1376. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1377. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1378. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1379. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1380. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1381. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1382. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1383. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1384. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1385. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1386. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1387. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1388. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1389. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1390. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1391. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1392. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1393. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1394. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1395. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1396. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1397. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1398. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1399. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1400. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1401. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1402. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1403. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1404. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1405. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1406. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1407. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1408. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1409. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1410. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1411. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1412. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1413. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1414. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1415. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1416. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1417. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1418. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1419. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1420. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1421. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1422. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1423. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1424. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1425. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1426. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1427. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1428. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1429. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1430. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1431. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1432. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1433. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1434. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1435. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1436. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1437. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1438. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1439. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1440. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1441. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1442. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1443. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1444. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1445. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1446. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1447. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1448. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1449. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1450. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1451. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1452. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1453. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1454. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1455. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1456. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1457. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1458. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1459. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1460. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1461. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1462. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1463. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1464. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1465. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1466. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1467. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1468. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1469. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1470. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1471. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1472. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1473. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1474. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1475. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1476. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1477. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1478. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1479. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1480. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1481. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1482. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1483. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1484. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1485. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1486. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1487. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1488. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1489. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1490. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1491. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1492. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1493. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1494. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1495. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1496. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1497. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1498. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1499. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1500. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1501. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1502. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1503. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1504. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1505. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1506. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1507. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1508. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1509. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1510. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1511. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1512. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1513. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1514. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1515. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1516. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1517. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1518. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1519. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1520. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1521. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1522. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1523. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1524. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1525. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1526. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1527. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1528. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1529. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1530. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1531. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1532. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1533. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1534. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1535. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1536. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1537. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1538. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1539. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1540. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1541. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1542. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1543. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1544. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1545. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1546. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1547. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1548. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1549. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1550. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1551. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1552. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1553. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1554. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1555. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1556. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1557. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1558. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1559. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1560. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1561. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1562. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1563. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1564. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1565. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1566. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1567. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1568. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1569. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1570. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1571. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1572. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1573. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1574. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1575. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1576. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1577. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1578. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1579. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1580. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1581. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1582. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1583. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1584. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1585. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1586. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1587. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1588. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1589. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1590. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1591. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1592. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1593. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1594. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1595. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1596. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1597. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1598. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1599. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1600. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1601. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1602. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1603. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1604. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1605. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1606. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1607. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1608. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1609. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1610. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1611. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1612. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1613. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1614. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1615. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1616. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1617. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1618. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1619. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1620. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1621. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1622. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1623. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1624. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1625. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1626. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1627. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1628. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1629. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1630. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1631. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1632. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1633. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1634. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1635. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1636. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1637. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1638. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1639. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1640. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1641. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1642. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1643. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1644. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1645. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1646. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1647. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1648. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1649. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1650. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1651. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1652. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1653. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1654. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1655. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1656. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1657. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1658. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1659. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1660. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1661. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1662. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1663. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1664. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1665. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1666. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1667. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1668. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1669. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1670. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1671. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1672. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1673. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1674. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1675. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1676. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1677. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1678. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1679. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1680. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1681. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1682. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1683. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1684. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1685. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1686. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1687. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1688. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1689. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1690. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1691. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1692. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1693. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1694. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1695. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1696. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1697. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1698. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1699. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1700. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1701. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1702. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1703. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1704. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1705. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1706. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1707. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1708. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1709. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1710. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1711. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1712. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1713. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1714. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1715. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1716. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1717. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1718. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1719. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1720. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1721. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1722. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1723. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1724. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1725. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1726. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1727. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1728. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1729. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1730. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1731. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1732. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1733. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1734. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1735. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1736. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1737. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1738. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1739. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1740. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1741. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1742. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1743. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1744. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1745. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1746. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1747. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1748. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1749. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1750. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1751. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1752. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1753. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1754. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1755. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1756. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1757. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1758. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1759. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1760. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1761. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1762. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1763. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1764. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1765. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1766. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1767. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1768. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1769. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1770. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1771. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1772. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1773. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1774. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1775. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1776. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1777. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1778. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1779. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1780. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1781. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1782. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1783. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1784. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1785. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1786. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1787. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1788. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1789. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1790. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1791. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1792. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1793. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1794. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1795. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1796. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1797. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1798. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1799. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1800. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1801. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1802. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1803. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1804. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1805. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1806. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1807. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1808. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1809. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1810. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1811. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1812. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1813. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1814. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1815. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1816. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1817. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1818. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1819. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1820. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1821. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1822. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1823. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1824. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1825. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1826. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1827. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1828. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1829. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1830. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1831. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1832. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1833. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1834. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1835. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1836. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1837. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1838. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1839. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1840. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1841. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1842. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1843. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1844. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1845. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1846. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1847. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1848. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1849. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1850. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1851. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1852. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1853. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1854. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1855. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1856. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1857. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1858. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1859. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1860. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1861. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1862. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1863. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1864. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1865. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1866. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1867. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1868. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1869. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1870. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1871. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1872. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1873. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1874. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1875. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1876. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1877. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1878. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1879. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1880. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1881. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1882. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1883. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1884. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1885. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1886. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1887. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1888. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1889. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1890. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1891. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1892. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1893. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1894. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1895. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1896. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1897. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1898. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1899. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1900. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1901. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1902. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1903. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1904. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1905. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1906. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1907. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1908. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1909. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1910. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1911. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1912. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1913. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1914. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1915. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1916. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1917. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1918. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1919. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1920. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1921. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1922. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1923. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1924. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1925. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1926. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1927. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1928. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1929. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1930. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1931. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1932. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1933. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1934. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1935. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1936. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1937. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1938. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1939. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1940. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1941. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1942. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1943. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1944. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1945. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1946. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1947. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1948. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1949. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1950. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1951. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1952. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1953. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1954. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1955. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1956. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1957. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1958. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1959. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1960. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1961. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1962. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1963. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1964. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  1965. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  1966. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  1967. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  1968. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  1969. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  1970. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  1971. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  1972. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  1973. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  1974. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  1975. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1976. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1977. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1978. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1979. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1980. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1981. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  1982. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1983. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  1984. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  1985. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1986. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1987. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1988. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1989. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1990. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1991. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1992. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  1993. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1994. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  1995. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  1996. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1997. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  1998. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  1999. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2000. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2001. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2002. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2003. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2004. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2005. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2006. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2007. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2008. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2009. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2010. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2011. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2012. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2013. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2014. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2015. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2016. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2017. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2018. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2019. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2020. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2021. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2022. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2023. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2024. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2025. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2026. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2027. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2028. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2029. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2030. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2031. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2032. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2033. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2034. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2035. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2036. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2037. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2038. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2039. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2040. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2041. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2042. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2043. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2044. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2045. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2046. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2047. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2048. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2049. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2050. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2051. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2052. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2053. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2054. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2055. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2056. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2057. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2058. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2059. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2060. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2061. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2062. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2063. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2064. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2065. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2066. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2067. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2068. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2069. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2070. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2071. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2072. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2073. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2074. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2075. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2076. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2077. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2078. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2079. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2080. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2081. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2082. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2083. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2084. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2085. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2086. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2087. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2088. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2089. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2090. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2091. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2092. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2093. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2094. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2095. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2096. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2097. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2098. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2099. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2100. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2101. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2102. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2103. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2104. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2105. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2106. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2107. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2108. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2109. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2110. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2111. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2112. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2113. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2114. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2115. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2116. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2117. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2118. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2119. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2120. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2121. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2122. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2123. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2124. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2125. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2126. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2127. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2128. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2129. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2130. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2131. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2132. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2133. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2134. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2135. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2136. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2137. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2138. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2139. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2140. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2141. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2142. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2143. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2144. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2145. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2146. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2147. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2148. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2149. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2150. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2151. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2152. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2153. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2154. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2155. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2156. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2157. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2158. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2159. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2160. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2161. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2162. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2163. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2164. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2165. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2166. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2167. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2168. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2169. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2170. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2171. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2172. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2173. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2174. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2175. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2176. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2177. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2178. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2179. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2180. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2181. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2182. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2183. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2184. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2185. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2186. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2187. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2188. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2189. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2190. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2191. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2192. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2193. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2194. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2195. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2196. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2197. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2198. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2199. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2200. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2201. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2202. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2203. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2204. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2205. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2206. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2207. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2208. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2209. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2210. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2211. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2212. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2213. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2214. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2215. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2216. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2217. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2218. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2219. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2220. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2221. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2222. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2223. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2224. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2225. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2226. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2227. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2228. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2229. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2230. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2231. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2232. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2233. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2234. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2235. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2236. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2237. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2238. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2239. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2240. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2241. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2242. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2243. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2244. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2245. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2246. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2247. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2248. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2249. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2250. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2251. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2252. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2253. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2254. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2255. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2256. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2257. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2258. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2259. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2260. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2261. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2262. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2263. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2264. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2265. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2266. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2267. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2268. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2269. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2270. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2271. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2272. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2273. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2274. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2275. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2276. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2277. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2278. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2279. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2280. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2281. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2282. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2283. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2284. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2285. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2286. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2287. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2288. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2289. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2290. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2291. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2292. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2293. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2294. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2295. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2296. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2297. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2298. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2299. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2300. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2301. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2302. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2303. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2304. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2305. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2306. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2307. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2308. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2309. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2310. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2311. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2312. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2313. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2314. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2315. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2316. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2317. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2318. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2319. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2320. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2321. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2322. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2323. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2324. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2325. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2326. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2327. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2328. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2329. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2330. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2331. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2332. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2333. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2334. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2335. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2336. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2337. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2338. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2339. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2340. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2341. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2342. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2343. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2344. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2345. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2346. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2347. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2348. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2349. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2350. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2351. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2352. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2353. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2354. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2355. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2356. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2357. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2358. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2359. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2360. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2361. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2362. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2363. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2364. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2365. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2366. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2367. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2368. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2369. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2370. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2371. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2372. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2373. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2374. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2375. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2376. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2377. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2378. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2379. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2380. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2381. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2382. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2383. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2384. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2385. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2386. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2387. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2388. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2389. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2390. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2391. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2392. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2393. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2394. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2395. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2396. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2397. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2398. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2399. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2400. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2401. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2402. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2403. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2404. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2405. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2406. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2407. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2408. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2409. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2410. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2411. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2412. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2413. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2414. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2415. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2416. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2417. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2418. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2419. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2420. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2421. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2422. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2423. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2424. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2425. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2426. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2427. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2428. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2429. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2430. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2431. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2432. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2433. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2434. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2435. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2436. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2437. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2438. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2439. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2440. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2441. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2442. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2443. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2444. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2445. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2446. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2447. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2448. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2449. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2450. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2451. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2452. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2453. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2454. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2455. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2456. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2457. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2458. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2459. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2460. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2461. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2462. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2463. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2464. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2465. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2466. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2467. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2468. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2469. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2470. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2471. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2472. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2473. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2474. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2475. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2476. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2477. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2478. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2479. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2480. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2481. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2482. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2483. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2484. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2485. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2486. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2487. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2488. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2489. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2490. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2491. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2492. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2493. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2494. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2495. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2496. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2497. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2498. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2499. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2500. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2501. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2502. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2503. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2504. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2505. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2506. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2507. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2508. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2509. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2510. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2511. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2512. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2513. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2514. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2515. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2516. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2517. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2518. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2519. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2520. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2521. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2522. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2523. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2524. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2525. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2526. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2527. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2528. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2529. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2530. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2531. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2532. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2533. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2534. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2535. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2536. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2537. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2538. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2539. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2540. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2541. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2542. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2543. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2544. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2545. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2546. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2547. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2548. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2549. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2550. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2551. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2552. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2553. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2554. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2555. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2556. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2557. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2558. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2559. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2560. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2561. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2562. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2563. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2564. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2565. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2566. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2567. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2568. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2569. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2570. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2571. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2572. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2573. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2574. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2575. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2576. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2577. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2578. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2579. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2580. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2581. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2582. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2583. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2584. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2585. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2586. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2587. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2588. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2589. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2590. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2591. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2592. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2593. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2594. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2595. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2596. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2597. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2598. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2599. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2600. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2601. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2602. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2603. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2604. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2605. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2606. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2607. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2608. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2609. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2610. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2611. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2612. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2613. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2614. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2615. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2616. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2617. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2618. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2619. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2620. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2621. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2622. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2623. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2624. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2625. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2626. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2627. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2628. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2629. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2630. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2631. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2632. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2633. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2634. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2635. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2636. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2637. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2638. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2639. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2640. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2641. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2642. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2643. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2644. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2645. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2646. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2647. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2648. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2649. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2650. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2651. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2652. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2653. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2654. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2655. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2656. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2657. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2658. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2659. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2660. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2661. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2662. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2663. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2664. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2665. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2666. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2667. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2668. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2669. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2670. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2671. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2672. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2673. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2674. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2675. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2676. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2677. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2678. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2679. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2680. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2681. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2682. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2683. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2684. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2685. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2686. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2687. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2688. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2689. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2690. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2691. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2692. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2693. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2694. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2695. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2696. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2697. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2698. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2699. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2700. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2701. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2702. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2703. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2704. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2705. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2706. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2707. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2708. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2709. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2710. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2711. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2712. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2713. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2714. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2715. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2716. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2717. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2718. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2719. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2720. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2721. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2722. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2723. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2724. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2725. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2726. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2727. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2728. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2729. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2730. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2731. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2732. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2733. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2734. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2735. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2736. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2737. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2738. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2739. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2740. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2741. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2742. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2743. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2744. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2745. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2746. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2747. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2748. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2749. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2750. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2751. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2752. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2753. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2754. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2755. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2756. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2757. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2758. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2759. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2760. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2761. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2762. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2763. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2764. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2765. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2766. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2767. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2768. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2769. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2770. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2771. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2772. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2773. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2774. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2775. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2776. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2777. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2778. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2779. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2780. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2781. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2782. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2783. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2784. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2785. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2786. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2787. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2788. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2789. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2790. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2791. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2792. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2793. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2794. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2795. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2796. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2797. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2798. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2799. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2800. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2801. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2802. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2803. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2804. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2805. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2806. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2807. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2808. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2809. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2810. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2811. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2812. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2813. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2814. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2815. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2816. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2817. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2818. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2819. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2820. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2821. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2822. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2823. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2824. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2825. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2826. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2827. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2828. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2829. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2830. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2831. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2832. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2833. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2834. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2835. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2836. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2837. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2838. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2839. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2840. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2841. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2842. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2843. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2844. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2845. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2846. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2847. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2848. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2849. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2850. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2851. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2852. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2853. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2854. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2855. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2856. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2857. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2858. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2859. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2860. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2861. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2862. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2863. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2864. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2865. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2866. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2867. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2868. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2869. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2870. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2871. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2872. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2873. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2874. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2875. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2876. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2877. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2878. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2879. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2880. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2881. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2882. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2883. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2884. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2885. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2886. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2887. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2888. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2889. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2890. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2891. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2892. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2893. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2894. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2895. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2896. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2897. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2898. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2899. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2900. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2901. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2902. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2903. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2904. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2905. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2906. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2907. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2908. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2909. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2910. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2911. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2912. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2913. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2914. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2915. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2916. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2917. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2918. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2919. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2920. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2921. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2922. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2923. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2924. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2925. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2926. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2927. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2928. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2929. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2930. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2931. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2932. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2933. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2934. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2935. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2936. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2937. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2938. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2939. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2940. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2941. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2942. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2943. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2944. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2945. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2946. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2947. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2948. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2949. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2950. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2951. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2952. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2953. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2954. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2955. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2956. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2957. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2958. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  2959. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2960. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2961. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2962. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2963. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2964. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2965. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  2966. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2967. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  2968. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  2969. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2970. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2971. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2972. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2973. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2974. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2975. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2976. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  2977. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2978. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2979. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2980. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2981. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  2982. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  2983. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2984. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2985. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2986. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2987. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  2988. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  2989. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  2990. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  2991. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  2992. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  2993. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  2994. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  2995. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  2996. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  2997. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  2998. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  2999. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3000. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3001. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3002. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3003. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3004. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3005. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3006. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3007. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3008. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3009. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3010. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3011. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3012. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3013. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3014. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3015. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3016. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3017. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3018. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3019. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3020. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3021. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3022. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3023. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3024. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3025. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3026. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3027. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3028. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3029. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3030. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3031. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3032. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3033. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3034. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3035. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3036. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3037. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3038. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3039. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3040. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3041. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3042. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3043. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3044. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3045. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3046. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3047. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3048. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3049. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3050. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3051. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3052. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3053. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3054. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3055. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3056. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3057. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3058. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3059. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3060. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3061. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3062. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3063. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3064. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3065. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3066. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3067. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3068. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3069. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3070. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3071. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3072. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3073. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3074. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3075. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3076. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3077. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3078. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3079. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3080. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3081. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3082. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3083. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3084. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3085. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3086. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3087. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3088. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3089. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3090. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3091. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3092. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3093. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3094. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3095. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3096. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3097. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3098. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3099. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3100. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3101. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3102. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3103. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3104. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3105. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3106. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3107. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3108. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3109. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3110. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3111. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3112. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3113. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3114. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3115. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3116. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3117. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3118. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3119. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3120. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3121. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3122. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3123. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3124. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3125. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3126. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3127. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3128. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3129. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3130. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3131. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3132. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3133. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3134. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3135. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3136. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3137. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3138. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3139. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3140. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3141. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3142. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3143. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3144. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3145. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3146. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3147. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3148. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3149. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3150. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3151. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3152. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3153. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3154. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3155. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3156. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3157. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3158. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3159. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3160. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3161. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3162. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3163. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3164. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3165. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3166. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3167. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3168. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3169. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3170. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3171. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3172. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3173. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3174. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3175. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3176. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3177. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3178. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3179. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3180. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3181. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3182. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3183. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3184. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3185. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3186. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3187. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3188. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3189. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3190. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3191. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3192. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3193. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3194. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3195. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3196. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3197. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3198. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3199. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3200. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3201. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3202. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3203. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3204. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3205. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3206. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3207. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3208. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3209. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3210. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3211. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3212. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3213. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3214. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3215. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3216. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3217. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3218. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3219. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3220. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3221. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3222. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3223. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3224. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3225. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3226. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3227. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3228. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3229. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3230. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3231. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3232. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3233. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3234. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3235. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3236. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3237. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3238. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3239. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3240. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3241. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3242. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3243. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3244. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3245. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3246. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3247. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3248. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3249. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3250. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3251. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3252. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3253. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3254. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3255. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3256. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3257. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3258. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3259. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3260. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3261. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3262. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3263. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3264. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3265. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3266. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3267. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3268. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3269. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3270. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3271. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3272. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3273. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3274. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3275. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3276. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3277. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3278. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3279. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3280. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3281. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3282. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3283. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3284. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3285. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3286. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3287. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3288. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3289. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3290. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3291. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3292. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3293. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3294. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3295. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3296. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3297. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3298. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3299. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3300. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3301. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3302. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3303. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3304. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3305. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3306. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3307. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3308. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3309. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3310. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3311. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3312. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3313. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3314. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3315. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3316. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3317. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3318. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3319. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3320. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3321. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3322. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3323. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3324. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3325. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3326. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3327. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3328. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3329. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3330. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3331. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3332. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3333. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3334. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3335. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3336. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3337. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3338. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3339. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3340. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3341. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3342. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3343. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3344. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3345. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3346. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3347. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3348. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3349. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3350. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3351. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3352. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3353. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3354. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3355. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3356. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3357. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3358. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3359. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3360. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3361. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3362. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3363. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3364. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3365. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3366. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3367. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3368. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3369. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3370. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3371. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3372. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3373. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3374. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3375. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3376. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3377. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3378. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3379. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3380. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3381. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3382. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3383. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3384. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3385. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3386. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3387. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3388. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3389. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3390. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3391. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3392. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3393. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3394. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3395. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3396. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3397. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3398. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3399. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3400. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3401. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3402. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3403. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3404. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3405. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3406. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3407. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3408. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3409. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3410. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3411. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3412. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3413. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3414. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3415. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3416. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3417. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3418. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3419. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3420. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3421. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3422. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3423. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3424. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3425. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3426. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3427. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3428. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3429. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3430. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3431. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3432. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3433. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3434. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3435. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3436. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3437. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3438. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3439. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3440. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3441. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3442. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3443. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3444. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3445. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3446. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3447. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3448. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3449. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3450. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3451. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3452. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3453. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3454. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3455. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3456. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3457. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3458. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3459. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3460. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3461. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3462. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3463. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3464. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3465. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3466. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3467. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3468. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3469. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3470. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3471. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3472. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3473. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3474. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3475. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3476. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3477. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3478. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3479. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3480. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3481. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3482. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3483. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3484. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3485. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3486. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3487. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3488. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3489. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3490. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3491. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3492. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3493. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3494. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3495. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3496. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3497. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3498. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3499. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3500. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3501. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3502. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3503. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3504. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3505. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3506. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3507. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3508. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3509. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3510. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3511. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3512. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3513. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3514. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3515. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3516. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3517. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3518. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3519. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3520. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3521. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3522. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3523. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3524. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3525. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3526. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3527. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3528. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3529. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3530. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3531. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3532. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3533. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3534. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3535. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3536. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3537. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3538. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3539. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3540. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3541. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3542. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3543. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3544. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3545. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3546. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3547. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3548. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3549. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3550. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3551. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3552. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3553. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3554. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3555. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3556. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3557. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3558. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3559. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3560. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3561. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3562. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3563. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3564. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3565. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3566. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3567. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3568. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3569. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3570. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3571. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3572. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3573. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3574. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3575. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3576. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3577. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3578. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3579. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3580. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3581. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3582. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3583. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3584. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3585. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3586. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3587. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3588. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3589. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3590. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3591. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3592. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3593. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3594. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3595. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3596. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3597. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3598. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3599. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3600. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3601. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3602. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3603. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3604. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3605. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3606. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3607. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3608. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3609. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3610. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3611. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3612. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3613. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3614. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3615. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3616. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3617. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3618. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3619. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3620. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3621. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3622. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3623. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3624. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3625. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3626. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3627. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3628. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3629. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3630. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3631. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3632. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3633. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3634. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3635. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3636. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3637. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3638. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3639. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3640. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3641. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3642. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3643. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3644. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3645. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3646. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3647. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3648. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3649. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3650. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3651. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3652. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3653. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3654. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3655. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3656. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3657. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3658. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3659. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3660. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3661. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3662. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3663. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3664. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3665. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3666. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3667. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3668. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3669. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3670. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3671. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3672. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3673. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3674. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3675. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3676. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3677. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3678. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3679. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3680. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3681. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3682. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3683. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3684. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3685. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3686. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3687. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3688. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3689. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3690. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3691. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3692. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3693. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3694. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3695. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3696. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3697. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3698. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3699. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3700. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3701. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3702. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3703. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3704. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3705. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3706. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3707. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3708. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3709. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3710. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3711. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3712. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3713. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3714. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3715. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3716. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3717. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3718. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3719. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3720. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3721. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3722. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3723. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3724. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3725. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3726. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3727. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3728. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3729. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3730. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3731. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3732. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3733. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3734. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3735. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3736. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3737. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3738. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3739. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3740. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3741. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3742. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3743. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3744. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3745. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3746. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3747. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3748. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3749. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3750. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3751. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3752. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3753. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3754. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3755. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3756. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3757. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3758. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3759. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3760. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3761. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3762. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3763. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3764. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3765. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3766. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3767. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3768. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3769. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3770. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3771. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3772. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3773. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3774. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3775. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3776. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3777. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3778. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3779. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3780. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3781. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3782. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3783. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3784. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3785. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3786. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3787. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3788. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3789. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3790. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3791. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3792. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3793. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3794. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3795. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3796. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3797. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3798. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3799. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3800. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3801. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3802. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3803. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3804. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3805. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3806. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3807. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3808. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3809. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3810. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3811. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3812. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3813. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3814. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3815. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3816. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3817. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3818. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3819. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3820. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3821. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3822. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3823. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3824. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3825. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3826. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3827. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3828. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3829. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3830. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3831. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3832. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3833. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3834. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3835. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3836. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3837. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3838. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3839. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3840. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3841. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3842. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3843. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3844. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3845. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3846. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3847. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3848. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3849. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3850. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3851. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3852. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3853. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3854. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3855. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3856. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3857. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3858. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3859. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3860. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3861. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3862. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3863. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3864. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3865. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3866. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3867. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3868. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3869. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3870. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3871. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3872. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3873. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3874. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3875. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3876. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3877. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3878. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3879. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3880. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3881. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3882. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3883. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3884. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3885. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3886. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3887. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3888. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3889. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3890. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3891. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3892. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3893. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3894. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3895. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3896. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3897. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3898. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3899. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3900. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3901. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3902. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3903. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3904. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3905. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3906. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3907. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3908. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3909. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3910. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3911. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3912. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3913. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3914. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3915. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3916. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3917. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3918. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3919. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3920. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3921. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3922. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3923. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3924. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3925. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3926. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3927. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3928. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3929. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3930. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3931. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3932. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3933. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3934. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3935. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3936. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3937. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3938. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3939. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3940. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3941. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3942. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3943. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3944. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3945. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3946. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3947. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3948. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3949. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3950. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3951. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3952. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3953. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3954. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3955. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3956. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3957. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3958. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3959. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3960. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3961. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3962. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3963. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3964. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3965. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3966. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  3967. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3968. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3969. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3970. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3971. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3972. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3973. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  3974. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  3975. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  3976. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  3977. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  3978. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  3979. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  3980. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  3981. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  3982. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  3983. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  3984. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3985. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3986. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3987. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3988. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3989. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3990. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  3991. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3992. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  3993. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  3994. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  3995. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3996. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  3997. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  3998. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  3999. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4000. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4001. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4002. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4003. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4004. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4005. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4006. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4007. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4008. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4009. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4010. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4011. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4012. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4013. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4014. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4015. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4016. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4017. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4018. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4019. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4020. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4021. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4022. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4023. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4024. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4025. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4026. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4027. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4028. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4029. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4030. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4031. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4032. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4033. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4034. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4035. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4036. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4037. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4038. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4039. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4040. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4041. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4042. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4043. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4044. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4045. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4046. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4047. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4048. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4049. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4050. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4051. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4052. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4053. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4054. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4055. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4056. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4057. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4058. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4059. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4060. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4061. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4062. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4063. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4064. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4065. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4066. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4067. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4068. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4069. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4070. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4071. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4072. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4073. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4074. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4075. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4076. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4077. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4078. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4079. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4080. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4081. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4082. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4083. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4084. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4085. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4086. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4087. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4088. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4089. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4090. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4091. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4092. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4093. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4094. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4095. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4096. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4097. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4098. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4099. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4100. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4101. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4102. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4103. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4104. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4105. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4106. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4107. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4108. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4109. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4110. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4111. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4112. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4113. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4114. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4115. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4116. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4117. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4118. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4119. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4120. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4121. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4122. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4123. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4124. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4125. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4126. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4127. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4128. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4129. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4130. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4131. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4132. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4133. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4134. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4135. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4136. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4137. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4138. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4139. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4140. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4141. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4142. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4143. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4144. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4145. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4146. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4147. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4148. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4149. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4150. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4151. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4152. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4153. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4154. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4155. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4156. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4157. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4158. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4159. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4160. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4161. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4162. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4163. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4164. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4165. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4166. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4167. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4168. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4169. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4170. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4171. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4172. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4173. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4174. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4175. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4176. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4177. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4178. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4179. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4180. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4181. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4182. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4183. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4184. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4185. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4186. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4187. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4188. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4189. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4190. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4191. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4192. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4193. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4194. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4195. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4196. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4197. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4198. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4199. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4200. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4201. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4202. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4203. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4204. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4205. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4206. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4207. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4208. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4209. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4210. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4211. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4212. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4213. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4214. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4215. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4216. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4217. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4218. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4219. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4220. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4221. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4222. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4223. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4224. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4225. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4226. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4227. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4228. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4229. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4230. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4231. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4232. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4233. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4234. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4235. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4236. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4237. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4238. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4239. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4240. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4241. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4242. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4243. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4244. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4245. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4246. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4247. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4248. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4249. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4250. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4251. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4252. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4253. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4254. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4255. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4256. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4257. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4258. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4259. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4260. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4261. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4262. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4263. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4264. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4265. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4266. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4267. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4268. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4269. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4270. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4271. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4272. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4273. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4274. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4275. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4276. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4277. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4278. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4279. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4280. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4281. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4282. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4283. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4284. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4285. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4286. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4287. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4288. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4289. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4290. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4291. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4292. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4293. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4294. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4295. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4296. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4297. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4298. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4299. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4300. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4301. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4302. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4303. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4304. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4305. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4306. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4307. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4308. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4309. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4310. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4311. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4312. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4313. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4314. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4315. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4316. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4317. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4318. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4319. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4320. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4321. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4322. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4323. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4324. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4325. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4326. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4327. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4328. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4329. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4330. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4331. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4332. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4333. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4334. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4335. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4336. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4337. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4338. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4339. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4340. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4341. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4342. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4343. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4344. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4345. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4346. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4347. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4348. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4349. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4350. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4351. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4352. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4353. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4354. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4355. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4356. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4357. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4358. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4359. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4360. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4361. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4362. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4363. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4364. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4365. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4366. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4367. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4368. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4369. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4370. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4371. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4372. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4373. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4374. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4375. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4376. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4377. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4378. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4379. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4380. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4381. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4382. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4383. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4384. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4385. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4386. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4387. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4388. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4389. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4390. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4391. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4392. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4393. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4394. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4395. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4396. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4397. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4398. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4399. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4400. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4401. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4402. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4403. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4404. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4405. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4406. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4407. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4408. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4409. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4410. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4411. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4412. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4413. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4414. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4415. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4416. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4417. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4418. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4419. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4420. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4421. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4422. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4423. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4424. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4425. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4426. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4427. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4428. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4429. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4430. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4431. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4432. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4433. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4434. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4435. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4436. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4437. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4438. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4439. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4440. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4441. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4442. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4443. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4444. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4445. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4446. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4447. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4448. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4449. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4450. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4451. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4452. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4453. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4454. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4455. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4456. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4457. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4458. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4459. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4460. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4461. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4462. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4463. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4464. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4465. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4466. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4467. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4468. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4469. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4470. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4471. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4472. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4473. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4474. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4475. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4476. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4477. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4478. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4479. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4480. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4481. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4482. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4483. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4484. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4485. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4486. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4487. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4488. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4489. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4490. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4491. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4492. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4493. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4494. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4495. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4496. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4497. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4498. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4499. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4500. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4501. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4502. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4503. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4504. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4505. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4506. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4507. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4508. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4509. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4510. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4511. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4512. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4513. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4514. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4515. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4516. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4517. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4518. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4519. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4520. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4521. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4522. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4523. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4524. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4525. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4526. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4527. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4528. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4529. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4530. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4531. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4532. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4533. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4534. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4535. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4536. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4537. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4538. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4539. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4540. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4541. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4542. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4543. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4544. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4545. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4546. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4547. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4548. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4549. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4550. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4551. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4552. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4553. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4554. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4555. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4556. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4557. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4558. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4559. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4560. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4561. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4562. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4563. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4564. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4565. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4566. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4567. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4568. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4569. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4570. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4571. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4572. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4573. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4574. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4575. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4576. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4577. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4578. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4579. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4580. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4581. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4582. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4583. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4584. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4585. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4586. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4587. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4588. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4589. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4590. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4591. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4592. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4593. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4594. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4595. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4596. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4597. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4598. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4599. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4600. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4601. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4602. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4603. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4604. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4605. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4606. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4607. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4608. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4609. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4610. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4611. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4612. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4613. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4614. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4615. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4616. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4617. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4618. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4619. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4620. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4621. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4622. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4623. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4624. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4625. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4626. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4627. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4628. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4629. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4630. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4631. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4632. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4633. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4634. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4635. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4636. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4637. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4638. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4639. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4640. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4641. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4642. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4643. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4644. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4645. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4646. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4647. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4648. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4649. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4650. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4651. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4652. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4653. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4654. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4655. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4656. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4657. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4658. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4659. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4660. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4661. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4662. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4663. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4664. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4665. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4666. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4667. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4668. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4669. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4670. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4671. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4672. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4673. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4674. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4675. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4676. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4677. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4678. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4679. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4680. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4681. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4682. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4683. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4684. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4685. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4686. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4687. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4688. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4689. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4690. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4691. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4692. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4693. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4694. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4695. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4696. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4697. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4698. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4699. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4700. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4701. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4702. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4703. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4704. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4705. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4706. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4707. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4708. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4709. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4710. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4711. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4712. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4713. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4714. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4715. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4716. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4717. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4718. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4719. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4720. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4721. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4722. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4723. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4724. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4725. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4726. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4727. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4728. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4729. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4730. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4731. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4732. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4733. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4734. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4735. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4736. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4737. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4738. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4739. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4740. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4741. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4742. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4743. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4744. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4745. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4746. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4747. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4748. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4749. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4750. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4751. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4752. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4753. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4754. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4755. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4756. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4757. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4758. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4759. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4760. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4761. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4762. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4763. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4764. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4765. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4766. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4767. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4768. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4769. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4770. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4771. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4772. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4773. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4774. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4775. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4776. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4777. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4778. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4779. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4780. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4781. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4782. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4783. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4784. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4785. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4786. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4787. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4788. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4789. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4790. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4791. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4792. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4793. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4794. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4795. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4796. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4797. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4798. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4799. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4800. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4801. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4802. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4803. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4804. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4805. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4806. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4807. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4808. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4809. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4810. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4811. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4812. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4813. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4814. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4815. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4816. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4817. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4818. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4819. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4820. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4821. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4822. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4823. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4824. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4825. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4826. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4827. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4828. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4829. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4830. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4831. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4832. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4833. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4834. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4835. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4836. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4837. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4838. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4839. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4840. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4841. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4842. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4843. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4844. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4845. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4846. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4847. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4848. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4849. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4850. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4851. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4852. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4853. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4854. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4855. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4856. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4857. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4858. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4859. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4860. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4861. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4862. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4863. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4864. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4865. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4866. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4867. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4868. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4869. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4870. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4871. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4872. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4873. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4874. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4875. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4876. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4877. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4878. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4879. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4880. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4881. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4882. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4883. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4884. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4885. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4886. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4887. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4888. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4889. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4890. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4891. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4892. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4893. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4894. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4895. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4896. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4897. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4898. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4899. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4900. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4901. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4902. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4903. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4904. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4905. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4906. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4907. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4908. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4909. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4910. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4911. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4912. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4913. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4914. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4915. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4916. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4917. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4918. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4919. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4920. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4921. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4922. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4923. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4924. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4925. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4926. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4927. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4928. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4929. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4930. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4931. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4932. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4933. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4934. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4935. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4936. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4937. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4938. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4939. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4940. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4941. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4942. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4943. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4944. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4945. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4946. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4947. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4948. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4949. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4950. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4951. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4952. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4953. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4954. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4955. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4956. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4957. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4958. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  4959. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  4960. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  4961. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  4962. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  4963. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  4964. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  4965. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  4966. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  4967. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  4968. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4969. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4970. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4971. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4972. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4973. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4974. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  4975. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4976. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  4977. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  4978. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4979. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4980. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4981. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4982. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4983. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4984. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4985. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  4986. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4987. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4988. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4989. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4990. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  4991. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  4992. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4993. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4994. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4995. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4996. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  4997. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  4998. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  4999. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  5000. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  5001. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  5002. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  5003. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  5004. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  5005. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  5006. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  5007. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  5008. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  5009. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5010. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5011. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5012. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5013. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5014. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5015. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5016. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5017. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  5018. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5019. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5020. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5021. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5022. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5023. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5024. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5025. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5026. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5027. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5028. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5029. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5030. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5031. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5032. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5033. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5034. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5035. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5036. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5037. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5038. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5039. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  5040. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  5041. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  5042. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  5043. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  5044. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  5045. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  5046. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  5047. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  5048. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  5049. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  5050. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5051. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5052. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5053. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5054. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5055. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5056. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5057. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5058. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  5059. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5060. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5061. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5062. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5063. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5064. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5065. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5066. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5067. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5068. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5069. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5070. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5071. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5072. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5073. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5074. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5075. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5076. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5077. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5078. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5079. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5080. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  5081. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  5082. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  5083. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  5084. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  5085. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  5086. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  5087. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  5088. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  5089. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  5090. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  5091. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5092. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5093. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5094. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5095. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5096. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5097. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5098. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5099. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  5100. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5101. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5102. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5103. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5104. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5105. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5106. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5107. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5108. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5109. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5110. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5111. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5112. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5113. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5114. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5115. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5116. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5117. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5118. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5119. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
  5120. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5121. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  5122. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  5123. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  5124. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  5125. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  5126. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  5127. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  5128. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  5129. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  5130. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  5131. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  5132. HLE: W {PPU[1] Thread (CPUThread)[0x009ce388]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/BUNDLES/SHADERPROGS/Shaders.xom" opened: fd = 32
  5133. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 33
  5134. HLE: W {PPU[1] Thread (CPUThread)[0x009ce300]} sys_fs warning: cellFsClose(fd=32)
  5135. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb0dc]} sys_lwmutex warning: sys_lwmutex_destroy(lwmutex_addr=0x31a90d20)
  5136. HLE: W {PPU[1] Thread (CPUThread)[0x009ce388]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/BUNDLES/SHADERPROGS/Shaders.xom" opened: fd = 34
  5137. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 35
  5138. HLE: W {PPU[1] Thread (CPUThread)[0x009ce300]} sys_fs warning: cellFsClose(fd=34)
  5139. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb0dc]} sys_lwmutex warning: sys_lwmutex_destroy(lwmutex_addr=0x31a90d20)
  5140. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5141. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5142. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
  5143. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5144. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5145. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5146. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5147. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5148. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5149. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5150. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5151. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5152. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5153. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5154. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5155. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5156. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5157. RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
  5158. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5159. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5160. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  5161. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5162. RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
  5163. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5164. RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
  5165. RSX: E {RSXThread} NV4097_SET_POINT_PARAMS_ENABLE: 1
  5166. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5167. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  5168. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5169. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5170. RSX: W {RSXThread} FP not found in buffer!
  5171. RSX: W {RSXThread} VP not found in buffer!
  5172. RSX: ! {RSXThread} Add program (1):
  5173. RSX: ! {RSXThread} *** prog id = 6
  5174. RSX: ! {RSXThread} *** vp id = 5
  5175. RSX: ! {RSXThread} *** fp id = 4
  5176. RSX: ! {RSXThread} *** vp data size = 112
  5177. RSX: ! {RSXThread} *** fp data size = 416
  5178. RSX: ! {RSXThread} *** vp shader =
  5179. #version 330
  5180.  
  5181. uniform mat4 scaleOffsetMat = mat4(1.0);
  5182. vec4 tmp0;
  5183. vec4 dst_reg7 = vec4(0.0);
  5184. vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
  5185. layout (location = 0) in vec4 in_pos;
  5186. layout (location = 8) in vec4 in_tc0;
  5187. uniform vec4 vc[468];
  5188. out vec4 tc0;
  5189.  
  5190. void func0();
  5191.  
  5192. void main()
  5193. {
  5194.         func0();
  5195.         gl_Position = dst_reg0;
  5196.         tc0 = dst_reg7;
  5197.         gl_Position = gl_Position * scaleOffsetMat;
  5198. }
  5199.  
  5200. void func0()
  5201. {
  5202.         tmp0 = (in_pos * vc[260]);
  5203.         tmp0 = (vc[261] + tmp0);
  5204.         dst_reg7.xy = (in_tc0.xyxx * vc[262].xyxx + vc[262].zwzz).xy;
  5205.         dst_reg0.w = vec4(dot(tmp0, vc[259])).w;
  5206.         dst_reg0.z = vec4(dot(tmp0, vc[258])).z;
  5207.         dst_reg0.y = vec4(dot(tmp0, vc[257])).y;
  5208.         dst_reg0.x = vec4(dot(tmp0, vc[256])).x;
  5209. }
  5210.  
  5211. RSX: ! {RSXThread} *** fp shader =
  5212. #version 330
  5213.  
  5214. vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
  5215. vec4 cc0;
  5216. uniform sampler2D tex0;
  5217. in vec4 tc0;
  5218. uniform vec4 fc32 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
  5219. uniform vec4 fc64 = vec4(0.010000, 0.000000, 0.000000, 0.000000);
  5220. uniform vec4 fc288 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
  5221. uniform vec4 fc320 = vec4(0.010000, 0.000000, 0.000000, 0.000000);
  5222. uniform vec4 fc400 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
  5223. layout (location = 0) out vec4 ocol0;
  5224.  
  5225. void main()
  5226. {
  5227.         r0 = texture(tex0, tc0.xy);
  5228.         r0.w = (r0 * fc32.xxxx).w;
  5229.         cc0.x = vec4(lessThan(r0.wwww, fc64.xxxx)).x;
  5230.         if(any(notEqual(cc0.xxxx, vec4(0.0)))) discard;
  5231.         r0.w = r0.w;
  5232.         r0 = texture(tex0, tc0.xy);
  5233.         r0.w = (r0 * fc288.xxxx).w;
  5234.         cc0.x = vec4(lessThan(r0.wwww, fc320.xxxx)).x;
  5235.         if(any(notEqual(cc0.xxxx, vec4(0.0)))) discard;
  5236.         r0.w = r0.w;
  5237.         r0.xyz = (r0 + fc400).xyz;
  5238.         ocol0 = r0;
  5239. }
  5240.  
  5241. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5242. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
  5243. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5244. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5245. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5246. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5247. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5248. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5249. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5250. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5251. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5252. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5253. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5254. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5255. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5256. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5257. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5258. RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
  5259. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5260. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  5261. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5262. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5263. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
  5264. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5265. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5266. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5267. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5268. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5269. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5270. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5271. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5272. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5273. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5274. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5275. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
  5276. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
  5277. RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
  5278. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
  5279. RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
  5280. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5281. RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
  5282. RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
  5283. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5284. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5285. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5286. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5287. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5288. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5289. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  5290. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5291. RSX: W {RSXThread} FP not found in buffer!
  5292. RSX: ! {RSXThread} Add program (2):
  5293. RSX: ! {RSXThread} *** prog id = 8
  5294. RSX: ! {RSXThread} *** vp id = 2
  5295. RSX: ! {RSXThread} *** fp id = 7
  5296. RSX: ! {RSXThread} *** vp data size = 5680
  5297. RSX: ! {RSXThread} *** fp data size = 144
  5298. RSX: ! {RSXThread} *** vp shader =
  5299. #version 330
  5300.  
  5301. uniform mat4 scaleOffsetMat = mat4(1.0);
  5302. vec4 tmp0;
  5303. vec4 tmp3;
  5304. vec4 cc0 = vec4(0.0);
  5305. vec4 tmp5;
  5306. vec4 tmp4;
  5307. vec4 tmp2;
  5308. vec4 tmp1;
  5309. vec4 tmp14;
  5310. vec4 tmp8;
  5311. vec4 tmp6;
  5312. vec4 tmp7;
  5313. vec4 tmp9;
  5314. vec4 tmp10;
  5315. vec4 tmp11;
  5316. vec4 tmp12;
  5317. vec4 tmp13;
  5318. vec4 tmp15;
  5319. vec4 tmp16;
  5320. vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
  5321. vec4 dst_reg1 = vec4(0.0);
  5322. vec4 dst_reg3 = vec4(0.0);
  5323. vec4 dst_reg5 = vec4(0.0);
  5324. vec4 dst_reg6 = vec4(0.0);
  5325. vec4 dst_reg10 = vec4(0.0);
  5326. vec4 dst_reg9 = vec4(0.0);
  5327. vec4 dst_reg8 = vec4(0.0);
  5328. vec4 dst_reg7 = vec4(0.0);
  5329. layout (location = 0) in vec4 in_pos;
  5330. layout (location = 2) in vec4 in_normal;
  5331. layout (location = 3) in vec4 in_diff_color;
  5332. layout (location = 8) in vec4 in_tc0;
  5333. layout (location = 9) in vec4 in_tc1;
  5334. layout (location = 10) in vec4 in_tc2;
  5335. layout (location = 11) in vec4 in_tc3;
  5336. uniform vec4 vc[468];
  5337. ivec4 a0 = ivec4(0);
  5338. out vec4 diff_color;
  5339. out vec4 front_diff_color;
  5340. out vec4 fogc;
  5341. out vec4 tc0;
  5342. out vec4 tc1;
  5343. out vec4 tc2;
  5344. out vec4 tc3;
  5345. out vec4 tc9;
  5346.  
  5347. void func0();
  5348.  
  5349. void main()
  5350. {
  5351.         func0();
  5352.         gl_Position = dst_reg0;
  5353.         diff_color = dst_reg1;
  5354.         front_diff_color = dst_reg3;
  5355.         fogc = vec4(dst_reg5.x);
  5356.         gl_ClipDistance[0] = dst_reg5.y;
  5357.         gl_ClipDistance[1] = dst_reg5.z;
  5358.         gl_ClipDistance[2] = dst_reg5.w;
  5359.         gl_PointSize = dst_reg6.x;
  5360.         gl_ClipDistance[3] = dst_reg6.y;
  5361.         gl_ClipDistance[4] = dst_reg6.z;
  5362.         gl_ClipDistance[5] = dst_reg6.w;
  5363.         tc0 = dst_reg7;
  5364.         tc1 = dst_reg8;
  5365.         tc2 = dst_reg9;
  5366.         tc3 = dst_reg10;
  5367.         tc9 = dst_reg6;
  5368.         gl_Position = gl_Position * scaleOffsetMat;
  5369. }
  5370.  
  5371. void func0()
  5372. {
  5373.         tmp0.w = vec4(dot(in_pos, vc[263])).w;
  5374.         tmp0.z = vec4(dot(in_pos, vc[262])).z;
  5375.         tmp0.y = vec4(dot(in_pos, vc[261])).y;
  5376.         tmp0.x = vec4(dot(in_pos, vc[260])).x;
  5377.         tmp3.w = vec4(dot(in_pos, vc[259])).w;
  5378.         tmp3.y = vec4(dot(in_pos, vc[257])).y;
  5379.         tmp3.x = vec4(dot(in_pos, vc[256])).x;
  5380.         cc0.xy = vc[467].wxww.xy;
  5381.         tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
  5382.         tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
  5383.         tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
  5384.         tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
  5385.         tmp2 = clamp(in_diff_color, 0.0, 1.0);
  5386.         tmp1 = tmp2;
  5387.         tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
  5388.         tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
  5389.         tmp3.z = tmp5.yyyy.z;
  5390.         tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
  5391.         tmp14.w = abs(tmp5.xxxx).w;
  5392.         tmp14.xyz = tmp4.xyzx.xyz;
  5393.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
  5394.         if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  5395.         {
  5396.                 tmp1.xyz = vc[463].xxxx.xyz;
  5397.                 tmp1.w = vc[463].xxxx.w;
  5398.                 tmp4 = in_diff_color;
  5399.                 cc0.x = vc[467].zzzz.x;
  5400.                 tmp5.xyz = in_diff_color.xyzx.xyz;
  5401.                 tmp2.x = vc[462].xxxx.x;
  5402.                 cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
  5403.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
  5404.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
  5405.                 if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  5406.                 {
  5407.                         do
  5408.                         {
  5409.                                 tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
  5410.                                 a0.x = ivec4(tmp2.xxxx).x;
  5411.                                 tmp8.z = vc[405].xxxx.z;
  5412.                                 tmp2.xyz = vc[463].xxxx.xyz;
  5413.                                 tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  5414.                                 tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
  5415.                                 tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
  5416.                                 tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
  5417.                                 tmp2.w = vc[463].xxxx.w;
  5418.                                 cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  5419.                                 cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
  5420.                                 cc0.x = vc[411 + a0.x].xxxx.x;
  5421.                                 tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
  5422.                                 tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  5423.                                 tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
  5424.                                 tmp6.w = -tmp6.wwww.w;
  5425.                                 if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
  5426.                                 tmp2.w = tmp6.wwww.w;
  5427.                                 tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
  5428.                                 tmp6.w = log2(tmp6.wwww).w;
  5429.                                 tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
  5430.                                 cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
  5431.                                 cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
  5432.                                 tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  5433.                                 tmp5.w = (1.0 / tmp5.wwww).w;
  5434.                                 tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
  5435.                                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  5436.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
  5437.                                 cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
  5438.                                 tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
  5439.                                 tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
  5440.                                 tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
  5441.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
  5442.                                 tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
  5443.                                 tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
  5444.                                 tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
  5445.                                 if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
  5446.                                 tmp5.w = (1.0 / tmp2.xxxx).w;
  5447.                                 tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
  5448.                                 tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
  5449.                                 tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
  5450.                                 tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
  5451.                                 tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
  5452.                                 tmp2.w = (tmp2.wwww * tmp5.wwww).w;
  5453.                                 tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
  5454.                         } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  5455.                 }
  5456.                 cc0.x = vc[467].yyyy.x;
  5457.                 tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  5458.                 tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
  5459.                 tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
  5460.                 tmp1.w = tmp4.wwww.w;
  5461.                 tmp2 = clamp(tmp1, 0.0, 1.0);
  5462.                 tmp1 = tmp2;
  5463.                 if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  5464.                 {
  5465.                         tmp2.x = vc[462].xxxx.x;
  5466.                         cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
  5467.                         tmp2.xyz = vc[463].xxxx.xyz;
  5468.                         if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  5469.                         {
  5470.                         tmp2.w = vc[463].xxxx.w;
  5471.                                 do
  5472.                                 {
  5473.                                         tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
  5474.                                         a0.x = ivec4(tmp5.wwww).x;
  5475.                                         tmp9.z = vc[405].xxxx.z;
  5476.                                         tmp6.xyz = vc[463].xxxx.xyz;
  5477.                                         tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  5478.                                         tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
  5479.                                         tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
  5480.                                         tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  5481.                                         tmp5.w = vc[463].xxxx.w;
  5482.                                         cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
  5483.                                         cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
  5484.                                         cc0.x = vc[411 + a0.x].xxxx.x;
  5485.                                         tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
  5486.                                         tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  5487.                                         tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
  5488.                                         tmp8.y = -tmp7.wwww.y;
  5489.                                         if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
  5490.                                         tmp7.w = log2(tmp8.yyyy).w;
  5491.                                         tmp5.w = tmp8.yyyy.w;
  5492.                                         tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
  5493.                                         tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
  5494.                                         cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
  5495.                                         cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
  5496.                                         tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
  5497.                                         tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
  5498.                                         tmp6.w = (1.0 / tmp6.wwww).w;
  5499.                                         tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
  5500.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
  5501.                                         cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
  5502.                                         tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
  5503.                                         tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
  5504.                                         tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
  5505.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
  5506.                                         tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
  5507.                                         tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
  5508.                                         tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
  5509.                                         if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
  5510.                                         tmp6.w = (1.0 / tmp6.xxxx).w;
  5511.                                         tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
  5512.                                         tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
  5513.                                         tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
  5514.                                         tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
  5515.                                         tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
  5516.                                         tmp5.w = (tmp5.wwww * tmp6.wwww).w;
  5517.                                         tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
  5518.                                 } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  5519.                         }
  5520.                         tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
  5521.                         tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  5522.                         tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
  5523.                         tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
  5524.                 }
  5525.         }
  5526.         tmp4.x = vc[463].xxxx.x;
  5527.         tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
  5528.         tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
  5529.         tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
  5530.         cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
  5531.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  5532.         {
  5533.         tmp4 = in_tc0;
  5534.                 tmp9.x = vc[400].xxxx.x;
  5535.                 tmp7.zw = vc[463].xxxz.zw;
  5536.                 tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
  5537.                 tmp5 = (tmp3.yyyy * vc[268]);
  5538.                 tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
  5539.                 tmp7.xy = vc[400].yzyy.xy;
  5540.                 tmp4 = in_tc0;
  5541.                 tmp6 = (in_pos.yyyy * vc[268]);
  5542.                 tmp8.zw = vc[463].zzzw.zw;
  5543.                 cc0 = vec4(equal(vc[401], tmp8.zzzz));
  5544.                 tmp6 = (in_pos.xxxx * vc[267] + tmp6);
  5545.                 tmp6 = (in_pos.zzzz * vc[269] + tmp6);
  5546.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
  5547.                 cc0 = vec4(equal(vc[401], tmp7.xxxx));
  5548.                 tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
  5549.                 tmp5 = (tmp3.xxxx * vc[267] + tmp5);
  5550.                 tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
  5551.                 tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
  5552.                 tmp5 = (tmp3.zzzz * vc[269] + tmp5);
  5553.                 tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
  5554.                 tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
  5555.                 tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
  5556.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
  5557.                 tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  5558.                 cc0 = vec4(equal(vc[401], tmp7.yyyy));
  5559.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  5560.                 tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
  5561.                 tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  5562.                 tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  5563.                 tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
  5564.                 tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
  5565.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  5566.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
  5567.                 cc0 = vec4(equal(vc[401], tmp9.xxxx));
  5568.                 tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
  5569.                 tmp5.w = vc[463].zzzz.w;
  5570.                 tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
  5571.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  5572.                 cc0 = vec4(equal(vc[401], tmp8.wwww));
  5573.                 tmp5.xyz = tmp14.xyzx.xyz;
  5574.                 tmp5.w = vc[463].zzzz.w;
  5575.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  5576.         }
  5577.         tmp5.x = vc[463].xxxx.x;
  5578.         tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
  5579.         tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
  5580.         tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
  5581.         cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
  5582.         tmp5 = tmp4;
  5583.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  5584.         {
  5585.         tmp6 = in_tc1;
  5586.                 tmp9.zw = vc[463].xxxz.zw;
  5587.                 tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  5588.                 tmp7 = (tmp3.yyyy * vc[276]);
  5589.                 tmp10.xyz = vc[400].xyzx.xyz;
  5590.                 tmp6 = in_tc1;
  5591.                 tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  5592.                 tmp8 = (in_pos.yyyy * vc[276]);
  5593.                 tmp11.zw = vc[463].zzzw.zw;
  5594.                 cc0 = vec4(equal(vc[399], tmp11.zzzz));
  5595.                 tmp8 = (in_pos.xxxx * vc[275] + tmp8);
  5596.                 tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
  5597.                 tmp8 = (in_pos.zzzz * vc[277] + tmp8);
  5598.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
  5599.                 cc0 = vec4(equal(vc[399], tmp10.yyyy));
  5600.                 tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
  5601.                 tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
  5602.                 tmp7 = (tmp3.xxxx * vc[275] + tmp7);
  5603.                 tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
  5604.                 tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
  5605.                 tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
  5606.                 tmp7 = (tmp3.zzzz * vc[277] + tmp7);
  5607.                 tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
  5608.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
  5609.                 tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  5610.                 cc0 = vec4(equal(vc[399], tmp10.zzzz));
  5611.                 tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
  5612.                 tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
  5613.                 tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  5614.                 tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
  5615.                 tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
  5616.                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  5617.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
  5618.                 cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
  5619.                 cc0 = vec4(equal(vc[399], tmp10.xxxx));
  5620.                 tmp7.w = vc[463].zzzz.w;
  5621.                 tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
  5622.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  5623.                 cc0 = vec4(equal(vc[399], tmp11.wwww));
  5624.                 tmp7.xyz = tmp14.xyzx.xyz;
  5625.                 tmp7.w = vc[463].zzzz.w;
  5626.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  5627.         }
  5628.         tmp7.x = vc[463].xxxx.x;
  5629.         tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
  5630.         tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
  5631.         tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
  5632.         cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
  5633.         tmp7 = tmp6;
  5634.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  5635.         {
  5636.         tmp8 = in_tc2;
  5637.                 tmp11.zw = vc[463].xxxz.zw;
  5638.                 tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  5639.                 tmp9 = (tmp3.yyyy * vc[284]);
  5640.                 tmp12.xyz = vc[400].xyzx.xyz;
  5641.                 tmp8 = in_tc2;
  5642.                 tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  5643.                 tmp10 = (in_pos.yyyy * vc[284]);
  5644.                 tmp13.zw = vc[463].zzzw.zw;
  5645.                 cc0 = vec4(equal(vc[398], tmp13.zzzz));
  5646.                 tmp10 = (in_pos.xxxx * vc[283] + tmp10);
  5647.                 tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
  5648.                 tmp10 = (in_pos.zzzz * vc[285] + tmp10);
  5649.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
  5650.                 cc0 = vec4(equal(vc[398], tmp12.yyyy));
  5651.                 tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
  5652.                 tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
  5653.                 tmp9 = (tmp3.xxxx * vc[283] + tmp9);
  5654.                 tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
  5655.                 tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
  5656.                 tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
  5657.                 tmp9 = (tmp3.zzzz * vc[285] + tmp9);
  5658.                 tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
  5659.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
  5660.                 tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
  5661.                 cc0 = vec4(equal(vc[398], tmp12.zzzz));
  5662.                 tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
  5663.                 tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
  5664.                 tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  5665.                 tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
  5666.                 tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
  5667.                 tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
  5668.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
  5669.                 cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
  5670.                 cc0 = vec4(equal(vc[398], tmp12.xxxx));
  5671.                 tmp9.w = vc[463].zzzz.w;
  5672.                 tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
  5673.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  5674.                 cc0 = vec4(equal(vc[398], tmp13.wwww));
  5675.                 tmp9.xyz = tmp14.xyzx.xyz;
  5676.                 tmp9.w = vc[463].zzzz.w;
  5677.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  5678.         }
  5679.         tmp9.x = vc[463].xxxx.x;
  5680.         tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
  5681.         tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
  5682.         tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
  5683.         cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
  5684.         tmp9 = tmp8;
  5685.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  5686.         {
  5687.         tmp10 = in_tc3;
  5688.                 tmp13.zw = vc[463].xxxz.zw;
  5689.                 tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  5690.                 tmp11 = (tmp3.yyyy * vc[292]);
  5691.                 tmp15.xyz = vc[400].xyzx.xyz;
  5692.                 tmp10 = in_tc3;
  5693.                 tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  5694.                 tmp12 = (in_pos.yyyy * vc[292]);
  5695.                 tmp16.zw = vc[463].zzzw.zw;
  5696.                 cc0 = vec4(equal(vc[397], tmp16.zzzz));
  5697.                 tmp12 = (in_pos.xxxx * vc[291] + tmp12);
  5698.                 tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
  5699.                 tmp12 = (in_pos.zzzz * vc[293] + tmp12);
  5700.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
  5701.                 cc0 = vec4(equal(vc[397], tmp15.yyyy));
  5702.                 tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
  5703.                 tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
  5704.                 tmp11 = (tmp3.xxxx * vc[291] + tmp11);
  5705.                 tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
  5706.                 tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
  5707.                 tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
  5708.                 tmp11 = (tmp3.zzzz * vc[293] + tmp11);
  5709.                 tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
  5710.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
  5711.                 tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
  5712.                 cc0 = vec4(equal(vc[397], tmp15.zzzz));
  5713.                 tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
  5714.                 tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
  5715.                 tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  5716.                 tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
  5717.                 tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
  5718.                 tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  5719.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
  5720.                 cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
  5721.                 cc0 = vec4(equal(vc[397], tmp15.xxxx));
  5722.                 tmp11.w = vc[463].zzzz.w;
  5723.                 tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
  5724.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  5725.                 cc0 = vec4(equal(vc[397], tmp16.wwww));
  5726.                 tmp11.xyz = tmp14.xyzx.xyz;
  5727.                 tmp11.w = vc[463].zzzz.w;
  5728.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  5729.         }
  5730.         dst_reg0 = tmp0;
  5731.         dst_reg1 = tmp1;
  5732.         dst_reg3 = tmp2;
  5733.         dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
  5734.         dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
  5735.         dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
  5736.         dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
  5737.         dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
  5738.         dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
  5739.         dst_reg5.x = tmp14.wwww.x;
  5740.         tmp0.w = vec4(dot(tmp10, vc[298])).w;
  5741.         tmp0.z = vec4(dot(tmp10, vc[297])).z;
  5742.         tmp0.y = vec4(dot(tmp10, vc[296])).y;
  5743.         tmp0.x = vec4(dot(tmp10, vc[295])).x;
  5744.         dst_reg10 = tmp10;
  5745.         dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
  5746.         dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
  5747.         dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
  5748.         dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
  5749.         dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
  5750.         dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
  5751.         dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
  5752.         cc0.x = vc[396].xxxx.x;
  5753.         dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
  5754.         dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
  5755.         dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
  5756.         dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
  5757.         dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
  5758.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
  5759.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
  5760.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
  5761.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
  5762. }
  5763.  
  5764. RSX: ! {RSXThread} *** fp shader =
  5765. #version 330
  5766.  
  5767. vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
  5768. vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
  5769. vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
  5770. vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
  5771. in vec4 diff_color;
  5772. in vec4 tc0;
  5773. uniform sampler2D tex0;
  5774. layout (location = 0) out vec4 ocol0;
  5775. layout (location = 2) out vec4 ocol2;
  5776. layout (location = 3) out vec4 ocol3;
  5777.  
  5778. void main()
  5779. {
  5780.         h2 = diff_color;
  5781.         r0 = h2;
  5782.         r2 = h2;
  5783.         r3 = h2;
  5784.         r0 = texture(tex0, tc0.xy);
  5785.         ocol0 = r0;
  5786.         ocol2 = r2;
  5787.         ocol3 = r3;
  5788. }
  5789.  
  5790. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5791. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5792. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5793. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5794. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5795. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5796. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5797. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  5798. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5799. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5800. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5801. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5802. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5803. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  5804. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5805. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5806. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5807. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5808. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  5809. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  5810. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  5811. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  5812. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  5813. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  5814. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  5815. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  5816. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  5817. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  5818. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  5819. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  5820. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  5821. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5822. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5823. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5824. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5825. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  5826. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5827. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  5828. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5829. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  5830. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  5831. RSX: ! {RSXThread} Add program (3):
  5832. RSX: ! {RSXThread} *** prog id = 9
  5833. RSX: ! {RSXThread} *** vp id = 2
  5834. RSX: ! {RSXThread} *** fp id = 7
  5835. RSX: ! {RSXThread} *** vp data size = 5680
  5836. RSX: ! {RSXThread} *** fp data size = 144
  5837. RSX: ! {RSXThread} *** vp shader =
  5838. #version 330
  5839.  
  5840. uniform mat4 scaleOffsetMat = mat4(1.0);
  5841. vec4 tmp0;
  5842. vec4 tmp3;
  5843. vec4 cc0 = vec4(0.0);
  5844. vec4 tmp5;
  5845. vec4 tmp4;
  5846. vec4 tmp2;
  5847. vec4 tmp1;
  5848. vec4 tmp14;
  5849. vec4 tmp8;
  5850. vec4 tmp6;
  5851. vec4 tmp7;
  5852. vec4 tmp9;
  5853. vec4 tmp10;
  5854. vec4 tmp11;
  5855. vec4 tmp12;
  5856. vec4 tmp13;
  5857. vec4 tmp15;
  5858. vec4 tmp16;
  5859. vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
  5860. vec4 dst_reg1 = vec4(0.0);
  5861. vec4 dst_reg3 = vec4(0.0);
  5862. vec4 dst_reg5 = vec4(0.0);
  5863. vec4 dst_reg6 = vec4(0.0);
  5864. vec4 dst_reg10 = vec4(0.0);
  5865. vec4 dst_reg9 = vec4(0.0);
  5866. vec4 dst_reg8 = vec4(0.0);
  5867. vec4 dst_reg7 = vec4(0.0);
  5868. layout (location = 0) in vec4 in_pos;
  5869. layout (location = 2) in vec4 in_normal;
  5870. layout (location = 3) in vec4 in_diff_color;
  5871. layout (location = 8) in vec4 in_tc0;
  5872. layout (location = 9) in vec4 in_tc1;
  5873. layout (location = 10) in vec4 in_tc2;
  5874. layout (location = 11) in vec4 in_tc3;
  5875. uniform vec4 vc[468];
  5876. ivec4 a0 = ivec4(0);
  5877. out vec4 diff_color;
  5878. out vec4 front_diff_color;
  5879. out vec4 fogc;
  5880. out vec4 tc0;
  5881. out vec4 tc1;
  5882. out vec4 tc2;
  5883. out vec4 tc3;
  5884. out vec4 tc9;
  5885.  
  5886. void func0();
  5887.  
  5888. void main()
  5889. {
  5890.         func0();
  5891.         gl_Position = dst_reg0;
  5892.         diff_color = dst_reg1;
  5893.         front_diff_color = dst_reg3;
  5894.         fogc = vec4(dst_reg5.x);
  5895.         gl_ClipDistance[0] = dst_reg5.y;
  5896.         gl_ClipDistance[1] = dst_reg5.z;
  5897.         gl_ClipDistance[2] = dst_reg5.w;
  5898.         gl_PointSize = dst_reg6.x;
  5899.         gl_ClipDistance[3] = dst_reg6.y;
  5900.         gl_ClipDistance[4] = dst_reg6.z;
  5901.         gl_ClipDistance[5] = dst_reg6.w;
  5902.         tc0 = dst_reg7;
  5903.         tc1 = dst_reg8;
  5904.         tc2 = dst_reg9;
  5905.         tc3 = dst_reg10;
  5906.         tc9 = dst_reg6;
  5907.         gl_Position = gl_Position * scaleOffsetMat;
  5908. }
  5909.  
  5910. void func0()
  5911. {
  5912.         tmp0.w = vec4(dot(in_pos, vc[263])).w;
  5913.         tmp0.z = vec4(dot(in_pos, vc[262])).z;
  5914.         tmp0.y = vec4(dot(in_pos, vc[261])).y;
  5915.         tmp0.x = vec4(dot(in_pos, vc[260])).x;
  5916.         tmp3.w = vec4(dot(in_pos, vc[259])).w;
  5917.         tmp3.y = vec4(dot(in_pos, vc[257])).y;
  5918.         tmp3.x = vec4(dot(in_pos, vc[256])).x;
  5919.         cc0.xy = vc[467].wxww.xy;
  5920.         tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
  5921.         tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
  5922.         tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
  5923.         tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
  5924.         tmp2 = clamp(in_diff_color, 0.0, 1.0);
  5925.         tmp1 = tmp2;
  5926.         tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
  5927.         tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
  5928.         tmp3.z = tmp5.yyyy.z;
  5929.         tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
  5930.         tmp14.w = abs(tmp5.xxxx).w;
  5931.         tmp14.xyz = tmp4.xyzx.xyz;
  5932.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
  5933.         if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  5934.         {
  5935.                 tmp1.xyz = vc[463].xxxx.xyz;
  5936.                 tmp1.w = vc[463].xxxx.w;
  5937.                 tmp4 = in_diff_color;
  5938.                 cc0.x = vc[467].zzzz.x;
  5939.                 tmp5.xyz = in_diff_color.xyzx.xyz;
  5940.                 tmp2.x = vc[462].xxxx.x;
  5941.                 cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
  5942.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
  5943.                 if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
  5944.                 if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
  5945.                 {
  5946.                         do
  5947.                         {
  5948.                                 tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
  5949.                                 a0.x = ivec4(tmp2.xxxx).x;
  5950.                                 tmp8.z = vc[405].xxxx.z;
  5951.                                 tmp2.xyz = vc[463].xxxx.xyz;
  5952.                                 tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  5953.                                 tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
  5954.                                 tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
  5955.                                 tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
  5956.                                 tmp2.w = vc[463].xxxx.w;
  5957.                                 cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  5958.                                 cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
  5959.                                 cc0.x = vc[411 + a0.x].xxxx.x;
  5960.                                 tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
  5961.                                 tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  5962.                                 tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
  5963.                                 tmp6.w = -tmp6.wwww.w;
  5964.                                 if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
  5965.                                 tmp2.w = tmp6.wwww.w;
  5966.                                 tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
  5967.                                 tmp6.w = log2(tmp6.wwww).w;
  5968.                                 tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
  5969.                                 cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
  5970.                                 cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
  5971.                                 tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  5972.                                 tmp5.w = (1.0 / tmp5.wwww).w;
  5973.                                 tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
  5974.                                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  5975.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
  5976.                                 cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
  5977.                                 tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
  5978.                                 tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
  5979.                                 tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
  5980.                                 if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
  5981.                                 tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
  5982.                                 tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
  5983.                                 tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
  5984.                                 if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
  5985.                                 tmp5.w = (1.0 / tmp2.xxxx).w;
  5986.                                 tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
  5987.                                 tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
  5988.                                 tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
  5989.                                 tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
  5990.                                 tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
  5991.                                 tmp2.w = (tmp2.wwww * tmp5.wwww).w;
  5992.                                 tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
  5993.                         } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  5994.                 }
  5995.                 cc0.x = vc[467].yyyy.x;
  5996.                 tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  5997.                 tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
  5998.                 tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
  5999.                 tmp1.w = tmp4.wwww.w;
  6000.                 tmp2 = clamp(tmp1, 0.0, 1.0);
  6001.                 tmp1 = tmp2;
  6002.                 if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  6003.                 {
  6004.                         tmp2.x = vc[462].xxxx.x;
  6005.                         cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
  6006.                         tmp2.xyz = vc[463].xxxx.xyz;
  6007.                         if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
  6008.                         {
  6009.                         tmp2.w = vc[463].xxxx.w;
  6010.                                 do
  6011.                                 {
  6012.                                         tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
  6013.                                         a0.x = ivec4(tmp5.wwww).x;
  6014.                                         tmp9.z = vc[405].xxxx.z;
  6015.                                         tmp6.xyz = vc[463].xxxx.xyz;
  6016.                                         tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
  6017.                                         tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
  6018.                                         tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
  6019.                                         tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  6020.                                         tmp5.w = vc[463].xxxx.w;
  6021.                                         cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
  6022.                                         cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
  6023.                                         cc0.x = vc[411 + a0.x].xxxx.x;
  6024.                                         tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
  6025.                                         tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
  6026.                                         tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
  6027.                                         tmp8.y = -tmp7.wwww.y;
  6028.                                         if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
  6029.                                         tmp7.w = log2(tmp8.yyyy).w;
  6030.                                         tmp5.w = tmp8.yyyy.w;
  6031.                                         tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
  6032.                                         tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
  6033.                                         cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
  6034.                                         cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
  6035.                                         tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
  6036.                                         tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
  6037.                                         tmp6.w = (1.0 / tmp6.wwww).w;
  6038.                                         tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
  6039.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
  6040.                                         cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
  6041.                                         tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
  6042.                                         tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
  6043.                                         tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
  6044.                                         if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
  6045.                                         tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
  6046.                                         tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
  6047.                                         tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
  6048.                                         if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
  6049.                                         tmp6.w = (1.0 / tmp6.xxxx).w;
  6050.                                         tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
  6051.                                         tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
  6052.                                         tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
  6053.                                         tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
  6054.                                         tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
  6055.                                         tmp5.w = (tmp5.wwww * tmp6.wwww).w;
  6056.                                         tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
  6057.                                 } while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
  6058.                         }
  6059.                         tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
  6060.                         tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
  6061.                         tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
  6062.                         tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
  6063.                 }
  6064.         }
  6065.         tmp4.x = vc[463].xxxx.x;
  6066.         tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
  6067.         tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
  6068.         tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
  6069.         cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
  6070.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  6071.         {
  6072.         tmp4 = in_tc0;
  6073.                 tmp9.x = vc[400].xxxx.x;
  6074.                 tmp7.zw = vc[463].xxxz.zw;
  6075.                 tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
  6076.                 tmp5 = (tmp3.yyyy * vc[268]);
  6077.                 tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
  6078.                 tmp7.xy = vc[400].yzyy.xy;
  6079.                 tmp4 = in_tc0;
  6080.                 tmp6 = (in_pos.yyyy * vc[268]);
  6081.                 tmp8.zw = vc[463].zzzw.zw;
  6082.                 cc0 = vec4(equal(vc[401], tmp8.zzzz));
  6083.                 tmp6 = (in_pos.xxxx * vc[267] + tmp6);
  6084.                 tmp6 = (in_pos.zzzz * vc[269] + tmp6);
  6085.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
  6086.                 cc0 = vec4(equal(vc[401], tmp7.xxxx));
  6087.                 tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
  6088.                 tmp5 = (tmp3.xxxx * vc[267] + tmp5);
  6089.                 tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
  6090.                 tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
  6091.                 tmp5 = (tmp3.zzzz * vc[269] + tmp5);
  6092.                 tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
  6093.                 tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
  6094.                 tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
  6095.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
  6096.                 tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
  6097.                 cc0 = vec4(equal(vc[401], tmp7.yyyy));
  6098.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  6099.                 tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
  6100.                 tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
  6101.                 tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  6102.                 tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
  6103.                 tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
  6104.                 tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
  6105.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
  6106.                 cc0 = vec4(equal(vc[401], tmp9.xxxx));
  6107.                 tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
  6108.                 tmp5.w = vc[463].zzzz.w;
  6109.                 tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
  6110.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  6111.                 cc0 = vec4(equal(vc[401], tmp8.wwww));
  6112.                 tmp5.xyz = tmp14.xyzx.xyz;
  6113.                 tmp5.w = vc[463].zzzz.w;
  6114.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
  6115.         }
  6116.         tmp5.x = vc[463].xxxx.x;
  6117.         tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
  6118.         tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
  6119.         tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
  6120.         cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
  6121.         tmp5 = tmp4;
  6122.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  6123.         {
  6124.         tmp6 = in_tc1;
  6125.                 tmp9.zw = vc[463].xxxz.zw;
  6126.                 tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  6127.                 tmp7 = (tmp3.yyyy * vc[276]);
  6128.                 tmp10.xyz = vc[400].xyzx.xyz;
  6129.                 tmp6 = in_tc1;
  6130.                 tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  6131.                 tmp8 = (in_pos.yyyy * vc[276]);
  6132.                 tmp11.zw = vc[463].zzzw.zw;
  6133.                 cc0 = vec4(equal(vc[399], tmp11.zzzz));
  6134.                 tmp8 = (in_pos.xxxx * vc[275] + tmp8);
  6135.                 tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
  6136.                 tmp8 = (in_pos.zzzz * vc[277] + tmp8);
  6137.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
  6138.                 cc0 = vec4(equal(vc[399], tmp10.yyyy));
  6139.                 tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
  6140.                 tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
  6141.                 tmp7 = (tmp3.xxxx * vc[275] + tmp7);
  6142.                 tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
  6143.                 tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
  6144.                 tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
  6145.                 tmp7 = (tmp3.zzzz * vc[277] + tmp7);
  6146.                 tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
  6147.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
  6148.                 tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  6149.                 cc0 = vec4(equal(vc[399], tmp10.zzzz));
  6150.                 tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
  6151.                 tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
  6152.                 tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  6153.                 tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
  6154.                 tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
  6155.                 tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
  6156.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
  6157.                 cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
  6158.                 cc0 = vec4(equal(vc[399], tmp10.xxxx));
  6159.                 tmp7.w = vc[463].zzzz.w;
  6160.                 tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
  6161.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  6162.                 cc0 = vec4(equal(vc[399], tmp11.wwww));
  6163.                 tmp7.xyz = tmp14.xyzx.xyz;
  6164.                 tmp7.w = vc[463].zzzz.w;
  6165.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
  6166.         }
  6167.         tmp7.x = vc[463].xxxx.x;
  6168.         tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
  6169.         tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
  6170.         tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
  6171.         cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
  6172.         tmp7 = tmp6;
  6173.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  6174.         {
  6175.         tmp8 = in_tc2;
  6176.                 tmp11.zw = vc[463].xxxz.zw;
  6177.                 tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  6178.                 tmp9 = (tmp3.yyyy * vc[284]);
  6179.                 tmp12.xyz = vc[400].xyzx.xyz;
  6180.                 tmp8 = in_tc2;
  6181.                 tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  6182.                 tmp10 = (in_pos.yyyy * vc[284]);
  6183.                 tmp13.zw = vc[463].zzzw.zw;
  6184.                 cc0 = vec4(equal(vc[398], tmp13.zzzz));
  6185.                 tmp10 = (in_pos.xxxx * vc[283] + tmp10);
  6186.                 tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
  6187.                 tmp10 = (in_pos.zzzz * vc[285] + tmp10);
  6188.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
  6189.                 cc0 = vec4(equal(vc[398], tmp12.yyyy));
  6190.                 tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
  6191.                 tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
  6192.                 tmp9 = (tmp3.xxxx * vc[283] + tmp9);
  6193.                 tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
  6194.                 tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
  6195.                 tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
  6196.                 tmp9 = (tmp3.zzzz * vc[285] + tmp9);
  6197.                 tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
  6198.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
  6199.                 tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
  6200.                 cc0 = vec4(equal(vc[398], tmp12.zzzz));
  6201.                 tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
  6202.                 tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
  6203.                 tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  6204.                 tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
  6205.                 tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
  6206.                 tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
  6207.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
  6208.                 cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
  6209.                 cc0 = vec4(equal(vc[398], tmp12.xxxx));
  6210.                 tmp9.w = vc[463].zzzz.w;
  6211.                 tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
  6212.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  6213.                 cc0 = vec4(equal(vc[398], tmp13.wwww));
  6214.                 tmp9.xyz = tmp14.xyzx.xyz;
  6215.                 tmp9.w = vc[463].zzzz.w;
  6216.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
  6217.         }
  6218.         tmp9.x = vc[463].xxxx.x;
  6219.         tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
  6220.         tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
  6221.         tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
  6222.         cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
  6223.         tmp9 = tmp8;
  6224.         if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
  6225.         {
  6226.         tmp10 = in_tc3;
  6227.                 tmp13.zw = vc[463].xxxz.zw;
  6228.                 tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
  6229.                 tmp11 = (tmp3.yyyy * vc[292]);
  6230.                 tmp15.xyz = vc[400].xyzx.xyz;
  6231.                 tmp10 = in_tc3;
  6232.                 tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
  6233.                 tmp12 = (in_pos.yyyy * vc[292]);
  6234.                 tmp16.zw = vc[463].zzzw.zw;
  6235.                 cc0 = vec4(equal(vc[397], tmp16.zzzz));
  6236.                 tmp12 = (in_pos.xxxx * vc[291] + tmp12);
  6237.                 tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
  6238.                 tmp12 = (in_pos.zzzz * vc[293] + tmp12);
  6239.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
  6240.                 cc0 = vec4(equal(vc[397], tmp15.yyyy));
  6241.                 tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
  6242.                 tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
  6243.                 tmp11 = (tmp3.xxxx * vc[291] + tmp11);
  6244.                 tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
  6245.                 tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
  6246.                 tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
  6247.                 tmp11 = (tmp3.zzzz * vc[293] + tmp11);
  6248.                 tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
  6249.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
  6250.                 tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
  6251.                 cc0 = vec4(equal(vc[397], tmp15.zzzz));
  6252.                 tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
  6253.                 tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
  6254.                 tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
  6255.                 tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
  6256.                 tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
  6257.                 tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
  6258.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
  6259.                 cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
  6260.                 cc0 = vec4(equal(vc[397], tmp15.xxxx));
  6261.                 tmp11.w = vc[463].zzzz.w;
  6262.                 tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
  6263.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  6264.                 cc0 = vec4(equal(vc[397], tmp16.wwww));
  6265.                 tmp11.xyz = tmp14.xyzx.xyz;
  6266.                 tmp11.w = vc[463].zzzz.w;
  6267.                 if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
  6268.         }
  6269.         dst_reg0 = tmp0;
  6270.         dst_reg1 = tmp1;
  6271.         dst_reg3 = tmp2;
  6272.         dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
  6273.         dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
  6274.         dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
  6275.         dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
  6276.         dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
  6277.         dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
  6278.         dst_reg5.x = tmp14.wwww.x;
  6279.         tmp0.w = vec4(dot(tmp10, vc[298])).w;
  6280.         tmp0.z = vec4(dot(tmp10, vc[297])).z;
  6281.         tmp0.y = vec4(dot(tmp10, vc[296])).y;
  6282.         tmp0.x = vec4(dot(tmp10, vc[295])).x;
  6283.         dst_reg10 = tmp10;
  6284.         dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
  6285.         dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
  6286.         dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
  6287.         dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
  6288.         dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
  6289.         dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
  6290.         dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
  6291.         cc0.x = vc[396].xxxx.x;
  6292.         dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
  6293.         dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
  6294.         dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
  6295.         dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
  6296.         dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
  6297.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
  6298.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
  6299.         if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
  6300.         if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
  6301. }
  6302.  
  6303. RSX: ! {RSXThread} *** fp shader =
  6304. #version 330
  6305.  
  6306. vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
  6307. vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
  6308. vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
  6309. vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
  6310. in vec4 diff_color;
  6311. in vec4 tc0;
  6312. uniform sampler2D tex0;
  6313. layout (location = 0) out vec4 ocol0;
  6314. layout (location = 2) out vec4 ocol2;
  6315. layout (location = 3) out vec4 ocol3;
  6316.  
  6317. void main()
  6318. {
  6319.         h2 = diff_color;
  6320.         r0 = h2;
  6321.         r2 = h2;
  6322.         r3 = h2;
  6323.         r0 = texture(tex0, tc0.xy);
  6324.         ocol0 = r0;
  6325.         ocol2 = r2;
  6326.         ocol3 = r3;
  6327. }
  6328.  
  6329. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6330. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6331. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6332. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6333. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6334. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6335. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6336. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6337. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6338. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6339. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6340. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6341. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6342. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6343. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6344. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6345. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6346. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6347. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6348. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6349. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6350. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6351. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6352. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6353. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6354. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6355. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6356. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6357. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6358. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6359. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6360. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6361. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6362. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6363. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6364. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6365. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6366. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6367. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6368. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6369. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6370. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6371. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6372. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6373. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6374. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6375. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6376. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6377. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6378. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6379. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6380. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6381. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6382. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6383. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6384. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6385. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6386. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6387. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6388. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6389. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6390. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6391. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6392. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6393. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6394. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6395. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6396. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6397. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6398. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6399. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6400. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6401. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6402. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6403. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6404. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6405. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6406. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6407. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6408. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6409. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6410. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6411. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6412. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6413. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6414. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6415. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6416. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6417. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6418. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6419. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6420. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6421. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6422. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6423. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6424. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6425. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6426. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6427. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6428. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6429. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6430. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6431. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6432. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6433. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6434. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6435. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6436. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6437. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6438. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6439. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6440. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6441. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6442. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6443. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6444. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6445. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6446. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6447. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6448. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6449. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6450. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6451. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6452. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6453. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6454. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6455. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6456. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6457. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6458. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6459. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6460. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6461. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6462. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6463. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6464. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6465. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6466. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6467. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6468. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6469. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6470. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6471. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6472. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6473. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6474. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6475. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6476. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6477. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6478. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6479. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6480. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6481. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6482. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6483. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6484. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6485. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6486. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6487. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6488. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6489. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6490. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6491. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6492. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6493. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6494. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6495. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6496. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6497. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6498. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6499. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6500. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6501. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6502. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6503. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6504. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6505. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6506. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6507. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6508. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6509. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6510. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6511. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6512. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6513. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6514. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6515. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6516. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6517. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6518. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6519. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6520. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6521. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6522. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6523. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6524. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6525. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6526. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6527. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6528. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6529. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6530. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6531. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6532. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6533. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6534. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6535. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6536. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6537. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6538. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6539. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6540. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6541. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6542. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6543. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6544. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6545. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6546. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6547. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6548. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6549. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6550. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6551. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6552. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6553. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6554. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6555. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6556. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6557. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6558. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6559. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6560. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6561. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6562. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6563. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6564. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6565. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6566. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6567. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6568. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6569. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6570. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6571. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6572. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6573. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6574. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6575. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6576. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6577. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6578. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6579. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6580. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6581. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6582. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6583. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6584. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6585. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6586. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6587. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6588. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6589. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6590. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6591. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6592. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6593. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6594. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6595. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6596. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6597. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6598. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6599. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6600. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6601. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6602. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6603. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6604. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6605. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6606. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6607. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6608. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6609. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6610. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6611. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6612. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6613. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6614. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6615. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6616. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6617. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6618. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6619. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6620. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6621. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6622. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6623. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6624. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6625. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6626. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6627. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6628. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6629. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6630. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6631. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6632. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6633. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6634. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6635. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6636. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6637. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6638. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6639. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6640. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6641. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6642. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6643. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6644. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6645. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6646. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6647. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6648. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6649. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6650. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6651. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6652. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6653. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6654. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6655. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6656. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6657. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6658. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6659. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6660. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6661. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6662. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6663. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6664. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6665. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6666. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6667. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6668. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6669. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6670. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6671. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6672. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6673. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6674. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6675. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6676. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6677. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6678. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6679. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6680. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6681. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6682. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6683. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6684. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6685. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6686. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6687. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6688. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6689. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6690. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6691. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6692. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6693. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6694. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6695. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6696. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6697. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6698. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6699. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6700. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6701. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6702. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6703. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6704. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6705. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6706. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6707. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6708. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6709. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6710. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6711. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6712. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6713. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6714. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6715. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6716. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6717. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6718. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6719. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6720. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6721. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6722. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6723. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6724. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6725. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6726. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6727. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6728. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6729. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6730. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6731. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6732. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6733. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6734. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6735. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6736. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6737. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6738. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6739. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6740. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6741. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6742. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6743. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6744. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6745. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6746. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6747. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6748. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6749. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6750. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6751. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6752. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6753. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6754. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6755. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6756. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6757. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6758. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6759. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6760. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6761. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6762. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6763. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6764. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6765. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6766. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6767. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6768. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6769. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6770. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6771. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6772. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6773. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6774. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6775. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6776. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6777. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6778. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6779. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6780. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6781. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6782. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6783. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6784. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6785. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6786. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6787. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6788. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6789. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6790. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6791. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6792. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6793. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6794. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6795. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6796. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6797. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6798. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6799. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6800. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6801. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6802. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6803. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6804. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6805. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6806. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6807. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6808. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6809. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6810. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6811. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6812. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6813. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6814. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6815. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6816. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6817. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6818. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6819. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6820. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6821. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6822. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6823. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6824. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6825. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6826. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6827. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6828. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6829. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6830. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6831. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6832. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6833. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6834. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6835. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6836. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6837. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6838. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6839. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6840. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6841. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6842. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6843. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6844. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6845. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6846. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6847. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6848. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6849. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6850. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6851. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6852. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6853. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6854. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6855. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6856. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6857. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6858. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6859. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6860. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6861. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6862. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6863. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6864. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6865. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6866. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6867. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6868. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6869. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6870. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6871. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6872. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6873. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6874. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6875. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6876. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6877. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6878. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6879. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6880. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6881. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6882. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6883. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6884. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6885. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6886. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6887. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6888. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6889. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6890. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6891. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6892. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6893. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6894. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6895. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6896. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6897. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6898. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6899. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6900. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6901. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6902. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6903. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6904. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6905. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6906. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6907. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6908. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6909. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6910. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6911. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6912. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6913. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6914. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6915. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6916. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6917. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6918. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6919. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6920. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6921. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6922. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6923. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6924. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6925. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6926. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6927. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6928. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6929. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6930. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6931. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6932. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6933. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6934. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6935. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6936. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6937. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6938. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6939. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6940. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6941. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6942. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6943. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6944. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6945. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6946. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6947. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6948. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6949. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6950. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6951. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6952. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6953. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6954. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6955. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6956. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6957. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6958. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6959. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6960. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6961. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6962. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6963. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6964. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  6965. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  6966. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  6967. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  6968. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  6969. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  6970. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  6971. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  6972. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  6973. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  6974. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  6975. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6976. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6977. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6978. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6979. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6980. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6981. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  6982. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6983. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  6984. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  6985. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6986. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6987. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6988. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6989. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6990. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6991. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6992. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  6993. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6994. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  6995. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  6996. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6997. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  6998. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  6999. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7000. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7001. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7002. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7003. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7004. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7005. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7006. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7007. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7008. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7009. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7010. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7011. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7012. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7013. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7014. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7015. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7016. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7017. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7018. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7019. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7020. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7021. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7022. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7023. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7024. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7025. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7026. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7027. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7028. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7029. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7030. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7031. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7032. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7033. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7034. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7035. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7036. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7037. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7038. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7039. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7040. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7041. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7042. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7043. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7044. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7045. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7046. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7047. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7048. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7049. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7050. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7051. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7052. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7053. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7054. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7055. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7056. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7057. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7058. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7059. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7060. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7061. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7062. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7063. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7064. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7065. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7066. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7067. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7068. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7069. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7070. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7071. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7072. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7073. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7074. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7075. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7076. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7077. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7078. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7079. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7080. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7081. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7082. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7083. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7084. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7085. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7086. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7087. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7088. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7089. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7090. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7091. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7092. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7093. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7094. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7095. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7096. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7097. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7098. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7099. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7100. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7101. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7102. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7103. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7104. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7105. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7106. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7107. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7108. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7109. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7110. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7111. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7112. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7113. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7114. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7115. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7116. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7117. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7118. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7119. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7120. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7121. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7122. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7123. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7124. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7125. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7126. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7127. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7128. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7129. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7130. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7131. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7132. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7133. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7134. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7135. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7136. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7137. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7138. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7139. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7140. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7141. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7142. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7143. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7144. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7145. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7146. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7147. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7148. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7149. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7150. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7151. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7152. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7153. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7154. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7155. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7156. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7157. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7158. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7159. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7160. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7161. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7162. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7163. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7164. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7165. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7166. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7167. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7168. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7169. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7170. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7171. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7172. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7173. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7174. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7175. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7176. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7177. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7178. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7179. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7180. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7181. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7182. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7183. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7184. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7185. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7186. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7187. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7188. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7189. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7190. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7191. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7192. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7193. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7194. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7195. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7196. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7197. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7198. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7199. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7200. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7201. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7202. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7203. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7204. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7205. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7206. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7207. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7208. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7209. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7210. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7211. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7212. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7213. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7214. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7215. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7216. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7217. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7218. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7219. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7220. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7221. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7222. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7223. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7224. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7225. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7226. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7227. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7228. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7229. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7230. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7231. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7232. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7233. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7234. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7235. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7236. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7237. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7238. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7239. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7240. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7241. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7242. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7243. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7244. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7245. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7246. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7247. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7248. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7249. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7250. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7251. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7252. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7253. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7254. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7255. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7256. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7257. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7258. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7259. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7260. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7261. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7262. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7263. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7264. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7265. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7266. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7267. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7268. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7269. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7270. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7271. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7272. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7273. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7274. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7275. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7276. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7277. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7278. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7279. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7280. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7281. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7282. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7283. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7284. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7285. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7286. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7287. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7288. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7289. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7290. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7291. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7292. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7293. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7294. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7295. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7296. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7297. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7298. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7299. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7300. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7301. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7302. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7303. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7304. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7305. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7306. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7307. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7308. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7309. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7310. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7311. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7312. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7313. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7314. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7315. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7316. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7317. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7318. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7319. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7320. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7321. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7322. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7323. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7324. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7325. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7326. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7327. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7328. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7329. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7330. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7331. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7332. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7333. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7334. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7335. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7336. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7337. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7338. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7339. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7340. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7341. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7342. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7343. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7344. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7345. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7346. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7347. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7348. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7349. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7350. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7351. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7352. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7353. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7354. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7355. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7356. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7357. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7358. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7359. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7360. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7361. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7362. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7363. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7364. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7365. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7366. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7367. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7368. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7369. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7370. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7371. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7372. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7373. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7374. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7375. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7376. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7377. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7378. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7379. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7380. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7381. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7382. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7383. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7384. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7385. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7386. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7387. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7388. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7389. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7390. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7391. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7392. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7393. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7394. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7395. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7396. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7397. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7398. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7399. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7400. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7401. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7402. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7403. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7404. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7405. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7406. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7407. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7408. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7409. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7410. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7411. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7412. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7413. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7414. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7415. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7416. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7417. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7418. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7419. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7420. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7421. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7422. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7423. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7424. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7425. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7426. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7427. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7428. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7429. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7430. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7431. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7432. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7433. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7434. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7435. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7436. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7437. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7438. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7439. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7440. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7441. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7442. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7443. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7444. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7445. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7446. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7447. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7448. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7449. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7450. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7451. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7452. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7453. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7454. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7455. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7456. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7457. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7458. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7459. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7460. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7461. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7462. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7463. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7464. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7465. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7466. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7467. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7468. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7469. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7470. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7471. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7472. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7473. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7474. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7475. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7476. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7477. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7478. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7479. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7480. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7481. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7482. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7483. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7484. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7485. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7486. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7487. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7488. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7489. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7490. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7491. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7492. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7493. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7494. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7495. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7496. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7497. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7498. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7499. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7500. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7501. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7502. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7503. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7504. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7505. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7506. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7507. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7508. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7509. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7510. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7511. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7512. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7513. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7514. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7515. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7516. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7517. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7518. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7519. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7520. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7521. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7522. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7523. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7524. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7525. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7526. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7527. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7528. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7529. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7530. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7531. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7532. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7533. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7534. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7535. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7536. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7537. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7538. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7539. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7540. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7541. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7542. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7543. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7544. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7545. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7546. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7547. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7548. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7549. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7550. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7551. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7552. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7553. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7554. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7555. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7556. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7557. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7558. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7559. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7560. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7561. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7562. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7563. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7564. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7565. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7566. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7567. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7568. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7569. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7570. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7571. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7572. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7573. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7574. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7575. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7576. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7577. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7578. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7579. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7580. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7581. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7582. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7583. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7584. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7585. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7586. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7587. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7588. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7589. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7590. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7591. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7592. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7593. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7594. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7595. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7596. RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
  7597. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7598. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
  7599. RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
  7600. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7601. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7602. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7603. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7604. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7605. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7606. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7607. RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
  7608. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7609. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7610. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7611. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7612. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
  7613. RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
  7614. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7615. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7616. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7617. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7618. RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
  7619. RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
  7620. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
  7621. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
  7622. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
  7623. HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
  7624. RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
  7625. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
  7626. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
  7627. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
  7628. RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
  7629. RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
  7630. RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
  7631. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 36
  7632. HLE: W {PPU[1] Thread (CPUThread)[0x00fa10a0]} cellSysutil warning: cellAudioOutGetSoundAvailability(audioOut=0, type=0, fs=0x4, option=0)
  7633. HLE: W {PPU[1] Thread (CPUThread)[0x00fa1058]} cellSysutil warning: cellAudioOutConfigure(audioOut=0, config_addr=0xd000fa3c, option_addr=0x0, (!)waitForEvent=0)
  7634. HLE: W {PPU[1] Thread (CPUThread)[0x00fa3010]} cellAudio warning: cellAudioInit()
  7635. HLE: ! {Audio Thread} Audio thread started
  7636. HLE: W {PPU[1] Thread (CPUThread)[0x00fa3058]} cellAudio warning: cellAudioPortOpen(audioParam_addr=0xd000fa50, portNum_addr=0xd000fa28)
  7637. HLE: W {PPU[1] Thread (CPUThread)[0x00fa3058]} cellAudio warning: *** audio port opened(nChannel=8, nBlock=8, attr=0x0, level=1.000000): port = 0
  7638. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 37
  7639. HLE: W {PPU[1] Thread (CPUThread)[0x00fa3034]} cellAudio warning: cellAudioGetPortConfig(portNum=0x0, portConfig_addr=0xd000f4c8)
  7640. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb118]} sysPrxForUser warning: sys_spu_image_import(img=0x31f1a334, src=0xc09900, type=0x1)
  7641. LDR: W {PPU[1] Thread (CPUThread)[0x00fbb118]} LoadShdr32 error: shstrndx too big!
  7642. LDR: W {PPU[1] Thread (CPUThread)[0x00fbb118]} desc = 'PS3_SPU_Release/fmodps3_spu.elf'
  7643. HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317b3d28, attr_addr=0xd000f300, initial_count=0, max_count=65535)
  7644. HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 38
  7645. PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD BGM status query thread] (flags=0x0, entry=0xcd0bc0): id = 39
  7646. HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_flash/sys/external/flashMP3.pic" opened: fd = 40
  7647. HLE: W {PPU[1] Thread (CPUThread)[0x00c4b004]} sys_fs warning: cellFsClose(fd=40)
  7648. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 41
  7649. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 42
  7650. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 43
  7651. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 44
  7652. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 45
  7653. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 46
  7654. HLE: W {PPU[1] Thread (CPUThread)[0x00fa30a0]} cellAudio warning: cellAudioPortStart(portNum=0x0)
  7655. HLE: W {PPU[1] Thread (CPUThread)[0x008fede4]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a348, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
  7656. HLE: W {PPU[1] Thread (CPUThread)[0x008fede4]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x1): id = 47
  7657. HLE: W {PPU[1] Thread (CPUThread)[0x008fee14]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a670, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
  7658. HLE: W {PPU[1] Thread (CPUThread)[0x008fee14]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x2): id = 48
  7659. HLE: W {PPU[1] Thread (CPUThread)[0x008fee34]} sys_event warning: sys_event_port_create(eport_id_addr=0x31f1a34c, port_type=0x1, name=0x0)
  7660. HLE: W {PPU[1] Thread (CPUThread)[0x008fee34]} sys_event warning: *** sys_event_port created: id = 49
  7661. HLE: W {PPU[1] Thread (CPUThread)[0x008fee4c]} sys_event warning: sys_event_port_connect_local(eport_id=49, equeue_id=48)
  7662. HLE: W {PPU[1] Thread (CPUThread)[0x008feea0]} sys_spu warning: sys_spu_thread_group_create(id_addr=0x31f1a32c, num=1, prio=16, attr_addr=0xd000f33c)
  7663. HLE: W {PPU[1] Thread (CPUThread)[0x008feea0]} sys_spu warning: *** SPU Thread Group created [FMOD] (type=0x0, option.ct=0x0): id=50
  7664. HLE: W {PPU[1] Thread (CPUThread)[0x008fef34]} sys_spu warning: sys_spu_thread_initialize(thread_addr=0x31f1a330, group=0x32, spu_num=0, img_addr=0x31f1a334, attr_addr=0xd000f330, arg_addr=0xd000f360)
  7665. HLE: W {PPU[1] Thread (CPUThread)[0x008fef34]} sys_spu warning: *** New SPU Thread [FMOD] (img_offset=0xfbf000, ls_offset=0xfff000, ep=0xf0, a1=0x3200000000000000, a2=0x317c2ec400000000, a3=0x317c2d8000000000, a4=0xf78f0000000000): id=51
  7666. HLE: W {PPU[1] Thread (CPUThread)[0x008fef54]} sys_spu warning: sys_spu_thread_connect_event(id=51, eq_id=47, event_type=0x1, spup=9)
  7667. HLE: W {PPU[1] Thread (CPUThread)[0x008fef70]} sys_spu warning: sys_spu_thread_bind_queue(id=51, equeue_id=48, spuq_num=0x63)
  7668. HLE: W {PPU[1] Thread (CPUThread)[0x008fefa4]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a350, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
  7669. HLE: W {PPU[1] Thread (CPUThread)[0x008fefa4]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x1): id = 52
  7670. HLE: W {PPU[1] Thread (CPUThread)[0x008fefd0]} sys_spu warning: sys_spu_thread_connect_event(id=51, eq_id=52, event_type=0x1, spup=8)
  7671. HLE: W {PPU[1] Thread (CPUThread)[0x008fefe4]} sys_spu warning: sys_spu_thread_group_start(id=50)
  7672. HLE: W {PPU[1] Thread (CPUThread)[0x008feffc]} sys_spu warning: sys_spu_thread_set_spu_cfg(id=51, value=0x0)
  7673. HLE: W {PPU[1] Thread (CPUThread)[0x00fa3004]} cellAudio warning: cellAudioCreateNotifyEventQueue(id_addr=0x31f1a0a4, key_addr=0x31f1a0a8)
  7674. HLE: W {PPU[1] Thread (CPUThread)[0x00fa301c]} cellAudio warning: cellAudioSetNotifyEventQueue(key=0x80004d494f323221)
  7675. HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317c3018, attr_addr=0xd000f2e0, initial_count=0, max_count=65535)
  7676. HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 54
  7677. PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD libAudio event receive thread] (flags=0x0, entry=0xcd0bc0): id = 55
  7678. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 56
  7679. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 57
  7680. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 58
  7681. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 59
  7682. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 60
  7683. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 61
  7684. HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317c30e8, attr_addr=0xd000f460, initial_count=0, max_count=65535)
  7685. HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 62
  7686. PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD stream thread] (flags=0x0, entry=0xcd0bc0): id = 63
  7687. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 64
  7688. HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 65
  7689. HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_hdd0/game/NPUB30817/USRDIR/AUDIO/PS3/WormsNext.fev" opened: fd = 66
  7690. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7691. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7692. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7693. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7694. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7695. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7696. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7697. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7698. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7699. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7700. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7701. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7702. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7703. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7704. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7705. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7706. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7707. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7708. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7709. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7710. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7711. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7712. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7713. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7714. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7715. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7716. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7717. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7718. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7719. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7720. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7721. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7722. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7723. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7724. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7725. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7726. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7727. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7728. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7729. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7730. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7731. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7732. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7733. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7734. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7735. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7736. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7737. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7738. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7739. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7740. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7741. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7742. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7743. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7744. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7745. TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
  7746. HLE: W {PPU[55] Thread (FMOD libAudio event receive thread)[0x009000d4]} sys_event_queue_receive(equeue=47) aborted
  7747. RSX: W {RSXThread} RSX thread aborted
  7748. HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa101c]} cellSysutilCheckCallback() aborted
  7749. RSX: W {VBlank thread} VBlank thread aborted
  7750. HLE: W {Audio Thread} Audio thread aborted
  7751. HLE: ! All threads stopped...
  7752. RSX: W GLVertexProgram::Delete(): glDeleteShader(2) avoided
  7753. RSX: W GLShaderProgram::Delete(): glDeleteShader(7) avoided
  7754. MEM: ! Closing memory...
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