HLE: ! path: /dev_hdd0/game/
LDR: ! Loading 'C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/USRDIR/BOOT.BIN'...
LDR: !  
LDR: ! Mount info:
LDR: ! /dev_hdd0/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd0/
LDR: ! /dev_hdd1/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd1/
LDR: ! /dev_flash/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_flash/
LDR: ! /dev_usb000/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_usb000/
LDR: ! /dev_usb/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_usb000/
LDR: ! /app_home/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
LDR: ! /host_root/ -> 
LDR: ! USRDIR/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR
LDR: ! //dev_hdd0/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64/dev_hdd0/
LDR: ! / -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
LDR: ! shader/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR/shader/
LDR: ! ps3texture/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//USRDIR/ps3texture/
LDR: ! /dev_bdvd/PS3_GAME/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817/
LDR: ! /dev_bdvd/ -> C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\game\NPUB30817//../
LDR: !  
MEM: ! Initing memory: m_base_addr = 0x180050000
MEM: ! Memory initialized.
LDR: W Unimplemented function 'cellFsSdataOpenByFd' in 'sys_fs' module
LDR: W Unimplemented function 'cellFsFsync' in 'sys_fs' module
LDR: W Unimplemented function 'sceNpMatching2DestroyContext' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetWorldInfoList' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2SearchRoom' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2SignalingGetConnectionStatus' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2LeaveRoom' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2SetRoomDataExternal' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2Term2' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetServerInfo' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetEventData' in 'sceNp2' module
LDR: W Unimplemented function 'sceNp2Init' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2JoinRoom' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetRoomMemberDataInternalLocal' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2ContextStartAsync' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2RegisterContextCallback' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2SetRoomDataInternal' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetServerIdListLocal' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2CreateContext' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2RegisterSignalingCallback' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2ClearEventData' in 'sceNp2' module
LDR: W Unimplemented function 'sceNp2Term' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2RegisterRoomEventCallback' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2GetRoomDataExternalList' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2CreateJoinRoom' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2Init2' in 'sceNp2' module
LDR: W Unimplemented function 'sceNpMatching2RegisterRoomMessageCallback' in 'sceNp2' module
LDR: W Unimplemented function 'inet_ntoa' in 'sys_net' module
LDR: W Unimplemented function 'inet_aton' in 'sys_net' module
LDR: W Unimplemented function 'socketselect' in 'sys_net' module
LDR: W Unimplemented function 'cellOskDialogGetInputText' in 'cellSysutil' module
LDR: W Unimplemented function 'cellOskDialogGetSize' in 'cellSysutil' module
LDR: W Unimplemented function 'cellOskDialogUnloadAsync' in 'cellSysutil' module
LDR: W Unimplemented function 'cellSaveDataUserAutoSave' in 'cellSysutil' module
LDR: W Unimplemented function 'cellOskDialogLoadAsync' in 'cellSysutil' module
LDR: W Unimplemented function 'cellOskDialogSetKeyLayoutOption' in 'cellSysutil' module
LDR: W Unimplemented function 'cellOskDialogSetInitialKeyLayout' in 'cellSysutil' module
LDR: W Unimplemented function 'cellSaveDataUserAutoLoad' in 'cellSysutil' module
LDR: W Unimplemented function 'cellAudioAdd6chData' in 'cellAudio' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterGetFrame' in 'cellSail' module
LDR: W Unimplemented function 'cellSailDescriptorCreateDatabase' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerSetSoundAdapter' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterPtsToTimePosition' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerFinalize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerSetGraphicsAdapter' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterInitialize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterSetPreferredFormat' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerInitialize2' in 'cellSail' module
LDR: W Unimplemented function 'cellSailDescriptorDestroyDatabase' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterSetPreferredFormat' in 'cellSail' module
LDR: W Unimplemented function 'cellSailMemAllocatorInitialize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerOpenStream' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterInitialize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterUpdateAvSync' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterPtsToTimePosition' in 'cellSail' module
LDR: W Unimplemented function 'cellSailFutureInitialize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerSetParameter' in 'cellSail' module
LDR: W Unimplemented function 'cellSailAviMovieGetMovieInfo' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterFinalize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerAddDescriptor' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterGetFrame' in 'cellSail' module
LDR: W Unimplemented function 'cellSailFutureFinalize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerBoot' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterFinalize' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerCreateDescriptor' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerStart' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterUpdateAvSync' in 'cellSail' module
LDR: W Unimplemented function 'cellSailSoundAdapterGetFormat' in 'cellSail' module
LDR: W Unimplemented function 'cellSailPlayerSetRepeatMode' in 'cellSail' module
LDR: W Unimplemented function 'cellSailGraphicsAdapterGetFormat' in 'cellSail' module
LDR: W Unimplemented function 'sceNpBasicSendMessageGui' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicGetFriendListEntry' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreGetRankingByRangeAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreSetTimeout' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreSanitizeCommentAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreInit' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreGetRankingByNpIdAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicRegisterContextSensitiveHandler' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerGetCachedInfo' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerUnregisterCallback' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicSetPresenceDetails2' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupInit' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicRecvMessageAttachmentLoad' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerGetContentRatingFlag' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreCreateTransactionCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicGetBlockListEntryCount' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupPollAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicRecvMessageCustom' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupTerm' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupTitleSmallStorageAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScorePollAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicUnregisterHandler' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicGetFriendListEntryCount' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreCreateTitleCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicAddPlayersHistoryAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreDestroyTransactionCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupCreateTitleCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpProfileCallGui' in 'sceNp' module
LDR: W Unimplemented function 'sceNpUtilCmpNpId' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicGetEvent' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerRegisterCallback' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupCreateTransactionCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerGetChatRestrictionFlag' in 'sceNp' module
LDR: W Unimplemented function 'sceNpScoreRecordScoreAsync' in 'sceNp' module
LDR: W Unimplemented function 'sceNpBasicGetBlockListEntry' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerGetOnlineName' in 'sceNp' module
LDR: W Unimplemented function 'sceNpLookupDestroyTransactionCtx' in 'sceNp' module
LDR: W Unimplemented function 'sceNpManagerGetNpId' in 'sceNp' module
LDR: W Unknown module 'cellSysutilAvc2'
LDR: W Unknown module 'sceNpCommerce2'
LDR: W Unimplemented function 'cellMicOpenEx' in 'cellMic' module
LDR: W Unimplemented function 'cellMicRead' in 'cellMic' module
LDR: W Unimplemented function 'cellMicSetNotifyEventQueue' in 'cellMic' module
LDR: W Unimplemented function 'cellMicClose' in 'cellMic' module
LDR: W Unimplemented function 'cellMicStart' in 'cellMic' module
LDR: W Unimplemented function 'cellMicStop' in 'cellMic' module
LDR: W Unknown module 'cellSysutilAvconfExt'
LDR: W Unimplemented function 'sys_prx_load_module_on_memcontainer_by_fd' in 'sysPrxForUser' module
LDR: W Unimplemented function 'sys_prx_load_module_by_fd' in 'sysPrxForUser' module
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 3
HLE: W {PPU[1] Thread (CPUThread)[0x009d3c34]} memory warning: sys_memory_get_user_memory_size(mem_info_addr=0xd0010c04)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 4
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 5
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 6
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 7
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 8
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 9
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 10
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 11
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 12
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_RTC)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_GCM_SYS)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_IO)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_USBD)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_FS)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_NET)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_AUDIO)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_ATRAC3PLUS)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP2)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_AVCHAT2)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_GAME)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_COMMERCE2)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_SAVEDATA)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_USERINFO)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_TROPHY)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SAIL)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_AVCONF_EXT)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_SYSUTIL_NP_COMMERCE2)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 13
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 14
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 15
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 16
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 17
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 18
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 19
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 20
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 21
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 22
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 23
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 24
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [ps3HDDL] (attribute=0x12): sq_id = 25
HLE: W {PPU[1] Thread (CPUThread)[0x009c3910]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009c3910]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009cae34]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x009c38bc]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009c38bc]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_TIMEZONE
HLE: W {PPU[1] Thread (CPUThread)[0x009c5380]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_SUMMERTIME
HLE: W {PPU[1] Thread (CPUThread)[0x007455d4]} sys_spu warning: sys_spu_initialize(max_usable_spu=5, max_raw_spu=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=0, func_addr=0xcacae0, userdata=0x0)
HLE: E {PPU[1] Thread (CPUThread)[0x00f9b070]} TODO: sceNp2Init
HLE: W {PPU[1] Thread (CPUThread)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd0010520, attributes_addr=0xd0010524, size_addr=0xd0010528, dirName_addr=0xd0010538)
HLE: W {PPU[1] Thread (CPUThread)[0x00fb101c]} cellGame warning: cellGameGetParamInt(id=102, value_addr=0xd090e0)
HLE: W {PPU[1] Thread (CPUThread)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd0010558, usrdirPath_addr=0xd00105d8)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable(k_licensee_addr=0xf55498, drm_path_addr=0xd000fb60)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Found DRM license file at /dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Using k_licensee 0xad4d54f97a88778baf7da0bbcad5c8be
LDR: E {PPU[1] Thread (CPUThread)[0x00fa9118]} EDAT: File has invalid NPD header.
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable(k_licensee_addr=0xf55498, drm_path_addr=0xd000fb60)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Found DRM license file at /dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT
HLE: W {PPU[1] Thread (CPUThread)[0x00fa9118]} sceNp warning: sceNpDrmIsAvailable: Using k_licensee 0xad4d54f97a88778baf7da0bbcad5c8be
LDR: E {PPU[1] Thread (CPUThread)[0x00fa9118]} EDAT: File has invalid NPD header.
HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/data.EDAT" opened: fd = 26
HLE: E {PPU[1] Thread (CPUThread)[0x00c4b028]} sys_fs error: "/dev_hdd0/game/NPUB30817/USRDIR/Default.cfg" not found! flags: 0x00000000
HLE: W {PPU[1] Thread (CPUThread)[0x00fa104c]} cellSysutil warning: cellSysutilGetSystemParamInt: CELL_SYSUTIL_SYSTEMPARAM_ID_LANG
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_GCM_SYS)
HLE: W {PPU[1] Thread (CPUThread)[0x00c47004]} cellSysmodule warning: cellSysmoduleLoadModule(CELL_SYSMODULE_RESC)
HLE: W {PPU[1] Thread (CPUThread)[0x00504960]} sys_spu warning: sys_raw_spu_create(id_addr=0xed6364, attr_addr=0xd0010220)
SPU: E {PPU[1] Thread (CPUThread)[0x00504d10]} RawSPUThread[0]: Read32(MFC_CMDStatus)
SPU: E {PPU[1] Thread (CPUThread)[0x00504d10]} RawSPUThread[0]: Read32(MFC_CMDStatus)
SPU: W {PPU[1] Thread (CPUThread)[0x0050500c]} RawSPUThread[0]: Write32(Prxy_QueryMask, 0x80000000)
SPU: W {PPU[1] Thread (CPUThread)[0x00505010]} RawSPUThread[0]: Write32(Prxy_QueryType, 0x2)
SPU: W {PPU[1] Thread (CPUThread)[0x00505010]} RawSPUThread[0]: Prxy Query Immediate.
SPU: W {PPU[1] Thread (CPUThread)[0x00505020]} RawSPUThread[0]: Read32(MFC_QStatus)
SPU: W {PPU[1] Thread (CPUThread)[0x00505060]} RawSPUThread[0]: Write32(SPU_NPC, 0xe0)
SPU: W {PPU[1] Thread (CPUThread)[0x00504700]} RawSPUThread[0]: Write32(SPU_NPC, 0xe0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmInit(context_addr=0xf6629c,cmdSize=0x10000,ioSize=0xb00000,ioAddress=0x30200000)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: *** local memory(addr=0xc0000000, size=0xf900000)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmInit(): 256MB io address space used
HLE: W {PPU[1] Thread (CPUThread)[0x00c49010]} cellGcmSys warning: cellGcmMapEaIoAddress(ea=0x30200000, io=0x0, size=0xb00000)
RSX: ! {RSXThread} RSX thread started
HLE: W {PPU[1] Thread (CPUThread)[0x00c49070]} cellGcmSys warning: cellGcmSetDebugOutputLevel(level=2)
HLE: E {PPU[1] Thread (CPUThread)[0x00c4916c]} cellGcmSys error: Unimplemented function: cellGcmSetGraphicsHandler
RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49094]} cellGcmSys warning: cellGcmMapEaIoAddress(ea=0x30f00000, io=0xe000000, size=0x100000)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=2)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=3)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=4)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=5)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=6)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=7)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=8)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=9)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=10)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=11)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=12)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=13)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49184]} cellGcmSys warning: cellGcmUnbindTile(index=14)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=0, location=0, offset=253231104, size=7864320, pitch=10240, comp=7, base=1, bank=0)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (7)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=0)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 3
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=1, location=0, offset=245366784, size=7864320, pitch=10240, comp=7, base=121, bank=0)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (7)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=1)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 5
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=2, location=0, offset=241434624, size=3932160, pitch=5120, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=2)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 7
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=2, location=0, offset=237502464, size=7864320, pitch=5120, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=2)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 9
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=3, location=0, offset=229638144, size=7864320, pitch=10240, comp=11, base=241, bank=3)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (11)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=3)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: b
HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=0)
HLE: W {PPU[1] Thread (CPUThread)[0x005624f4]} sys_semaphore warning: sys_semaphore_create(sem_addr=0xed6a28, attr_addr=0xd0010120, initial_count=1, max_count=2)
HLE: ! {PPU[1] Thread (CPUThread)[0x005624f4]} *** semaphore created [] (protocol=0x2): id = 28
HLE: W {PPU[1] Thread (CPUThread)[0x00c490f4]} cellGcmSys warning: cellGcmSetFlipHandler(handler_addr=13270752)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49130]} cellGcmSys warning: cellGcmSetVBlankHandler(handler_addr=0xca7f00)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa1010]} cellSysutil warning: cellVideoOutConfigure(videoOut=0, config_addr=0xd00100f0, option_addr=0x0, waitForEvent=0x0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49064]} cellGcmSys warning: cellGcmSetFlipMode(mode=1)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
HLE: W {PPU[1] Thread (CPUThread)[0x005040cc]} sys_mutex warning: *** mutex created [] (protocol=0x2, recursive=false): id = 29
HLE: W {PPU[1] Thread (CPUThread)[0x00504274]} sys_cond warning: *** condition created [] (mutex_id=29): id = 30
HLE: W {PPU[1] Thread (CPUThread)[0x00c49064]} cellGcmSys warning: cellGcmSetFlipMode(mode=2)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
HLE: E {PPU[1] Thread (CPUThread)[0x00c4b028]} sys_fs error: "/dev_hdd0/game/NPUB30817/USRDIR/BuildInfo.txt" not found! flags: 0x00000000
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [XPlatform::SwitchPs3::Main] (flags=0x0, entry=0xcae990): id = 31
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
RSX: E {RSXThread} NV4097_SET_POINT_PARAMS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: d
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=229376000, size=262144, pitch=2048, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} FP not found in buffer!
RSX: W {RSXThread} VP not found in buffer!
RSX: ! {RSXThread} Add program (0):
RSX: ! {RSXThread} *** prog id = 3
RSX: ! {RSXThread} *** vp id = 2
RSX: ! {RSXThread} *** fp id = 1
RSX: ! {RSXThread} *** vp data size = 5680
RSX: ! {RSXThread} *** fp data size = 224
RSX: ! {RSXThread} *** vp shader = 
#version 330

uniform mat4 scaleOffsetMat = mat4(1.0);
vec4 tmp0;
vec4 tmp3;
vec4 cc0 = vec4(0.0);
vec4 tmp5;
vec4 tmp4;
vec4 tmp2;
vec4 tmp1;
vec4 tmp14;
vec4 tmp8;
vec4 tmp6;
vec4 tmp7;
vec4 tmp9;
vec4 tmp10;
vec4 tmp11;
vec4 tmp12;
vec4 tmp13;
vec4 tmp15;
vec4 tmp16;
vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
vec4 dst_reg1 = vec4(0.0);
vec4 dst_reg3 = vec4(0.0);
vec4 dst_reg5 = vec4(0.0);
vec4 dst_reg6 = vec4(0.0);
vec4 dst_reg10 = vec4(0.0);
vec4 dst_reg9 = vec4(0.0);
vec4 dst_reg8 = vec4(0.0);
vec4 dst_reg7 = vec4(0.0);
layout (location = 0) in vec4 in_pos;
layout (location = 2) in vec4 in_normal;
layout (location = 3) in vec4 in_diff_color;
layout (location = 8) in vec4 in_tc0;
layout (location = 9) in vec4 in_tc1;
layout (location = 10) in vec4 in_tc2;
layout (location = 11) in vec4 in_tc3;
uniform vec4 vc[468];
ivec4 a0 = ivec4(0);
out vec4 diff_color;
out vec4 front_diff_color;
out vec4 fogc;
out vec4 tc0;
out vec4 tc1;
out vec4 tc2;
out vec4 tc3;
out vec4 tc9;

void func0();

void main()
{
	func0();
	gl_Position = dst_reg0;
	diff_color = dst_reg1;
	front_diff_color = dst_reg3;
	fogc = vec4(dst_reg5.x);
	gl_ClipDistance[0] = dst_reg5.y;
	gl_ClipDistance[1] = dst_reg5.z;
	gl_ClipDistance[2] = dst_reg5.w;
	gl_PointSize = dst_reg6.x;
	gl_ClipDistance[3] = dst_reg6.y;
	gl_ClipDistance[4] = dst_reg6.z;
	gl_ClipDistance[5] = dst_reg6.w;
	tc0 = dst_reg7;
	tc1 = dst_reg8;
	tc2 = dst_reg9;
	tc3 = dst_reg10;
	tc9 = dst_reg6;
	gl_Position = gl_Position * scaleOffsetMat;
}

void func0()
{
	tmp0.w = vec4(dot(in_pos, vc[263])).w;
	tmp0.z = vec4(dot(in_pos, vc[262])).z;
	tmp0.y = vec4(dot(in_pos, vc[261])).y;
	tmp0.x = vec4(dot(in_pos, vc[260])).x;
	tmp3.w = vec4(dot(in_pos, vc[259])).w;
	tmp3.y = vec4(dot(in_pos, vc[257])).y;
	tmp3.x = vec4(dot(in_pos, vc[256])).x;
	cc0.xy = vc[467].wxww.xy;
	tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
	tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
	tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
	tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
	tmp2 = clamp(in_diff_color, 0.0, 1.0);
	tmp1 = tmp2;
	tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
	tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
	tmp3.z = tmp5.yyyy.z;
	tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
	tmp14.w = abs(tmp5.xxxx).w;
	tmp14.xyz = tmp4.xyzx.xyz;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
	if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
	{
		tmp1.xyz = vc[463].xxxx.xyz;
		tmp1.w = vc[463].xxxx.w;
		tmp4 = in_diff_color;
		cc0.x = vc[467].zzzz.x;
		tmp5.xyz = in_diff_color.xyzx.xyz;
		tmp2.x = vc[462].xxxx.x;
		cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
		if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
		{
			do
			{
				tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
				a0.x = ivec4(tmp2.xxxx).x;
				tmp8.z = vc[405].xxxx.z;
				tmp2.xyz = vc[463].xxxx.xyz;
				tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
				tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
				tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
				tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
				tmp2.w = vc[463].xxxx.w;
				cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
				cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
				cc0.x = vc[411 + a0.x].xxxx.x;
				tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
				tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
				tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
				tmp6.w = -tmp6.wwww.w;
				if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
				tmp2.w = tmp6.wwww.w;
				tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
				tmp6.w = log2(tmp6.wwww).w;
				tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
				cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
				cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
				tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
				tmp5.w = (1.0 / tmp5.wwww).w;
				tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
				tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
				cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
				tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
				tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
				tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
				tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
				tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
				tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
				if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
				tmp5.w = (1.0 / tmp2.xxxx).w;
				tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
				tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
				tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
				tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.w = (tmp2.wwww * tmp5.wwww).w;
				tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
			} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
		}
		cc0.x = vc[467].yyyy.x;
		tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
		tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
		tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
		tmp1.w = tmp4.wwww.w;
		tmp2 = clamp(tmp1, 0.0, 1.0);
		tmp1 = tmp2;
		if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
		{
			tmp2.x = vc[462].xxxx.x;
			cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
			tmp2.xyz = vc[463].xxxx.xyz;
			if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
			{
			tmp2.w = vc[463].xxxx.w;
				do
				{
					tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
					a0.x = ivec4(tmp5.wwww).x;
					tmp9.z = vc[405].xxxx.z;
					tmp6.xyz = vc[463].xxxx.xyz;
					tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
					tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
					tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
					tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
					tmp5.w = vc[463].xxxx.w;
					cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
					cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
					cc0.x = vc[411 + a0.x].xxxx.x;
					tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
					tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
					tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
					tmp8.y = -tmp7.wwww.y;
					if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
					tmp7.w = log2(tmp8.yyyy).w;
					tmp5.w = tmp8.yyyy.w;
					tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
					tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
					cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
					cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
					tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
					tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
					tmp6.w = (1.0 / tmp6.wwww).w;
					tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
					cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
					tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
					tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
					tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
					tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
					tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
					tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
					if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
					tmp6.w = (1.0 / tmp6.xxxx).w;
					tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
					tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
					tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
					tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp5.w = (tmp5.wwww * tmp6.wwww).w;
					tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
				} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
			}
			tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
			tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
			tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
			tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
		}
	}
	tmp4.x = vc[463].xxxx.x;
	tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
	tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
	tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp4 = in_tc0;
		tmp9.x = vc[400].xxxx.x;
		tmp7.zw = vc[463].xxxz.zw;
		tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp5 = (tmp3.yyyy * vc[268]);
		tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7.xy = vc[400].yzyy.xy;
		tmp4 = in_tc0;
		tmp6 = (in_pos.yyyy * vc[268]);
		tmp8.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[401], tmp8.zzzz));
		tmp6 = (in_pos.xxxx * vc[267] + tmp6);
		tmp6 = (in_pos.zzzz * vc[269] + tmp6);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
		cc0 = vec4(equal(vc[401], tmp7.xxxx));
		tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
		tmp5 = (tmp3.xxxx * vc[267] + tmp5);
		tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
		tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
		tmp5 = (tmp3.zzzz * vc[269] + tmp5);
		tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
		tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
		tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
		tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
		cc0 = vec4(equal(vc[401], tmp7.yyyy));
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
		tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
		tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
		tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
		cc0 = vec4(equal(vc[401], tmp9.xxxx));
		tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
		tmp5.w = vc[463].zzzz.w;
		tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
		cc0 = vec4(equal(vc[401], tmp8.wwww));
		tmp5.xyz = tmp14.xyzx.xyz;
		tmp5.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
	}
	tmp5.x = vc[463].xxxx.x;
	tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
	tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
	tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
	tmp5 = tmp4;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp6 = in_tc1;
		tmp9.zw = vc[463].xxxz.zw;
		tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7 = (tmp3.yyyy * vc[276]);
		tmp10.xyz = vc[400].xyzx.xyz;
		tmp6 = in_tc1;
		tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp8 = (in_pos.yyyy * vc[276]);
		tmp11.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[399], tmp11.zzzz));
		tmp8 = (in_pos.xxxx * vc[275] + tmp8);
		tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
		tmp8 = (in_pos.zzzz * vc[277] + tmp8);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
		cc0 = vec4(equal(vc[399], tmp10.yyyy));
		tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
		tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
		tmp7 = (tmp3.xxxx * vc[275] + tmp7);
		tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
		tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
		tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
		tmp7 = (tmp3.zzzz * vc[277] + tmp7);
		tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
		tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[399], tmp10.zzzz));
		tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
		tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
		tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
		tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
		cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
		cc0 = vec4(equal(vc[399], tmp10.xxxx));
		tmp7.w = vc[463].zzzz.w;
		tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
		cc0 = vec4(equal(vc[399], tmp11.wwww));
		tmp7.xyz = tmp14.xyzx.xyz;
		tmp7.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
	}
	tmp7.x = vc[463].xxxx.x;
	tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
	tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
	tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
	tmp7 = tmp6;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp8 = in_tc2;
		tmp11.zw = vc[463].xxxz.zw;
		tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp9 = (tmp3.yyyy * vc[284]);
		tmp12.xyz = vc[400].xyzx.xyz;
		tmp8 = in_tc2;
		tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp10 = (in_pos.yyyy * vc[284]);
		tmp13.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[398], tmp13.zzzz));
		tmp10 = (in_pos.xxxx * vc[283] + tmp10);
		tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
		tmp10 = (in_pos.zzzz * vc[285] + tmp10);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
		cc0 = vec4(equal(vc[398], tmp12.yyyy));
		tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
		tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
		tmp9 = (tmp3.xxxx * vc[283] + tmp9);
		tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
		tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
		tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
		tmp9 = (tmp3.zzzz * vc[285] + tmp9);
		tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
		tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[398], tmp12.zzzz));
		tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
		tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
		tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
		tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
		cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
		cc0 = vec4(equal(vc[398], tmp12.xxxx));
		tmp9.w = vc[463].zzzz.w;
		tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
		cc0 = vec4(equal(vc[398], tmp13.wwww));
		tmp9.xyz = tmp14.xyzx.xyz;
		tmp9.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
	}
	tmp9.x = vc[463].xxxx.x;
	tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
	tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
	tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
	tmp9 = tmp8;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp10 = in_tc3;
		tmp13.zw = vc[463].xxxz.zw;
		tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp11 = (tmp3.yyyy * vc[292]);
		tmp15.xyz = vc[400].xyzx.xyz;
		tmp10 = in_tc3;
		tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp12 = (in_pos.yyyy * vc[292]);
		tmp16.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[397], tmp16.zzzz));
		tmp12 = (in_pos.xxxx * vc[291] + tmp12);
		tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
		tmp12 = (in_pos.zzzz * vc[293] + tmp12);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
		cc0 = vec4(equal(vc[397], tmp15.yyyy));
		tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
		tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
		tmp11 = (tmp3.xxxx * vc[291] + tmp11);
		tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
		tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
		tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
		tmp11 = (tmp3.zzzz * vc[293] + tmp11);
		tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
		tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[397], tmp15.zzzz));
		tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
		tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
		tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
		tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
		cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
		cc0 = vec4(equal(vc[397], tmp15.xxxx));
		tmp11.w = vc[463].zzzz.w;
		tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
		cc0 = vec4(equal(vc[397], tmp16.wwww));
		tmp11.xyz = tmp14.xyzx.xyz;
		tmp11.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
	}
	dst_reg0 = tmp0;
	dst_reg1 = tmp1;
	dst_reg3 = tmp2;
	dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
	dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
	dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
	dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
	dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
	dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
	dst_reg5.x = tmp14.wwww.x;
	tmp0.w = vec4(dot(tmp10, vc[298])).w;
	tmp0.z = vec4(dot(tmp10, vc[297])).z;
	tmp0.y = vec4(dot(tmp10, vc[296])).y;
	tmp0.x = vec4(dot(tmp10, vc[295])).x;
	dst_reg10 = tmp10;
	dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
	dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
	dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
	dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
	dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
	dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
	dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
	cc0.x = vc[396].xxxx.x;
	dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
	dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
	dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
	dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
	dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
}

RSX: ! {RSXThread} *** fp shader = 
#version 330

vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r4 = vec4(0.0, 0.0, 0.0, 0.0);
in vec4 diff_color;
layout (location = 0) out vec4 ocol0;
layout (location = 2) out vec4 ocol2;
layout (location = 3) out vec4 ocol3;
layout (location = 4) out vec4 ocol4;

void main()
{
	h2 = diff_color;
	r0 = h2;
	r2 = h2;
	r3 = h2;
	h2 = diff_color;
	r0 = h2;
	r2 = h2;
	r3 = h2;
	r4 = h2;
	ocol0 = r0;
	ocol2 = r2;
	ocol3 = r3;
	ocol4 = r4;
}

RSX: W {RSXThread} New FBO (1280x720)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: f
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=229113856, size=524288, pitch=2048, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 11
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228851712, size=786432, pitch=2048, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 13
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228589568, size=1048576, pitch=2048, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 15
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=4, location=0, offset=228327424, size=1310720, pitch=2048, comp=0, base=0, bank=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=4)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 17
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=5, location=0, offset=224133120, size=4194304, pitch=4096, comp=10, base=361, bank=3)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=5)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 19
HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=1)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1b
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=6, location=0, offset=220200960, size=3932160, pitch=5120, comp=10, base=425, bank=3)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=6)
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1d
HLE: W {PPU[1] Thread (CPUThread)[0x00c490dc]} cellGcmSys warning: cellGcmBindZcull(index=2)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV406E_SEMAPHORE_ACQUIRE: 1f
HLE: W {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys warning: cellGcmSetTileInfo(index=7, location=0, offset=219217920, size=983040, pitch=2560, comp=10, base=485, bank=3)
HLE: E {PPU[1] Thread (CPUThread)[0x00c49148]} cellGcmSys error: cellGcmSetTileInfo: bad compression mode! (10)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49058]} cellGcmSys warning: cellGcmBindTile(index=7)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
HLE: W {PPU[1] Thread (CPUThread)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=2, func_addr=0xcb00a0, userdata=0x317a8f90)
HLE: W {PPU[1] Thread (CPUThread)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd000f548, attributes_addr=0xd000f544, size_addr=0xd000f550, dirName_addr=0xd000f560)
HLE: W {PPU[1] Thread (CPUThread)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd000f580, usrdirPath_addr=0xd000f600)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fb1028]} cellGame warning: cellGameBootCheck(type_addr=0xd0040490, attributes_addr=0xd0040494, size_addr=0xd00404c8, dirName_addr=0xd0040508)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fb1004]} cellGame warning: cellGameContentPermit(contentInfoPath_addr=0xd0040610, usrdirPath_addr=0xd0040590)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab040]} sceNpTrophy warning: sceNpTrophyCreateContext(context_addr=0x317a9104, commID_addr=0xd0040af0, commSign_addr=0xd0040afc, options=0x0)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab010]} sceNpTrophy warning: sceNpTrophyCreateHandle(handle_addr=0x317a9108)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9d004]} sys_net warning: sys_net_initialize_network_ex(param_addr=0xd00409d8)
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9f028]} cellNetCtl error: Unimplemented function: cellNetCtlInit
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa1088]} cellSysutil warning: cellSysutilRegisterCallback(slot=1, func_addr=0xcafd30, userdata=0x317fb760)
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00f9b070]} TODO: sceNp2Init
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9058]} TODO: sceNpBasicRegisterContextSensitiveHandler
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9184]} TODO: sceNpManagerRegisterCallback
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf028]} cellUserInfo warning: cellUserInfoGetList(listNum_addr=0xd00409b8, listBuf_addr=0xd00409e4, currentUserId_addr=0xd00409b4)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf004]} cellUserInfo warning: cellUserInfoGetStat(id=1, stat_addr=0xd0040a24)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab01c]} sceNpTrophy warning: sceNpTrophyGetRequiredDiskSpace(context=0, handle=757935405, reqspace_addr=0x317a8ed8, options=0x0)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} sceNpTrophy warning: sceNpTrophyRegisterContext(context=0, handle=757935405, statusCb_addr=0xcb08f0, arg_addr=0x0, options=0x0)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROPCONF.SFM')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\ICON0.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\GR001.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP000.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP001.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP002.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP003.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP004.PNG')
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP005.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP006.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP007.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP008.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP009.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP010.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP011.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP012.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP013.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP014.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP015.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP016.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP017.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP018.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP019.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP020.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP021.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP022.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP023.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP024.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP025.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP026.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP027.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP028.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP029.PNG')
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP030.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP031.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP032.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP033.PNG')
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fab004]} vfsLocalFile::Create('C:\Users\Default.default-00\Desktop\PS3\rpcs3-59f08f9-windows-x86-64\dev_hdd0\home\00000001\trophy\NPWR03595_00\TROP034.PNG')
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00faf028]} cellUserInfo warning: cellUserInfoGetList(listNum_addr=0xd0040874, listBuf_addr=0xd00408b8, currentUserId_addr=0xd0040878)
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00600eb8]} Unknown syscall: 872 - 00000368
HLE: E {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa9064]} TODO: sceNpManagerGetCachedInfo
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 10
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
HLE: W {PPU[1] Thread (CPUThread)[0x009ce388]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/BUNDLES/SHADERPROGS/Shaders.xom" opened: fd = 32
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 33
HLE: W {PPU[1] Thread (CPUThread)[0x009ce300]} sys_fs warning: cellFsClose(fd=32)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb0dc]} sys_lwmutex warning: sys_lwmutex_destroy(lwmutex_addr=0x31a90d20)
HLE: W {PPU[1] Thread (CPUThread)[0x009ce388]} "/dev_hdd0/game/NPUB30817/USRDIR/DATAPS3/BUNDLES/SHADERPROGS/Shaders.xom" opened: fd = 34
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [_lc_mtx] (attribute=0x12): sq_id = 35
HLE: W {PPU[1] Thread (CPUThread)[0x009ce300]} sys_fs warning: cellFsClose(fd=34)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb0dc]} sys_lwmutex warning: sys_lwmutex_destroy(lwmutex_addr=0x31a90d20)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_REDUCE_DST_COLOR: 0x 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} TODO: unknown/illegal method [0x00001fec](0x0)
RSX: E {RSXThread} NV4097_SET_POINT_PARAMS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} FP not found in buffer!
RSX: W {RSXThread} VP not found in buffer!
RSX: ! {RSXThread} Add program (1):
RSX: ! {RSXThread} *** prog id = 6
RSX: ! {RSXThread} *** vp id = 5
RSX: ! {RSXThread} *** fp id = 4
RSX: ! {RSXThread} *** vp data size = 112
RSX: ! {RSXThread} *** fp data size = 416
RSX: ! {RSXThread} *** vp shader = 
#version 330

uniform mat4 scaleOffsetMat = mat4(1.0);
vec4 tmp0;
vec4 dst_reg7 = vec4(0.0);
vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
layout (location = 0) in vec4 in_pos;
layout (location = 8) in vec4 in_tc0;
uniform vec4 vc[468];
out vec4 tc0;

void func0();

void main()
{
	func0();
	gl_Position = dst_reg0;
	tc0 = dst_reg7;
	gl_Position = gl_Position * scaleOffsetMat;
}

void func0()
{
	tmp0 = (in_pos * vc[260]);
	tmp0 = (vc[261] + tmp0);
	dst_reg7.xy = (in_tc0.xyxx * vc[262].xyxx + vc[262].zwzz).xy;
	dst_reg0.w = vec4(dot(tmp0, vc[259])).w;
	dst_reg0.z = vec4(dot(tmp0, vc[258])).z;
	dst_reg0.y = vec4(dot(tmp0, vc[257])).y;
	dst_reg0.x = vec4(dot(tmp0, vc[256])).x;
}

RSX: ! {RSXThread} *** fp shader = 
#version 330

vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 cc0;
uniform sampler2D tex0;
in vec4 tc0;
uniform vec4 fc32 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
uniform vec4 fc64 = vec4(0.010000, 0.000000, 0.000000, 0.000000);
uniform vec4 fc288 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
uniform vec4 fc320 = vec4(0.010000, 0.000000, 0.000000, 0.000000);
uniform vec4 fc400 = vec4(0.000000, 0.000000, 0.000000, 0.000000);
layout (location = 0) out vec4 ocol0;

void main()
{
	r0 = texture(tex0, tc0.xy);
	r0.w = (r0 * fc32.xxxx).w;
	cc0.x = vec4(lessThan(r0.wwww, fc64.xxxx)).x;
	if(any(notEqual(cc0.xxxx, vec4(0.0)))) discard;
	r0.w = r0.w;
	r0 = texture(tex0, tc0.xy);
	r0.w = (r0 * fc288.xxxx).w;
	cc0.x = vec4(lessThan(r0.wwww, fc320.xxxx)).x;
	if(any(notEqual(cc0.xxxx, vec4(0.0)))) discard;
	r0.w = r0.w;
	r0.xyz = (r0 + fc400).xyz;
	ocol0 = r0;
}

RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: 101
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Address(0x101)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Control0(0x8000)
RSX: W {RSXThread} TODO: cellGcmSetVertexTexture_Filter(0x0)
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 4000
RSX: W {RSXThread} NV4097_SET_TEX_COORD_CONTROL
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} TODO: cellGcmSetTwoSideLightEn(0x0)
RSX: W {RSXThread} TODO: cellGcmSetTransformBranchBits(0x0)
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} FP not found in buffer!
RSX: ! {RSXThread} Add program (2):
RSX: ! {RSXThread} *** prog id = 8
RSX: ! {RSXThread} *** vp id = 2
RSX: ! {RSXThread} *** fp id = 7
RSX: ! {RSXThread} *** vp data size = 5680
RSX: ! {RSXThread} *** fp data size = 144
RSX: ! {RSXThread} *** vp shader = 
#version 330

uniform mat4 scaleOffsetMat = mat4(1.0);
vec4 tmp0;
vec4 tmp3;
vec4 cc0 = vec4(0.0);
vec4 tmp5;
vec4 tmp4;
vec4 tmp2;
vec4 tmp1;
vec4 tmp14;
vec4 tmp8;
vec4 tmp6;
vec4 tmp7;
vec4 tmp9;
vec4 tmp10;
vec4 tmp11;
vec4 tmp12;
vec4 tmp13;
vec4 tmp15;
vec4 tmp16;
vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
vec4 dst_reg1 = vec4(0.0);
vec4 dst_reg3 = vec4(0.0);
vec4 dst_reg5 = vec4(0.0);
vec4 dst_reg6 = vec4(0.0);
vec4 dst_reg10 = vec4(0.0);
vec4 dst_reg9 = vec4(0.0);
vec4 dst_reg8 = vec4(0.0);
vec4 dst_reg7 = vec4(0.0);
layout (location = 0) in vec4 in_pos;
layout (location = 2) in vec4 in_normal;
layout (location = 3) in vec4 in_diff_color;
layout (location = 8) in vec4 in_tc0;
layout (location = 9) in vec4 in_tc1;
layout (location = 10) in vec4 in_tc2;
layout (location = 11) in vec4 in_tc3;
uniform vec4 vc[468];
ivec4 a0 = ivec4(0);
out vec4 diff_color;
out vec4 front_diff_color;
out vec4 fogc;
out vec4 tc0;
out vec4 tc1;
out vec4 tc2;
out vec4 tc3;
out vec4 tc9;

void func0();

void main()
{
	func0();
	gl_Position = dst_reg0;
	diff_color = dst_reg1;
	front_diff_color = dst_reg3;
	fogc = vec4(dst_reg5.x);
	gl_ClipDistance[0] = dst_reg5.y;
	gl_ClipDistance[1] = dst_reg5.z;
	gl_ClipDistance[2] = dst_reg5.w;
	gl_PointSize = dst_reg6.x;
	gl_ClipDistance[3] = dst_reg6.y;
	gl_ClipDistance[4] = dst_reg6.z;
	gl_ClipDistance[5] = dst_reg6.w;
	tc0 = dst_reg7;
	tc1 = dst_reg8;
	tc2 = dst_reg9;
	tc3 = dst_reg10;
	tc9 = dst_reg6;
	gl_Position = gl_Position * scaleOffsetMat;
}

void func0()
{
	tmp0.w = vec4(dot(in_pos, vc[263])).w;
	tmp0.z = vec4(dot(in_pos, vc[262])).z;
	tmp0.y = vec4(dot(in_pos, vc[261])).y;
	tmp0.x = vec4(dot(in_pos, vc[260])).x;
	tmp3.w = vec4(dot(in_pos, vc[259])).w;
	tmp3.y = vec4(dot(in_pos, vc[257])).y;
	tmp3.x = vec4(dot(in_pos, vc[256])).x;
	cc0.xy = vc[467].wxww.xy;
	tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
	tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
	tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
	tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
	tmp2 = clamp(in_diff_color, 0.0, 1.0);
	tmp1 = tmp2;
	tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
	tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
	tmp3.z = tmp5.yyyy.z;
	tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
	tmp14.w = abs(tmp5.xxxx).w;
	tmp14.xyz = tmp4.xyzx.xyz;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
	if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
	{
		tmp1.xyz = vc[463].xxxx.xyz;
		tmp1.w = vc[463].xxxx.w;
		tmp4 = in_diff_color;
		cc0.x = vc[467].zzzz.x;
		tmp5.xyz = in_diff_color.xyzx.xyz;
		tmp2.x = vc[462].xxxx.x;
		cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
		if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
		{
			do
			{
				tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
				a0.x = ivec4(tmp2.xxxx).x;
				tmp8.z = vc[405].xxxx.z;
				tmp2.xyz = vc[463].xxxx.xyz;
				tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
				tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
				tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
				tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
				tmp2.w = vc[463].xxxx.w;
				cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
				cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
				cc0.x = vc[411 + a0.x].xxxx.x;
				tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
				tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
				tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
				tmp6.w = -tmp6.wwww.w;
				if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
				tmp2.w = tmp6.wwww.w;
				tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
				tmp6.w = log2(tmp6.wwww).w;
				tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
				cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
				cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
				tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
				tmp5.w = (1.0 / tmp5.wwww).w;
				tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
				tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
				cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
				tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
				tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
				tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
				tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
				tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
				tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
				if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
				tmp5.w = (1.0 / tmp2.xxxx).w;
				tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
				tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
				tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
				tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.w = (tmp2.wwww * tmp5.wwww).w;
				tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
			} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
		}
		cc0.x = vc[467].yyyy.x;
		tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
		tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
		tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
		tmp1.w = tmp4.wwww.w;
		tmp2 = clamp(tmp1, 0.0, 1.0);
		tmp1 = tmp2;
		if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
		{
			tmp2.x = vc[462].xxxx.x;
			cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
			tmp2.xyz = vc[463].xxxx.xyz;
			if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
			{
			tmp2.w = vc[463].xxxx.w;
				do
				{
					tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
					a0.x = ivec4(tmp5.wwww).x;
					tmp9.z = vc[405].xxxx.z;
					tmp6.xyz = vc[463].xxxx.xyz;
					tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
					tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
					tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
					tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
					tmp5.w = vc[463].xxxx.w;
					cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
					cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
					cc0.x = vc[411 + a0.x].xxxx.x;
					tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
					tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
					tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
					tmp8.y = -tmp7.wwww.y;
					if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
					tmp7.w = log2(tmp8.yyyy).w;
					tmp5.w = tmp8.yyyy.w;
					tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
					tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
					cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
					cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
					tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
					tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
					tmp6.w = (1.0 / tmp6.wwww).w;
					tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
					cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
					tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
					tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
					tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
					tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
					tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
					tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
					if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
					tmp6.w = (1.0 / tmp6.xxxx).w;
					tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
					tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
					tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
					tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp5.w = (tmp5.wwww * tmp6.wwww).w;
					tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
				} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
			}
			tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
			tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
			tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
			tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
		}
	}
	tmp4.x = vc[463].xxxx.x;
	tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
	tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
	tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp4 = in_tc0;
		tmp9.x = vc[400].xxxx.x;
		tmp7.zw = vc[463].xxxz.zw;
		tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp5 = (tmp3.yyyy * vc[268]);
		tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7.xy = vc[400].yzyy.xy;
		tmp4 = in_tc0;
		tmp6 = (in_pos.yyyy * vc[268]);
		tmp8.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[401], tmp8.zzzz));
		tmp6 = (in_pos.xxxx * vc[267] + tmp6);
		tmp6 = (in_pos.zzzz * vc[269] + tmp6);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
		cc0 = vec4(equal(vc[401], tmp7.xxxx));
		tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
		tmp5 = (tmp3.xxxx * vc[267] + tmp5);
		tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
		tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
		tmp5 = (tmp3.zzzz * vc[269] + tmp5);
		tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
		tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
		tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
		tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
		cc0 = vec4(equal(vc[401], tmp7.yyyy));
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
		tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
		tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
		tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
		cc0 = vec4(equal(vc[401], tmp9.xxxx));
		tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
		tmp5.w = vc[463].zzzz.w;
		tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
		cc0 = vec4(equal(vc[401], tmp8.wwww));
		tmp5.xyz = tmp14.xyzx.xyz;
		tmp5.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
	}
	tmp5.x = vc[463].xxxx.x;
	tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
	tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
	tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
	tmp5 = tmp4;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp6 = in_tc1;
		tmp9.zw = vc[463].xxxz.zw;
		tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7 = (tmp3.yyyy * vc[276]);
		tmp10.xyz = vc[400].xyzx.xyz;
		tmp6 = in_tc1;
		tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp8 = (in_pos.yyyy * vc[276]);
		tmp11.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[399], tmp11.zzzz));
		tmp8 = (in_pos.xxxx * vc[275] + tmp8);
		tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
		tmp8 = (in_pos.zzzz * vc[277] + tmp8);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
		cc0 = vec4(equal(vc[399], tmp10.yyyy));
		tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
		tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
		tmp7 = (tmp3.xxxx * vc[275] + tmp7);
		tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
		tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
		tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
		tmp7 = (tmp3.zzzz * vc[277] + tmp7);
		tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
		tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[399], tmp10.zzzz));
		tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
		tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
		tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
		tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
		cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
		cc0 = vec4(equal(vc[399], tmp10.xxxx));
		tmp7.w = vc[463].zzzz.w;
		tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
		cc0 = vec4(equal(vc[399], tmp11.wwww));
		tmp7.xyz = tmp14.xyzx.xyz;
		tmp7.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
	}
	tmp7.x = vc[463].xxxx.x;
	tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
	tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
	tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
	tmp7 = tmp6;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp8 = in_tc2;
		tmp11.zw = vc[463].xxxz.zw;
		tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp9 = (tmp3.yyyy * vc[284]);
		tmp12.xyz = vc[400].xyzx.xyz;
		tmp8 = in_tc2;
		tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp10 = (in_pos.yyyy * vc[284]);
		tmp13.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[398], tmp13.zzzz));
		tmp10 = (in_pos.xxxx * vc[283] + tmp10);
		tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
		tmp10 = (in_pos.zzzz * vc[285] + tmp10);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
		cc0 = vec4(equal(vc[398], tmp12.yyyy));
		tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
		tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
		tmp9 = (tmp3.xxxx * vc[283] + tmp9);
		tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
		tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
		tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
		tmp9 = (tmp3.zzzz * vc[285] + tmp9);
		tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
		tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[398], tmp12.zzzz));
		tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
		tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
		tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
		tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
		cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
		cc0 = vec4(equal(vc[398], tmp12.xxxx));
		tmp9.w = vc[463].zzzz.w;
		tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
		cc0 = vec4(equal(vc[398], tmp13.wwww));
		tmp9.xyz = tmp14.xyzx.xyz;
		tmp9.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
	}
	tmp9.x = vc[463].xxxx.x;
	tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
	tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
	tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
	tmp9 = tmp8;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp10 = in_tc3;
		tmp13.zw = vc[463].xxxz.zw;
		tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp11 = (tmp3.yyyy * vc[292]);
		tmp15.xyz = vc[400].xyzx.xyz;
		tmp10 = in_tc3;
		tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp12 = (in_pos.yyyy * vc[292]);
		tmp16.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[397], tmp16.zzzz));
		tmp12 = (in_pos.xxxx * vc[291] + tmp12);
		tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
		tmp12 = (in_pos.zzzz * vc[293] + tmp12);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
		cc0 = vec4(equal(vc[397], tmp15.yyyy));
		tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
		tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
		tmp11 = (tmp3.xxxx * vc[291] + tmp11);
		tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
		tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
		tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
		tmp11 = (tmp3.zzzz * vc[293] + tmp11);
		tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
		tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[397], tmp15.zzzz));
		tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
		tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
		tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
		tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
		cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
		cc0 = vec4(equal(vc[397], tmp15.xxxx));
		tmp11.w = vc[463].zzzz.w;
		tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
		cc0 = vec4(equal(vc[397], tmp16.wwww));
		tmp11.xyz = tmp14.xyzx.xyz;
		tmp11.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
	}
	dst_reg0 = tmp0;
	dst_reg1 = tmp1;
	dst_reg3 = tmp2;
	dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
	dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
	dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
	dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
	dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
	dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
	dst_reg5.x = tmp14.wwww.x;
	tmp0.w = vec4(dot(tmp10, vc[298])).w;
	tmp0.z = vec4(dot(tmp10, vc[297])).z;
	tmp0.y = vec4(dot(tmp10, vc[296])).y;
	tmp0.x = vec4(dot(tmp10, vc[295])).x;
	dst_reg10 = tmp10;
	dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
	dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
	dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
	dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
	dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
	dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
	dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
	cc0.x = vc[396].xxxx.x;
	dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
	dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
	dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
	dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
	dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
}

RSX: ! {RSXThread} *** fp shader = 
#version 330

vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
in vec4 diff_color;
in vec4 tc0;
uniform sampler2D tex0;
layout (location = 0) out vec4 ocol0;
layout (location = 2) out vec4 ocol2;
layout (location = 3) out vec4 ocol3;

void main()
{
	h2 = diff_color;
	r0 = h2;
	r2 = h2;
	r3 = h2;
	r0 = texture(tex0, tc0.xy);
	ocol0 = r0;
	ocol2 = r2;
	ocol3 = r3;
}

RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: ! {RSXThread} Add program (3):
RSX: ! {RSXThread} *** prog id = 9
RSX: ! {RSXThread} *** vp id = 2
RSX: ! {RSXThread} *** fp id = 7
RSX: ! {RSXThread} *** vp data size = 5680
RSX: ! {RSXThread} *** fp data size = 144
RSX: ! {RSXThread} *** vp shader = 
#version 330

uniform mat4 scaleOffsetMat = mat4(1.0);
vec4 tmp0;
vec4 tmp3;
vec4 cc0 = vec4(0.0);
vec4 tmp5;
vec4 tmp4;
vec4 tmp2;
vec4 tmp1;
vec4 tmp14;
vec4 tmp8;
vec4 tmp6;
vec4 tmp7;
vec4 tmp9;
vec4 tmp10;
vec4 tmp11;
vec4 tmp12;
vec4 tmp13;
vec4 tmp15;
vec4 tmp16;
vec4 dst_reg0 = vec4(0.0f, 0.0f, 0.0f, 1.0f);
vec4 dst_reg1 = vec4(0.0);
vec4 dst_reg3 = vec4(0.0);
vec4 dst_reg5 = vec4(0.0);
vec4 dst_reg6 = vec4(0.0);
vec4 dst_reg10 = vec4(0.0);
vec4 dst_reg9 = vec4(0.0);
vec4 dst_reg8 = vec4(0.0);
vec4 dst_reg7 = vec4(0.0);
layout (location = 0) in vec4 in_pos;
layout (location = 2) in vec4 in_normal;
layout (location = 3) in vec4 in_diff_color;
layout (location = 8) in vec4 in_tc0;
layout (location = 9) in vec4 in_tc1;
layout (location = 10) in vec4 in_tc2;
layout (location = 11) in vec4 in_tc3;
uniform vec4 vc[468];
ivec4 a0 = ivec4(0);
out vec4 diff_color;
out vec4 front_diff_color;
out vec4 fogc;
out vec4 tc0;
out vec4 tc1;
out vec4 tc2;
out vec4 tc3;
out vec4 tc9;

void func0();

void main()
{
	func0();
	gl_Position = dst_reg0;
	diff_color = dst_reg1;
	front_diff_color = dst_reg3;
	fogc = vec4(dst_reg5.x);
	gl_ClipDistance[0] = dst_reg5.y;
	gl_ClipDistance[1] = dst_reg5.z;
	gl_ClipDistance[2] = dst_reg5.w;
	gl_PointSize = dst_reg6.x;
	gl_ClipDistance[3] = dst_reg6.y;
	gl_ClipDistance[4] = dst_reg6.z;
	gl_ClipDistance[5] = dst_reg6.w;
	tc0 = dst_reg7;
	tc1 = dst_reg8;
	tc2 = dst_reg9;
	tc3 = dst_reg10;
	tc9 = dst_reg6;
	gl_Position = gl_Position * scaleOffsetMat;
}

void func0()
{
	tmp0.w = vec4(dot(in_pos, vc[263])).w;
	tmp0.z = vec4(dot(in_pos, vc[262])).z;
	tmp0.y = vec4(dot(in_pos, vc[261])).y;
	tmp0.x = vec4(dot(in_pos, vc[260])).x;
	tmp3.w = vec4(dot(in_pos, vc[259])).w;
	tmp3.y = vec4(dot(in_pos, vc[257])).y;
	tmp3.x = vec4(dot(in_pos, vc[256])).x;
	cc0.xy = vc[467].wxww.xy;
	tmp5.xy = vec4(dot(in_pos, vc[258])).xy;
	tmp4.z = vec4(dot(in_normal.xyzx.xyz, vc[266].xyzx.xyz)).z;
	tmp4.y = vec4(dot(in_normal.xyzx.xyz, vc[265].xyzx.xyz)).y;
	tmp4.x = vec4(dot(in_normal.xyzx.xyz, vc[264].xyzx.xyz)).x;
	tmp2 = clamp(in_diff_color, 0.0, 1.0);
	tmp1 = tmp2;
	tmp4.xyz = (tmp4.xyzx * vc[466].xxxx).xyz;
	tmp4.w = vec4(dot(tmp4.xyzx.xyz, tmp4.xyzx.xyz)).w;
	tmp3.z = tmp5.yyyy.z;
	tmp4.w = inversesqrt(abs(tmp4.wwww)).w;
	tmp14.w = abs(tmp5.xxxx).w;
	tmp14.xyz = tmp4.xyzx.xyz;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) tmp14.xyz = (tmp4.wwww * tmp4.xyzx).xyz;
	if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
	{
		tmp1.xyz = vc[463].xxxx.xyz;
		tmp1.w = vc[463].xxxx.w;
		tmp4 = in_diff_color;
		cc0.x = vc[467].zzzz.x;
		tmp5.xyz = in_diff_color.xyzx.xyz;
		tmp2.x = vc[462].xxxx.x;
		cc0.y = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).y;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp5.xyz = vc[465].xyzx.xyz;
		if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) tmp4 = vc[464];
		if(!any(equal(cc0.yyyy, vec4(0.0).yyyy)))
		{
			do
			{
				tmp2.x = (tmp1.wwww * vc[463].yyyy).x;
				a0.x = ivec4(tmp2.xxxx).x;
				tmp8.z = vc[405].xxxx.z;
				tmp2.xyz = vc[463].xxxx.xyz;
				tmp6.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
				tmp6.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp6.xyzx).xyz;
				tmp1.w = (tmp1.wwww + vc[463].zzzz).w;
				tmp5.w = vec4(dot(tmp6.xyzx.xyz, tmp6.xyzx.xyz)).w;
				tmp2.w = vc[463].xxxx.w;
				cc0.w = tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
				cc0.z = vec4(lessThan(tmp1.wwww, vc[462].xxxx)).z;
				cc0.x = vc[411 + a0.x].xxxx.x;
				tmp6.xyz = (tmp5.wwww * tmp6.xyzx).xyz;
				tmp6.w = vec4(dot(tmp6.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
				tmp7.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp2.wwww)).x;
				tmp6.w = -tmp6.wwww.w;
				if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp6.w = vc[463].zzzz.w;
				tmp2.w = tmp6.wwww.w;
				tmp7.y = vec4(greaterThan(tmp6.wwww, vc[411 + a0.x].xxxx)).y;
				tmp6.w = log2(tmp6.wwww).w;
				tmp7.z = vec4(equal(tmp7.yyyy, vc[463].xxxx)).z;
				cc0.y = (tmp7.xxxx * tmp7.yyyy).y;
				cc0.x = (tmp7.xxxx * tmp7.zzzz).x;
				tmp7.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
				tmp5.w = (1.0 / tmp5.wwww).w;
				tmp6.w = (vc[411 + a0.x].yyyy * tmp6.wwww).w;
				tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.w = exp2(tmp6.wwww).w;
				cc0.y = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).y;
				tmp8.x = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).x;
				tmp6.y = inversesqrt(abs(tmp7.wwww)).y;
				tmp6.x = (vc[412 + a0.x].zzzz * tmp5.wwww + vc[412 + a0.x].yyyy).x;
				if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp2.xyz = (tmp6.yyyy * tmp7.xyzx).xyz;
				tmp8.y = vec4(dot(tmp14.xyzx.xyz, tmp2.xyzx.xyz)).y;
				tmp2.x = (tmp6.xxxx * tmp5.wwww + vc[412 + a0.x].xxxx).x;
				tmp2.yz = vec4(1.0, tmp8.xyxz.x, (tmp8.xyxz.x > 0 ? exp2(tmp8.xyxz.w * log2(tmp8.xyxz.y)) : 0.0), 1.0).yz;
				if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp2.w = vc[463].xxxx.w;
				tmp5.w = (1.0 / tmp2.xxxx).w;
				tmp6.xyz = (tmp2.yyyy * tmp4.xyzx).xyz;
				tmp2.xyz = (tmp2.zzzz * vc[404].xyzx).xyz;
				tmp6.xyz = (tmp6.xyzx * vc[408 + a0.x].xyzx).xyz;
				tmp6.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.xyz = (tmp2.xyzx * vc[409 + a0.x].xyzx + tmp6.xyzx).xyz;
				tmp2.w = (tmp2.wwww * tmp5.wwww).w;
				tmp1.xyz = (tmp2.wwww * tmp2.xyzx + tmp1.xyzx).xyz;
			} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
		}
		cc0.x = vc[467].yyyy.x;
		tmp2.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
		tmp2.xyz = (tmp2.xyzx + vc[402].xyzx).xyz;
		tmp1.xyz = (tmp1.xyzx + tmp2.xyzx).xyz;
		tmp1.w = tmp4.wwww.w;
		tmp2 = clamp(tmp1, 0.0, 1.0);
		tmp1 = tmp2;
		if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
		{
			tmp2.x = vc[462].xxxx.x;
			cc0.x = vec4(lessThan(vc[463].xxxx, tmp2.xxxx)).x;
			tmp2.xyz = vc[463].xxxx.xyz;
			if(!any(equal(cc0.xxxx, vec4(0.0).xxxx)))
			{
			tmp2.w = vc[463].xxxx.w;
				do
				{
					tmp5.w = (tmp2.wwww * vc[463].yyyy).w;
					a0.x = ivec4(tmp5.wwww).x;
					tmp9.z = vc[405].xxxx.z;
					tmp6.xyz = vc[463].xxxx.xyz;
					tmp7.xyz = (tmp3.xyzx * vc[406 + a0.x].wwww).xyz;
					tmp7.xyz = (vc[406 + a0.x].xyzx * tmp3.wwww + -tmp7.xyzx).xyz;
					tmp2.w = (tmp2.wwww + vc[463].zzzz).w;
					tmp6.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
					tmp5.w = vc[463].xxxx.w;
					cc0.w = tmp6.w = inversesqrt(abs(tmp6.wwww)).w;
					cc0.z = vec4(lessThan(tmp2.wwww, vc[462].xxxx)).z;
					cc0.x = vc[411 + a0.x].xxxx.x;
					tmp7.xyz = (tmp6.wwww * tmp7.xyzx).xyz;
					tmp7.w = vec4(dot(tmp7.xyzx.xyz, vc[410 + a0.x].xyzx.xyz)).w;
					tmp8.x = vec4(greaterThanEqual(vc[411 + a0.x].xxxx, tmp5.wwww)).x;
					tmp8.y = -tmp7.wwww.y;
					if(any(lessThan(cc0.xxxx, vec4(0.0).xxxx))) tmp8.y = vc[463].zzzz.y;
					tmp7.w = log2(tmp8.yyyy).w;
					tmp5.w = tmp8.yyyy.w;
					tmp8.y = vec4(greaterThan(tmp8.yyyy, vc[411 + a0.x].xxxx)).y;
					tmp8.z = vec4(equal(tmp8.yyyy, vc[463].xxxx)).z;
					cc0.y = (tmp8.xxxx * tmp8.yyyy).y;
					cc0.x = (tmp8.xxxx * tmp8.zzzz).x;
					tmp8.xyz = (tmp7.xyzx + vc[463].xxzx).xyz;
					tmp7.w = (vc[411 + a0.x].yyyy * tmp7.wwww).w;
					tmp6.w = (1.0 / tmp6.wwww).w;
					tmp8.w = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).w;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp5.w = exp2(tmp7.wwww).w;
					cc0.y = vec4(dot(tmp8.xyzx.xyz, tmp8.xyzx.xyz)).y;
					tmp9.x = vec4(dot(-tmp14.xyzx.xyz, tmp7.xyzx.xyz)).x;
					tmp7.y = inversesqrt(abs(tmp8.wwww)).y;
					tmp7.x = (vc[412 + a0.x].zzzz * tmp6.wwww + vc[412 + a0.x].yyyy).x;
					if(any(greaterThan(cc0.yyyy, vec4(0.0).yyyy))) tmp6.xyz = (tmp7.yyyy * tmp8.xyzx).xyz;
					tmp9.y = vec4(dot(-tmp14.xyzx.xyz, tmp6.xyzx.xyz)).y;
					tmp6.x = (tmp7.xxxx * tmp6.wwww + vc[412 + a0.x].xxxx).x;
					tmp7.yz = vec4(1.0, tmp9.xyxz.x, (tmp9.xyxz.x > 0 ? exp2(tmp9.xyxz.w * log2(tmp9.xyxz.y)) : 0.0), 1.0).yz;
					if(any(greaterThan(cc0.xxxx, vec4(0.0).xxxx))) tmp5.w = vc[463].xxxx.w;
					tmp6.w = (1.0 / tmp6.xxxx).w;
					tmp6.xyz = (tmp7.zzzz * vc[404].xyzx).xyz;
					tmp7.xyz = (tmp7.yyyy * tmp4.xyzx).xyz;
					tmp7.xyz = (tmp7.xyzx * vc[408 + a0.x].xyzx).xyz;
					tmp7.xyz = (tmp5.xyzx * vc[407 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp6.xyz = (tmp6.xyzx * vc[409 + a0.x].xyzx + tmp7.xyzx).xyz;
					tmp5.w = (tmp5.wwww * tmp6.wwww).w;
					tmp2.xyz = (tmp5.wwww * tmp6.xyzx + tmp2.xyzx).xyz;
				} while (any(greaterThan(cc0.zzzz, vec4(0.0).zzzz)));
			}
			tmp2.w = clamp(tmp4.wwww.w, 0.0, 1.0);
			tmp4.xyz = (tmp5.xyzx * vc[403].xyzx).xyz;
			tmp4.xyz = (tmp4.xyzx + vc[402].xyzx).xyz;
			tmp2.xyz = clamp((tmp2.xyzx + tmp4.xyzx).xyz, 0.0, 1.0);
		}
	}
	tmp4.x = vc[463].xxxx.x;
	tmp4 = vec4(notEqual(vc[401], tmp4.xxxx));
	tmp4.x = clamp((tmp4.xxxx + tmp4.yyyy).x, 0.0, 1.0);
	tmp4.x = clamp((tmp4.xxxx + tmp4.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp4.xxxx + tmp4.wwww).x, 0.0, 1.0);
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp4 = in_tc0;
		tmp9.x = vc[400].xxxx.x;
		tmp7.zw = vc[463].xxxz.zw;
		tmp9.y = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp5 = (tmp3.yyyy * vc[268]);
		tmp8.x = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7.xy = vc[400].yzyy.xy;
		tmp4 = in_tc0;
		tmp6 = (in_pos.yyyy * vc[268]);
		tmp8.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[401], tmp8.zzzz));
		tmp6 = (in_pos.xxxx * vc[267] + tmp6);
		tmp6 = (in_pos.zzzz * vc[269] + tmp6);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (in_pos.wwww * vc[270] + tmp6);
		cc0 = vec4(equal(vc[401], tmp7.xxxx));
		tmp6.x = inversesqrt(abs(tmp8.xxxx)).x;
		tmp5 = (tmp3.xxxx * vc[267] + tmp5);
		tmp6.xyz = (tmp6.xxxx * tmp3.xyzx).xyz;
		tmp6.w = vec4(dot(tmp14.xyzx.xyz, tmp6.xyzx.xyz)).w;
		tmp5 = (tmp3.zzzz * vc[269] + tmp5);
		tmp8.xyz = (tmp14.xyzx * tmp6.wwww).xyz;
		tmp8.xyz = (tmp8.xyzx * vc[400].yyyy).xyz;
		tmp6.xyz = (tmp6.xyzx + -tmp8.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = (tmp3.wwww * vc[270] + tmp5);
		tmp5.xyz = (tmp6.xyzx + vc[463].xxzx).xyz;
		cc0 = vec4(equal(vc[401], tmp7.yyyy));
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		tmp5.xyz = (tmp14.xyzx * tmp9.yyyy).xyz;
		tmp5.w = inversesqrt(abs(tmp5.wwww)).w;
		tmp5.xyz = (-tmp5.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp6.xy = (tmp5.wwww * tmp6.xyxx).xy;
		tmp7.xy = (tmp6.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp5.w = vec4(dot(tmp5.xyzx.xyz, tmp5.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp7;
		cc0 = vec4(equal(vc[401], tmp9.xxxx));
		tmp6.x = inversesqrt(abs(tmp5.wwww)).x;
		tmp5.w = vc[463].zzzz.w;
		tmp5.xyz = (tmp6.xxxx * tmp5.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
		cc0 = vec4(equal(vc[401], tmp8.wwww));
		tmp5.xyz = tmp14.xyzx.xyz;
		tmp5.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp4 = tmp5;
	}
	tmp5.x = vc[463].xxxx.x;
	tmp5 = vec4(notEqual(vc[399], tmp5.xxxx));
	tmp5.x = clamp((tmp5.xxxx + tmp5.yyyy).x, 0.0, 1.0);
	tmp5.x = clamp((tmp5.xxxx + tmp5.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp5.xxxx + tmp5.wwww).x, 0.0, 1.0);
	tmp5 = tmp4;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp6 = in_tc1;
		tmp9.zw = vc[463].xxxz.zw;
		tmp9.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp7 = (tmp3.yyyy * vc[276]);
		tmp10.xyz = vc[400].xyzx.xyz;
		tmp6 = in_tc1;
		tmp9.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp8 = (in_pos.yyyy * vc[276]);
		tmp11.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[399], tmp11.zzzz));
		tmp8 = (in_pos.xxxx * vc[275] + tmp8);
		tmp9.y = inversesqrt(abs(tmp9.yyyy)).y;
		tmp8 = (in_pos.zzzz * vc[277] + tmp8);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (in_pos.wwww * vc[278] + tmp8);
		cc0 = vec4(equal(vc[399], tmp10.yyyy));
		tmp8.xyz = (tmp9.yyyy * tmp3.xyzx).xyz;
		tmp8.w = vec4(dot(tmp14.xyzx.xyz, tmp8.xyzx.xyz)).w;
		tmp7 = (tmp3.xxxx * vc[275] + tmp7);
		tmp11.xyz = (tmp14.xyzx * tmp8.wwww).xyz;
		tmp11.xyz = (tmp11.xyzx * vc[400].yyyy).xyz;
		tmp8.xyz = (tmp8.xyzx + -tmp11.xyzx).xyz;
		tmp7 = (tmp3.zzzz * vc[277] + tmp7);
		tmp11.xyz = (tmp8.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = (tmp3.wwww * vc[278] + tmp7);
		tmp7.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[399], tmp10.zzzz));
		tmp7.xyz = (tmp14.xyzx * tmp9.xxxx).xyz;
		tmp7.w = inversesqrt(abs(tmp7.wwww)).w;
		tmp7.xyz = (-tmp7.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp8.xy = (tmp7.wwww * tmp8.xyxx).xy;
		tmp9.xy = (tmp8.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp7.w = vec4(dot(tmp7.xyzx.xyz, tmp7.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp9;
		cc0.x = tmp8.x = inversesqrt(abs(tmp7.wwww)).x;
		cc0 = vec4(equal(vc[399], tmp10.xxxx));
		tmp7.w = vc[463].zzzz.w;
		tmp7.xyz = (tmp8.xxxx * tmp7.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
		cc0 = vec4(equal(vc[399], tmp11.wwww));
		tmp7.xyz = tmp14.xyzx.xyz;
		tmp7.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp6 = tmp7;
	}
	tmp7.x = vc[463].xxxx.x;
	tmp7 = vec4(notEqual(vc[398], tmp7.xxxx));
	tmp7.x = clamp((tmp7.xxxx + tmp7.yyyy).x, 0.0, 1.0);
	tmp7.x = clamp((tmp7.xxxx + tmp7.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp7.xxxx + tmp7.wwww).x, 0.0, 1.0);
	tmp7 = tmp6;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp8 = in_tc2;
		tmp11.zw = vc[463].xxxz.zw;
		tmp11.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp9 = (tmp3.yyyy * vc[284]);
		tmp12.xyz = vc[400].xyzx.xyz;
		tmp8 = in_tc2;
		tmp11.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp10 = (in_pos.yyyy * vc[284]);
		tmp13.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[398], tmp13.zzzz));
		tmp10 = (in_pos.xxxx * vc[283] + tmp10);
		tmp11.y = inversesqrt(abs(tmp11.yyyy)).y;
		tmp10 = (in_pos.zzzz * vc[285] + tmp10);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (in_pos.wwww * vc[286] + tmp10);
		cc0 = vec4(equal(vc[398], tmp12.yyyy));
		tmp10.xyz = (tmp11.yyyy * tmp3.xyzx).xyz;
		tmp10.w = vec4(dot(tmp14.xyzx.xyz, tmp10.xyzx.xyz)).w;
		tmp9 = (tmp3.xxxx * vc[283] + tmp9);
		tmp13.xyz = (tmp14.xyzx * tmp10.wwww).xyz;
		tmp13.xyz = (tmp13.xyzx * vc[400].yyyy).xyz;
		tmp10.xyz = (tmp10.xyzx + -tmp13.xyzx).xyz;
		tmp9 = (tmp3.zzzz * vc[285] + tmp9);
		tmp13.xyz = (tmp10.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = (tmp3.wwww * vc[286] + tmp9);
		tmp9.w = vec4(dot(tmp13.xyzx.xyz, tmp13.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[398], tmp12.zzzz));
		tmp9.xyz = (tmp14.xyzx * tmp11.xxxx).xyz;
		tmp9.w = inversesqrt(abs(tmp9.wwww)).w;
		tmp9.xyz = (-tmp9.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp10.xy = (tmp9.wwww * tmp10.xyxx).xy;
		tmp11.xy = (tmp10.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp9.w = vec4(dot(tmp9.xyzx.xyz, tmp9.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp11;
		cc0.x = tmp10.x = inversesqrt(abs(tmp9.wwww)).x;
		cc0 = vec4(equal(vc[398], tmp12.xxxx));
		tmp9.w = vc[463].zzzz.w;
		tmp9.xyz = (tmp10.xxxx * tmp9.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
		cc0 = vec4(equal(vc[398], tmp13.wwww));
		tmp9.xyz = tmp14.xyzx.xyz;
		tmp9.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp8 = tmp9;
	}
	tmp9.x = vc[463].xxxx.x;
	tmp9 = vec4(notEqual(vc[397], tmp9.xxxx));
	tmp9.x = clamp((tmp9.xxxx + tmp9.yyyy).x, 0.0, 1.0);
	tmp9.x = clamp((tmp9.xxxx + tmp9.zzzz).x, 0.0, 1.0);
	cc0.x = clamp((tmp9.xxxx + tmp9.wwww).x, 0.0, 1.0);
	tmp9 = tmp8;
	if(!any(lessThanEqual(cc0.xxxx, vec4(0.0).xxxx)))
	{
	tmp10 = in_tc3;
		tmp13.zw = vc[463].xxxz.zw;
		tmp13.x = vec4(dot(tmp14.xyzx.xyz, tmp3.xyzx.xyz)).x;
		tmp11 = (tmp3.yyyy * vc[292]);
		tmp15.xyz = vc[400].xyzx.xyz;
		tmp10 = in_tc3;
		tmp13.y = vec4(dot(tmp3.xyzx.xyz, tmp3.xyzx.xyz)).y;
		tmp12 = (in_pos.yyyy * vc[292]);
		tmp16.zw = vc[463].zzzw.zw;
		cc0 = vec4(equal(vc[397], tmp16.zzzz));
		tmp12 = (in_pos.xxxx * vc[291] + tmp12);
		tmp13.y = inversesqrt(abs(tmp13.yyyy)).y;
		tmp12 = (in_pos.zzzz * vc[293] + tmp12);
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (in_pos.wwww * vc[294] + tmp12);
		cc0 = vec4(equal(vc[397], tmp15.yyyy));
		tmp12.xyz = (tmp13.yyyy * tmp3.xyzx).xyz;
		tmp12.w = vec4(dot(tmp14.xyzx.xyz, tmp12.xyzx.xyz)).w;
		tmp11 = (tmp3.xxxx * vc[291] + tmp11);
		tmp16.xyz = (tmp14.xyzx * tmp12.wwww).xyz;
		tmp16.xyz = (tmp16.xyzx * vc[400].yyyy).xyz;
		tmp12.xyz = (tmp12.xyzx + -tmp16.xyzx).xyz;
		tmp11 = (tmp3.zzzz * vc[293] + tmp11);
		tmp16.xyz = (tmp12.xyzx + vc[463].xxzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = (tmp3.wwww * vc[294] + tmp11);
		tmp11.w = vec4(dot(tmp16.xyzx.xyz, tmp16.xyzx.xyz)).w;
		cc0 = vec4(equal(vc[397], tmp15.zzzz));
		tmp11.xyz = (tmp14.xyzx * tmp13.xxxx).xyz;
		tmp11.w = inversesqrt(abs(tmp11.wwww)).w;
		tmp11.xyz = (-tmp11.xyzx * vc[400].yyyy + tmp3.xyzx).xyz;
		tmp12.xy = (tmp11.wwww * tmp12.xyxx).xy;
		tmp13.xy = (tmp12.xyxx * vc[400].wwww + vc[400].wwww).xy;
		tmp11.w = vec4(dot(tmp11.xyzx.xyz, tmp11.xyzx.xyz)).w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp13;
		cc0.x = tmp12.x = inversesqrt(abs(tmp11.wwww)).x;
		cc0 = vec4(equal(vc[397], tmp15.xxxx));
		tmp11.w = vc[463].zzzz.w;
		tmp11.xyz = (tmp12.xxxx * tmp11.xyzx).xyz;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
		cc0 = vec4(equal(vc[397], tmp16.wwww));
		tmp11.xyz = tmp14.xyzx.xyz;
		tmp11.w = vc[463].zzzz.w;
		if(any(greaterThan(cc0, vec4(0.0)))) tmp10 = tmp11;
	}
	dst_reg0 = tmp0;
	dst_reg1 = tmp1;
	dst_reg3 = tmp2;
	dst_reg5.y = vec4(dot(tmp3, vc[395])).y;
	dst_reg5.z = vec4(dot(tmp3, vc[394])).z;
	dst_reg5.w = vec4(dot(tmp3, vc[393])).w;
	dst_reg6.y = vec4(dot(tmp3, vc[392])).y;
	dst_reg6.z = vec4(dot(tmp3, vc[391])).z;
	dst_reg6.w = vec4(dot(tmp3, vc[390])).w;
	dst_reg5.x = tmp14.wwww.x;
	tmp0.w = vec4(dot(tmp10, vc[298])).w;
	tmp0.z = vec4(dot(tmp10, vc[297])).z;
	tmp0.y = vec4(dot(tmp10, vc[296])).y;
	tmp0.x = vec4(dot(tmp10, vc[295])).x;
	dst_reg10 = tmp10;
	dst_reg9.w = vec4(dot(tmp8, vc[290])).w;
	dst_reg9.z = vec4(dot(tmp8, vc[289])).z;
	dst_reg9.y = vec4(dot(tmp8, vc[288])).y;
	dst_reg9.x = vec4(dot(tmp8, vc[287])).x;
	dst_reg8.w = vec4(dot(tmp6, vc[282])).w;
	dst_reg8.z = vec4(dot(tmp6, vc[281])).z;
	dst_reg8.y = vec4(dot(tmp6, vc[280])).y;
	cc0.x = vc[396].xxxx.x;
	dst_reg7.w = vec4(dot(tmp4, vc[274])).w;
	dst_reg7.z = vec4(dot(tmp4, vc[273])).z;
	dst_reg7.y = vec4(dot(tmp4, vc[272])).y;
	dst_reg7.x = vec4(dot(tmp4, vc[271])).x;
	dst_reg8.x = vec4(dot(tmp6, vc[279])).x;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg7 = tmp5;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg8 = tmp7;
	if(any(equal(cc0.xxxx, vec4(0.0).xxxx))) dst_reg9 = tmp9;
	if(any(notEqual(cc0.xxxx, vec4(0.0).xxxx))) dst_reg10 = tmp0;
}

RSX: ! {RSXThread} *** fp shader = 
#version 330

vec4 h2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r0 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r2 = vec4(0.0, 0.0, 0.0, 0.0);
vec4 r3 = vec4(0.0, 0.0, 0.0, 0.0);
in vec4 diff_color;
in vec4 tc0;
uniform sampler2D tex0;
layout (location = 0) out vec4 ocol0;
layout (location = 2) out vec4 ocol2;
layout (location = 3) out vec4 ocol3;

void main()
{
	h2 = diff_color;
	r0 = h2;
	r2 = h2;
	r3 = h2;
	r0 = texture(tex0, tc0.xy);
	ocol0 = r0;
	ocol2 = r2;
	ocol3 = r3;
}

RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_ZMIN_MAX_CONTROL: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_INPUT_MASK: f0d
RSX: W {RSXThread} NV4097_SET_VERTEX_ATTRIB_OUTPUT_MASK: 1
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_INVALIDATE_L2: 1
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0000
RSX: W {RSXThread} NV4097_SET_ANTI_ALIASING_CONTROL: ffff0001
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
RSX: W {RSXThread} NV4097_SET_ZCULL_CONTROL0: 1
RSX: W {RSXThread} NV4097_SET_SCULL_CONTROL: ff000007
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4991, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4992, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4993, location=1)
HLE: W {PPU[1] Thread (CPUThread)[0x00c49118]} cellGcmSys warning: cellGcmGetReportDataLocation(index=4994, location=1)
RSX: W {RSXThread} TODO: cellGcmSetContextDmaReport(0xbad68000)
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 2
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 3
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 4
RSX: W {RSXThread} NV4097_GET_REPORT: Unimplemented type 5
RSX: W {RSXThread} NV4097_CLEAR_REPORT_VALUE: 2
RSX: W {RSXThread} NV4097_SET_ZCULL_STATS_ENABLE: 1
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 36
HLE: W {PPU[1] Thread (CPUThread)[0x00fa10a0]} cellSysutil warning: cellAudioOutGetSoundAvailability(audioOut=0, type=0, fs=0x4, option=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa1058]} cellSysutil warning: cellAudioOutConfigure(audioOut=0, config_addr=0xd000fa3c, option_addr=0x0, (!)waitForEvent=0)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa3010]} cellAudio warning: cellAudioInit()
HLE: ! {Audio Thread} Audio thread started
HLE: W {PPU[1] Thread (CPUThread)[0x00fa3058]} cellAudio warning: cellAudioPortOpen(audioParam_addr=0xd000fa50, portNum_addr=0xd000fa28)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa3058]} cellAudio warning: *** audio port opened(nChannel=8, nBlock=8, attr=0x0, level=1.000000): port = 0
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 37
HLE: W {PPU[1] Thread (CPUThread)[0x00fa3034]} cellAudio warning: cellAudioGetPortConfig(portNum=0x0, portConfig_addr=0xd000f4c8)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb118]} sysPrxForUser warning: sys_spu_image_import(img=0x31f1a334, src=0xc09900, type=0x1)
LDR: W {PPU[1] Thread (CPUThread)[0x00fbb118]} LoadShdr32 error: shstrndx too big!
LDR: W {PPU[1] Thread (CPUThread)[0x00fbb118]} desc = 'PS3_SPU_Release/fmodps3_spu.elf'
HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317b3d28, attr_addr=0xd000f300, initial_count=0, max_count=65535)
HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 38
PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD BGM status query thread] (flags=0x0, entry=0xcd0bc0): id = 39
HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_flash/sys/external/flashMP3.pic" opened: fd = 40
HLE: W {PPU[1] Thread (CPUThread)[0x00c4b004]} sys_fs warning: cellFsClose(fd=40)
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 41
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 42
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 43
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 44
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 45
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 46
HLE: W {PPU[1] Thread (CPUThread)[0x00fa30a0]} cellAudio warning: cellAudioPortStart(portNum=0x0)
HLE: W {PPU[1] Thread (CPUThread)[0x008fede4]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a348, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
HLE: W {PPU[1] Thread (CPUThread)[0x008fede4]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x1): id = 47
HLE: W {PPU[1] Thread (CPUThread)[0x008fee14]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a670, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
HLE: W {PPU[1] Thread (CPUThread)[0x008fee14]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x2): id = 48
HLE: W {PPU[1] Thread (CPUThread)[0x008fee34]} sys_event warning: sys_event_port_create(eport_id_addr=0x31f1a34c, port_type=0x1, name=0x0)
HLE: W {PPU[1] Thread (CPUThread)[0x008fee34]} sys_event warning: *** sys_event_port created: id = 49
HLE: W {PPU[1] Thread (CPUThread)[0x008fee4c]} sys_event warning: sys_event_port_connect_local(eport_id=49, equeue_id=48)
HLE: W {PPU[1] Thread (CPUThread)[0x008feea0]} sys_spu warning: sys_spu_thread_group_create(id_addr=0x31f1a32c, num=1, prio=16, attr_addr=0xd000f33c)
HLE: W {PPU[1] Thread (CPUThread)[0x008feea0]} sys_spu warning: *** SPU Thread Group created [FMOD] (type=0x0, option.ct=0x0): id=50
HLE: W {PPU[1] Thread (CPUThread)[0x008fef34]} sys_spu warning: sys_spu_thread_initialize(thread_addr=0x31f1a330, group=0x32, spu_num=0, img_addr=0x31f1a334, attr_addr=0xd000f330, arg_addr=0xd000f360)
HLE: W {PPU[1] Thread (CPUThread)[0x008fef34]} sys_spu warning: *** New SPU Thread [FMOD] (img_offset=0xfbf000, ls_offset=0xfff000, ep=0xf0, a1=0x3200000000000000, a2=0x317c2ec400000000, a3=0x317c2d8000000000, a4=0xf78f0000000000): id=51
HLE: W {PPU[1] Thread (CPUThread)[0x008fef54]} sys_spu warning: sys_spu_thread_connect_event(id=51, eq_id=47, event_type=0x1, spup=9)
HLE: W {PPU[1] Thread (CPUThread)[0x008fef70]} sys_spu warning: sys_spu_thread_bind_queue(id=51, equeue_id=48, spuq_num=0x63)
HLE: W {PPU[1] Thread (CPUThread)[0x008fefa4]} sys_event warning: sys_event_queue_create(equeue_id_addr=0x31f1a350, attr_addr=0xd000f34c, event_queue_key=0x0, size=1)
HLE: W {PPU[1] Thread (CPUThread)[0x008fefa4]} sys_event warning: *** event_queue created [] (protocol=0x1, type=0x1): id = 52
HLE: W {PPU[1] Thread (CPUThread)[0x008fefd0]} sys_spu warning: sys_spu_thread_connect_event(id=51, eq_id=52, event_type=0x1, spup=8)
HLE: W {PPU[1] Thread (CPUThread)[0x008fefe4]} sys_spu warning: sys_spu_thread_group_start(id=50)
HLE: W {PPU[1] Thread (CPUThread)[0x008feffc]} sys_spu warning: sys_spu_thread_set_spu_cfg(id=51, value=0x0)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa3004]} cellAudio warning: cellAudioCreateNotifyEventQueue(id_addr=0x31f1a0a4, key_addr=0x31f1a0a8)
HLE: W {PPU[1] Thread (CPUThread)[0x00fa301c]} cellAudio warning: cellAudioSetNotifyEventQueue(key=0x80004d494f323221)
HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317c3018, attr_addr=0xd000f2e0, initial_count=0, max_count=65535)
HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 54
PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD libAudio event receive thread] (flags=0x0, entry=0xcd0bc0): id = 55
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 56
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 57
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 58
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 59
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 60
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 61
HLE: W {PPU[1] Thread (CPUThread)[0x008fc920]} sys_semaphore warning: sys_semaphore_create(sem_addr=0x317c30e8, attr_addr=0xd000f460, initial_count=0, max_count=65535)
HLE: ! {PPU[1] Thread (CPUThread)[0x008fc920]} *** semaphore created [] (protocol=0x2): id = 62
PPU: ! {PPU[1] Thread (CPUThread)[0x00fbb028]} *** New PPU Thread [FMOD stream thread] (flags=0x0, entry=0xcd0bc0): id = 63
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 64
HLE: W {PPU[1] Thread (CPUThread)[0x00fbb058]} sys_lwmutex warning: *** lwmutex created [] (attribute=0x12): sq_id = 65
HLE: W {PPU[1] Thread (CPUThread)[0x00c4b028]} "/dev_hdd0/game/NPUB30817/USRDIR/AUDIO/PS3/WormsNext.fev" opened: fd = 66
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
TTY: ERROR - LIBAUDIO DROPOUT - LIBAUDIO POSITION NO LONGER INCREMENTING!!
HLE: W {PPU[55] Thread (FMOD libAudio event receive thread)[0x009000d4]} sys_event_queue_receive(equeue=47) aborted
RSX: W {RSXThread} RSX thread aborted
HLE: W {PPU[31] Thread (XPlatform::SwitchPs3::Main)[0x00fa101c]} cellSysutilCheckCallback() aborted
RSX: W {VBlank thread} VBlank thread aborted
HLE: W {Audio Thread} Audio thread aborted
HLE: ! All threads stopped...
RSX: W GLVertexProgram::Delete(): glDeleteShader(2) avoided
RSX: W GLShaderProgram::Delete(): glDeleteShader(7) avoided
MEM: ! Closing memory...