[VHDL] RAM 64x16 // RESET, CE, EN

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-- Company:
-- Engineer:
--
-- Create Date:    03:21:39 04/29/2017
-- Design Name:
-- Module Name:    RAM64x16 - Behavioral
----Zadatak 1: Napisati VHDL model memorije sa sledećim karakteristikama:
----• kapacitet memorije, m = 64
----• širine magistrala podataka, n = 16
----• tip čitanja podataka iz registarske banke - sinhrono
----• mod čitanja - „Write-First"
----• sinhroni reset ulaz
----• sinhroni clock enable ulaz
----• sinhroni enable ulaz
----Za razvijeni VHDL model napisai odgovarajući testbenč pomoću kojega će biti moguće izvršiti funkcionalnu verifikaciju modela.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity RAM64x16 is
    PORT(
        CLK: in std_logic;
        RESET: in std_logic;
        CE: in std_logic;
        EN: in std_logic;

        write : in std_logic;
        wdata : in std_logic_vector(15 downto 0);

        address : in std_logic_vector(5 downto 0);

        rdata: out std_logic_vector(15 downto 0)

    );
end RAM64x16;

architecture Behavioral of RAM64x16 is
type MEM_FILE_t is array (0 to 63) of std_logic_vector(15 downto 0);
signal MEM_FILE : MEM_FILE_t;

begin
    RAM: process(CLK)
    begin
        if(CLK'event and CLK = '1') then
            if(RESET = '1') then
                MEM_FILE <= (others => (others => '0'));
            else
                if(EN = '1' and CE = '1') then
                    if(write = '1') then
                        -- Write-First
                        MEM_FILE(conv_integer(address)) <= wdata;
                        rdata <= MEM_FILE(conv_integer(address));
                    else
                        rdata <= MEM_FILE(conv_integer(address));
                    end if;
                end if;
            end if;
        end if;
    end process;
end Behavioral;