2portowy ram quartus

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY hex7seg IS
    PORT (  hex     : IN    STD_LOGIC_VECTOR(3 DOWNTO 0);
                display : OUT   STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;

ARCHITECTURE Behavior OF hex7seg IS
BEGIN
    --
    --       0
    --      ---
    --     |   |
    --    5|   |1
    --     | 6 |
    --      ---
    --     |   |
    --    4|   |2
    --     |   |
    --      ---
    --       3
    --
    PROCESS (hex)
    BEGIN
        CASE hex IS
            WHEN "0000" => display <= "0000001";
            WHEN "0001" => display <= "1001111";
            WHEN "0010" => display <= "0010010";
            WHEN "0011" => display <= "0000110";
            WHEN "0100" => display <= "1001100";
            WHEN "0101" => display <= "0100100";
            WHEN "0110" => display <= "1100000";
            WHEN "0111" => display <= "0001111";
            WHEN "1000" => display <= "0000000";
            WHEN "1001" => display <= "0001100";
            WHEN "1010" => display <= "0001000";
            WHEN "1011" => display <= "1100000";
            WHEN "1100" => display <= "0110001";
            WHEN "1101" => display <= "1000010";
            WHEN "1110" => display <= "0110000";
            WHEN OTHERS => display <= "0111000";
        END CASE;
    END PROCESS;
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;


ENTITY ram_dual IS
    PORT (
        Resetn: in std_logic;
        clock1, clock2: IN STD_LOGIC;
        data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        write_address: IN std_logic_vector(4 downto 0);
        we: IN STD_LOGIC;
        hex0 : OUT  STD_LOGIC_VECTOR(0 TO 6);
      hex1 : OUT  STD_LOGIC_VECTOR(0 TO 6);
      hex2 : OUT  STD_LOGIC_VECTOR(0 TO 6);
        hex3 : OUT  STD_LOGIC_VECTOR(0 TO 6)
    );
END ram_dual;

ARCHITECTURE rtl OF ram_dual IS

    component hex7seg is
     port( hex      : IN    STD_LOGIC_VECTOR(3 DOWNTO 0);
           display  : OUT   STD_LOGIC_VECTOR(0 TO 6));
     end component;

    TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);

    signal read_address: std_logic_vector(4 downto 0);
    SIGNAL ram_block: MEM;
    signal q: STD_LOGIC_VECTOR (3 DOWNTO 0);

    SIGNAL liczsek : STD_LOGIC_VECTOR(24 DOWNTO 0);
    signal h1a1 :STD_LOGIC_VECTOR(3 DOWNTO 0);
    signal h1a2 :STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

    PROCESS (clock2)
    BEGIN
        IF (clock2'event AND clock2 = '0') THEN
            IF (we = '1') THEN
                ram_block(to_integer(unsigned(write_address))) <= data;
            END IF;
        END IF;
    END PROCESS;


    -- zliczenie 1 sekundy
    PROCESS (Clock1)
    BEGIN
        IF  (Clock1'EVENT AND Clock1 = '1') THEN
            liczsek <= liczsek + '1';
        END IF;
    END PROCESS;

    -- licznik co 1 sekunde
    PROCESS (Clock1)
    BEGIN
        IF  (Clock1'EVENT AND Clock1 = '1') THEN
            IF (Resetn = '0') THEN  -- synchroniczne zerowanie
                read_address <= "00000";
            ELSIF (liczsek = 0) THEN
                read_address <= read_address + '1';
                if read_address = "11111" then read_address <= "00000";
                end if;
                q <= ram_block(to_integer(unsigned(read_address)));
            END IF;
        END IF;
    END PROCESS;

    h0: hex7seg port map (q, hex0);
    h1a1 <= "000" & read_address(4);
    h1a2 <= read_address(3 downto 0);
    h1: hex7seg port map (h1a2, hex1);
    h2: hex7seg port map (h1a1, hex2);
    h3: hex7seg port map (("000" & we), hex3);

END rtl;