library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity RAM is
port(
 RAM_IN: in std_logic_vector(7 downto 0);   --wejscie
 RAM_OUT: out std_logic_vector(7 downto 0);     --wyjscie
 RAM_WR: in std_logic;                              --Zezwolenie
 RAM_CLOCK: in std_logic;                           --zegar
 RAM_ms: in std_logic_vector(3 downto 0)        --rej. RARH (clk, clr), RARL (clk, clr)
);
end RAM;

architecture Behavioral of RAM is
-------------------------------------------------------------------------------------------
    attribute RAM_style: string;                                                            --typ pamięci
    type RAM_ARRAY is array (0 to 1023 ) of std_logic_vector (7 downto 0);  --definicja rozmiaru
                                                                                                    --pamięci RAM 2^10=1024, 8 bit wejście/wyjście
    signal RAM: RAM_ARRAY;
-------------------------------------------------------------------------------------------
    signal RAM_ADDR : std_logic_vector(9 downto 0);     --adres ram
begin

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    process(RAM_CLOCK,RAM_WR)                                               --proces zegarowy
        begin
            if(rising_edge(RAM_CLOCK)) then                             --jeżeli narastające zbocze zegara

                if(RAM_WR='1') then                                             --jeżeli RAM_WR=1

                    RAM(to_integer(unsigned(RAM_ADDR))) <= RAM_IN;  --przypisz do pojedynczej komórki pamięci zgodnie z
                                                                                    --adresem zawartość odczytaną
                end if;
            RAM_OUT <= RAM(to_integer(unsigned(RAM_ADDR)));         --przypisanie wyjscia
            end if;
    end process;
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    process(RAM_ms(1), RAM_ms(0))               --rejestr RARL
        begin
            if(rising_edge(RAM_ms(1))) then --zapis
                if (RAM_ms(0)='0') then
                    RAM_ADDR(7 downto 0)<=RAM_IN;
                end if;
            end if;

            if(RAM_ms(0)='1') then              --zerowanie
                RAM_ADDR(7 downto 0)<="00000000";
            end if;
    end process;
---------------------------------------------------------------------------------------------
    process(RAM_ms(2), RAM_ms(3))               --rejestr RARH
        begin
            if(rising_edge(RAM_ms(3))) then --zapis
                if (RAM_ms(2)='0') then
                    RAM_ADDR(9 downto 8)<=RAM_IN(1 downto 0);
                end if;
            end if;

            if(RAM_ms(2)='1') then              --zerowanie
                RAM_ADDR(9 downto 8)<="00";
            end if;
    end process;
end Behavioral;