architecture Behavioral of cu is

    type STATES is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,NOP);
    signal sSTATE,sNEXT_STATE : STATES;

begin

    process(iCLK,iRST) begin
        if(iRST='1') then
            sSTATE <= S0;
        elsif(rising_edge(iCLK)) then
            sSTATE <= sNEXT_STATE;
        end if;
    end process;

    process(sSTATE,iZERO) begin
        case(sSTATE) is
            when S0 => sNEXT_STATE<=S1;
            when S1 => sNEXT_STATE<=S2;
            when S2 => sNEXT_STATE<=S3;
            when S3 => sNEXT_STATE<=S4;
            when S4 =>
                if(iZERO='1') then
                    sNEXT_STATE<=NOP;
                else
                    sNEXT_STATE<=S5;
                end if;
            when S5 => sNEXT_STATE<=S6;
            when S6 =>
                if(iZERO='1') then
                    sNEXT_STATE<=S9;
                else
                    sNEXT_STATE<=S7;
                end if;
            when S7 => sNEXT_STATE<=S8;
            when S8 => sNEXT_STATE<=S6;
            when S9 => sNEXT_STATE<=S10;
            when S10 => sNEXT_STATE<=S11;
            when S11 => sNEXT_STATE<=S4;
            when others => sNEXT_STATE<=NOP;
        end case;
    end process;

    process(sSTATE) begin

        case(sSTATE) is
            when S0 =>
                oREG_WE<="00000001";
                oALU_SEL<="0010";
                oMUXA_SEL<="0001";
                oMUXB_SEL<="0001";
            when S1 =>
                oREG_WE<="00000010";
                oALU_SEL<="0000";
                oMUXA_SEL<="1000";
                oMUXB_SEL<="----";
            when S2 =>
                oREG_WE<="00000100";
                oALU_SEL<="0111";
                oMUXA_SEL<="0001";
                oMUXB_SEL<="----";
            when S3 =>
                oREG_WE<="00001000";
                oALU_SEL<="0010";
                oMUXA_SEL<="0001";
                oMUXB_SEL<="0001";
            when S4 =>
                oREG_WE<="00000000";
                oALU_SEL<="0000";
                oMUXA_SEL<="0010";
                oMUXB_SEL<="----";
            when S5 =>
                oREG_WE<="00001000";
                oALU_SEL<="0010";
                oMUXA_SEL<="0001";
                oMUXB_SEL<="0001";
            when S6 =>
                oREG_WE<="00000000";
                oALU_SEL<="0010";
                oMUXA_SEL<="0000";
                oMUXB_SEL<="0010";
            when S7 =>
                oREG_WE<="00001000";
                oALU_SEL<="0001";
                oMUXA_SEL<="0011";
                oMUXB_SEL<="0001";
            when S8 =>
                oREG_WE<="00000001";
                oALU_SEL<="0110";
                oMUXA_SEL<="0000";
                oMUXB_SEL<="----";
            when S9 =>
                oREG_WE<="00000001";
                oALU_SEL<="0010";
                oMUXA_SEL<="0001";
                oMUXB_SEL<="0001";
            when S10 =>
                oREG_WE<="00000100";
                oALU_SEL<="0111";
                oMUXA_SEL<="0010";
                oMUXB_SEL<="----";
            when S11 =>
                oREG_WE<="00000010";
                oALU_SEL<="0000";
                oMUXA_SEL<="0011";
                oMUXB_SEL<="----";
            when others=>
                oREG_WE<="--------";
                oALU_SEL<="----";
                oMUXA_SEL<="----";
                oMUXB_SEL<="----";

        end case;
    end process;

end architecture;