Exercice 2 - Examen 2010 VHDL - SL2

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity reg_ex3 is
    port(
        D : std_logic_vector(3 downto 0);
        op: std_logic_vector(1 downto 0);
        clk: std_logic;
        left_in: std_logic;
        right_in: std_logic;
        Q: out std_logic_vector(3 downto 0)
    );
end entity;

architecture toto of reg_ex3 is
    signal inside, nextone : std_logic_vector(3 downto 0);

begin
    inside <= inside;

    process (clk, D, op, left_in, right_in)
    begin
        if rising_edge(clk) then
            case op is
                when "00" =>
                    null;
                when "01" =>
                    inside <= inside(3 downto 1) & right_in;
                when "10" =>
                    inside <= left_in & inside(2 downto 0);
                when "11" =>
                    inside <= D;
                when others =>
                    null;
            end case;
        end if;
    end process;

    Q <= inside;
end toto;