library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity litery1 is
    Port ( p : out  STD_LOGIC_VECTOR (3 downto 0);
           r : out  STD_LOGIC_VECTOR (3 downto 0);
           o : out  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           t : out  STD_LOGIC_VECTOR (3 downto 0);
           e1 : out  STD_LOGIC_VECTOR (3 downto 0);
           spacja0 : out  STD_LOGIC_VECTOR (3 downto 0);
           z : out  STD_LOGIC_VECTOR (3 downto 0);
           a1 : out  STD_LOGIC_VECTOR (3 downto 0);
           d : out  STD_LOGIC_VECTOR (3 downto 0);
           a2 : out  STD_LOGIC_VECTOR (3 downto 0);
           n : out  STD_LOGIC_VECTOR (3 downto 0);
           i : out  STD_LOGIC_VECTOR (3 downto 0);
           e2 : out  STD_LOGIC_VECTOR (3 downto 0);
           spacja1 : out  STD_LOGIC_VECTOR (3 downto 0);
           spacja2 : out  STD_LOGIC_VECTOR (3 downto 0));
end litery1;

architecture Behavioral of litery1 is

begin
           p <= "0000";
            r <=  "0001";
            o <=  "0010";
            s <=  "0011";
            t <=  "0100";
            e1 <=  "0101";
            spacja0 <=  "0110";
            z <=  "0111";
            a1 <=  "1000";
            d <=  "1001";
            a2 <=  "1010";
            n <=  "1011";
            i <=  "1100";
            e2 <=  "1101";
            spacja1 <=  "1110";
            spacja2 <=  "1111";

end Behavioral;