clk_dvb_s2x.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity clk_dvb_s2x is
    Port(
        i_clk             :  in  std_logic;                              -- тактирование
        i_res             :  in  std_logic;                              -- сброс
        i_enb             :  in  std_logic;                              -- разрешение работы
        i_QAM_select      :  in  std_logic_vector (2 downto 0);          -- выбор модуляции
        i_frame_select    :  in  std_logic_vector (0 downto 0);          -- выбор фрейма
        i_data            :  in  std_logic_vector (0 downto 0);          -- входные данные
        o_data            :  out std_logic_vector (0 downto 0));         -- выходные данные
end entity;

architecture Behavioral of clk_dvb_s2x is

    signal res_0          :   std_logic;
    signal res_1          :   std_logic;
    signal enb_0          :   std_logic;
    signal enb_1          :   std_logic;
    signal QAM_select_0   :   std_logic_vector (2 downto 0);
    signal QAM_select_1   :   std_logic_vector (2 downto 0);
    signal frame_select_0 :   std_logic_vector (0 downto 0);
    signal frame_select_1 :   std_logic_vector (0 downto 0);
    signal i_data_0       :   std_logic_vector (0 downto 0);
    signal i_data_1       :   std_logic_vector (0 downto 0);

    signal o_data_0       :   std_logic_vector (0 downto 0);
    signal o_data_1       :   std_logic_vector (0 downto 0);
    signal o_data_2       :   std_logic_vector (0 downto 0);

    component DVB_S2X_interleaver
        Port(
            i_clk           : in  std_logic;
            i_res           : in  std_logic;
            i_enb           : in  std_logic;
            i_QAM_select    : in  std_logic_vector (2 downto 0);
            i_frame_select  : in  std_logic_vector (0 downto 0);
            i_data          : in  std_logic_vector (0 downto 0);
            o_data          : out std_logic_vector (0 downto 0));
    end component;

begin

dut: DVB_S2X_interleaver
    port map(
        i_clk          => i_clk,
        i_res          => res_1,
        i_enb          => enb_1,
        i_QAM_select   => QAM_select_1,
        i_frame_select => frame_select_1,
        i_data         => i_data_1,
        o_data         => o_data_0);

process(i_clk) begin
    if(rising_edge(i_clk)) then

        res_0 <= i_res;
        res_1 <= res_0;

        enb_0 <= i_enb;
        enb_1 <= enb_0;

        QAM_select_0 <= i_QAM_select;
        QAM_select_1 <= QAM_select_0;

        frame_select_0 <= i_frame_select;
        frame_select_1 <= frame_select_0;

        i_data_0 <= i_data;
        i_data_1 <= i_data_0;

    end if;
end process;


process(i_clk) begin
    if(rising_edge(i_clk)) then

        o_data_1 <= o_data_0;
        o_data_2 <= o_data_1;
        o_data   <= o_data_2;

    end if;
end process;

end Behavioral;