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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use ieee.std_logic_unsigned.all;
- use IEEE.NUMERIC_STD.ALL;
- entity mac is
- generic (input_data_width : natural :=12);
- Port ( clk_i : in STD_LOGIC;
- ce_i : in STD_LOGIC;
- u_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
- b_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
- u_o : out STD_LOGIC_VECTOR (input_data_width-1 downto 0);
- mac_i : in STD_LOGIC_VECTOR (2*input_data_width-1 downto 0);
- mac_o : out STD_LOGIC_VECTOR (2*input_data_width-1 downto 0));
- end mac;
- architecture Behavioral of mac is
- signal reg_s : STD_LOGIC_VECTOR (input_data_width-1 downto 0):=(others=>'0');
- begin
- process(clk_i)
- begin
- if (clk_i'event and clk_i = '1')then
- if (ce_i = '1') then
- reg_s <= u_i;
- end if;
- end if;
- end process;
- mac_o <= std_logic_vector(signed(mac_i) + (signed(u_i) * signed(b_i)));
- u_o <= reg_s;
- end Behavioral;
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