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MAC za FIR filtar, Direktna forma parametrizovano

Jun 26th, 2018
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VHDL 1.03 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use ieee.std_logic_unsigned.all;
  4. use IEEE.NUMERIC_STD.ALL;
  5.  
  6. entity mac is
  7.     generic (input_data_width : natural :=12);
  8.     Port ( clk_i : in STD_LOGIC;
  9.            ce_i : in STD_LOGIC;
  10.            u_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
  11.            b_i : in STD_LOGIC_VECTOR (input_data_width-1 downto 0);
  12.            u_o : out STD_LOGIC_VECTOR (input_data_width-1 downto 0);
  13.            mac_i : in STD_LOGIC_VECTOR (2*input_data_width-1 downto 0);          
  14.            mac_o : out STD_LOGIC_VECTOR (2*input_data_width-1 downto 0));
  15. end mac;
  16.  
  17. architecture Behavioral of mac is
  18.     signal reg_s : STD_LOGIC_VECTOR (input_data_width-1 downto 0):=(others=>'0');
  19. begin
  20.     process(clk_i)
  21.     begin
  22.         if (clk_i'event and clk_i = '1')then
  23.             if (ce_i = '1') then
  24.                 reg_s <= u_i;
  25.             end if;
  26.         end if;
  27.     end process;
  28.     mac_o <= std_logic_vector(signed(mac_i) + (signed(u_i) * signed(b_i)));
  29.     u_o <= reg_s;
  30. end Behavioral;
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