library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
entity koder is
port(
      clk : in STD_LOGIC;
      din : in std_logic);
end koder;

architecture Behavioral of koder is

TYPE STATE_TYPE IS (s0,s1,s2,s3);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;

component peremezh is
    Port (clk : in std_logic;
          din : in std_logic;
          dintabl : in integer := 0;
          dout : out std_logic_vector(999 downto 0));
end component;

signal check1 : integer := 0;
signal peremezhdin : std_logic_vector(999 downto 0):=(others => '0');
signal rst : std_logic := '0';
signal findout: std_logic;
type rom is array (0 to 2) of std_logic;
signal soderzhimoe : rom := (others=> '0');
----------------------------------------------------------------------------
begin

clocked_proc : PROCESS (clk) BEGIN
    IF rising_edge(clk) THEN
        iF (rst = '0') THEN
            current_state <= s0;
        ELSE
            current_state <= next_state;
        END IF;
    END IF;
 END PROCESS clocked_proc;
 --------------------------------------------------------------------------
 nextstate_proc : PROCESS (clk,check1,current_state) BEGIN
    CASE current_state IS
        WHEN s0 =>
                if rising_edge(clk) then
                        soderzhimoe(1) <= soderzhimoe(0);
                        soderzhimoe(0) <= din xor (soderzhimoe(1) xor soderzhimoe(2));
                        soderzhimoe(2) <= soderzhimoe(1);
                end if;
                IF (check1=1) THEN
                next_state <= s1;
            END IF;
        WHEN s1 =>
            IF (check1=2) THEN
                next_state <= s2;
            END IF;
        WHEN s2 =>
            IF (check1=3) THEN
                next_state <= s3;
            end if;
        WHEN OTHERS =>
                next_state <= s0;
    END CASE;
  END PROCESS nextstate_proc;
 --------------------------------------------------------------
 output_proc : PROCESS (clk, current_state) BEGIN

  CASE current_state IS
  WHEN s0 =>
  findout <= soderzhimoe(0) xor soderzhimoe(2);
  WHEN s1 =>

  WHEN s2 =>

  WHEN s3 =>

  WHEN OTHERS =>
  NULL;
  END CASE;
  END PROCESS output_proc;

-----------------------------------------------------------------

process(clk) begin
    if rising_edge(clk) then
        FOR I in 0 to 999 loop
            soderzhimoe(1) <= soderzhimoe(0);
            soderzhimoe(0) <= peremezhdin(i) xor (soderzhimoe(1) xor soderzhimoe(2));
            soderzhimoe(2) <= soderzhimoe(1);
            findout <= soderzhimoe(0) xor soderzhimoe(2);
        end loop;
    end if;
end process;

komp: peremezh
port map(
    clk => clk,
    din => din,
    dout => peremezhdin);

end behavioral;