--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   12:59:11 11/14/2011
-- Design Name:
-- Module Name:   C:/Users/RPOD/Documents/Studium/Technische Informatik/Aufgabe1/test.vhd
-- Project Name:  Aufgabe1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DECODER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test IS
END test;

ARCHITECTURE behavior OF test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DECODER
    PORT(
         input : IN  bit_vector(3 downto 0);
         output : OUT  bit_vector(6 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal input : bit_vector(3 downto 0) := (others => '0');

    --Outputs
   signal output : bit_vector(6 downto 0);
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

   signal clock: std_logic;
    constant clock_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: DECODER PORT MAP (
          input => input,
          output => output
        );

   -- Clock process definitions
   clock_process :process
   begin
        clock <= '0';
        wait for clock_period/2;
        clock <= '1';
        wait for clock_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      wait for clock_period*10;

      -- insert stimulus here

      wait;
   end process;

END;