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- #if defined(INTELFPGA_CL)
- #define UTL_ENABLE_CHANNELS _Pragma("OPENCL EXTENSION cl_intel_channels : enable")
- #define UTL_READ_CH(ch) read_channel_intel(ch)
- #define UTL_WRITE_CH(ch, dat) write_channel_intel(ch, dat)
- #else
- #define UTL_ENABLE_CHANNELS _Pragma("OPENCL_EXTENSION cl_altera_channels : enable")
- #define UTL_READ_CH(ch) read_channel_altera(ch)
- #define UTL_WRITE_CH(ch, dat) write_channel_altera(ch, dat)
- #endif
- UTL_ENABLE_CHANNELS
- #define DATA_SIZE 4
- #define VEC_SIZE 4
- typedef struct {
- char d[DATA_SIZE];
- } data_t;
- typedef struct {
- data_t v[VEC_SIZE];
- } data_ch_t;
- typedef struct {
- char v[VEC_SIZE];
- } ch_t;
- channel ch_t ch_1 __attribute((depth(0)));
- channel data_ch_t ch_2 __attribute((depth(0)));
- channel data_ch_t ch_3 __attribute((depth(0)));
- channel ch_t ch_4 __attribute((depth(0)));
- __kernel
- __attribute((task))
- void k1(__global const ch_t* restrict data1,
- __global const data_ch_t* restrict data2,
- __global const data_t* restrict data3,
- const int l1,
- const int l2) {
- data_t buf_d3[2][2];
- data_ch_t buf_d2[8];
- #pragma loop_coalesce 2
- for (int i = 0; i < l1; ++i) {
- for (int j = 0; j < l2; ++j) {
- buf_d3[0][j] = data3[j];
- buf_d2[j] = data2[j];
- UTL_WRITE_CH(ch_1, data1[j]);
- UTL_WRITE_CH(ch_2, buf_d2[i]);
- data_ch_t dch;
- dch.v[0] = buf_d3[0][j];
- UTL_WRITE_CH(ch_3, dch);
- }
- }
- }
- __kernel
- __attribute((task))
- void k2(const int l1, const int l2) {
- for (int i = 0; i < l1; ++i) {
- ch_t t;
- for (int j = 0; j < l2; ++j) {
- const data_ch_t d3 = UTL_READ_CH(ch_3);
- const data_ch_t d2 = UTL_READ_CH(ch_2);
- t.v[0] += d2.v[0].d[0] * d3.v[0].d[0];
- const ch_t d1 = UTL_READ_CH(ch_1);
- t.v[0] += d1.v[0];
- }
- UTL_WRITE_CH(ch_4, t);
- }
- }
- __kernel
- __attribute((task))
- void k3(__global char* restrict output, const int l1) {
- for (int j = 0; j < l1; ++j) {
- ch_t dat = UTL_READ_CH(ch_4);
- output[j] = dat.v[0];
- }
- }
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