bistabil_D

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity bistabil_D is
    port(D,EN,S,R,CLK:in std_logic; Q: out std_logic);
end entity;

architecture comportamentala of bistabil_D is
begin
    process(EN,CLK,S,R)
    begin
        if(EN='1') then
            if(S='0' and R='1') then Q<='1';
            elsif (R='0' and S='1')then Q<='0';
            elsif (R='0' and S='0') then Q<='Z';
            elsif(CLK'event and (CLK='1')) then Q<=D;
            end if;
        else
            Q<='Z';
        end if;
    end process;
end architecture;