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hbinderup94

count_ones

Apr 23rd, 2017
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VHDL 0.89 KB | None | 0 0
  1. ------------ count_ones ---------
  2. Library ieee;
  3. use ieee.std_logic_1164.all;
  4. use ieee.numeric_std.all;
  5.  
  6. entity count_ones is
  7. port(
  8.     A       : in std_logic_vector(7 downto 0);
  9.     ones    : out std_logic_vector(3 downto 0));  
  10. end count_ones;
  11.  
  12. architecture structural of count_ones is
  13. begin
  14.     count: process(A)                               -- Counter process initieres
  15.         variable countA : integer;                  -- Counter variabel defineres
  16.         begin
  17.             countA := 0;                            -- Counter varibel resettes
  18.             for index in 7 downto 0 loop            -- Loop som gentager sig 8 gange
  19.                 if (A(index) = '1') then            -- Tester om vores A-input er 1 eller ikke
  20.                     countA := countA + 1;           -- Hvis A = 1, så stiger vores counter
  21.                 else
  22.                 end if;
  23.             end loop;
  24.  
  25.             ones <= std_logic_vector(to_unsigned(countA, ones'length)); -- Counteren konverteres til en vector,
  26.         end process;                                                    -- da input på bin2hex er en vector
  27. end structural;
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