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gcc-msm8255.c

govnonabortike
Oct 13th, 2026 (edited)
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  1. // SPDX-License-Identifier: GPL-2.0-only
  2.  
  3. #include <linux/kernel.h>
  4. #include <linux/module.h>
  5. #include <linux/of.h>
  6. #include <linux/platform_device.h>
  7. #include <linux/regmap.h>
  8. #include <linux/clk-provider.h>
  9. #include "clk-alpha-pll.h"
  10. #include "clk-regmap.h"
  11. #include "clk-rcg.h"
  12. #include "clk-pll.h"
  13. #include "clk-regmap-mux.h"
  14. #include <dt-bindings/clock/qcom,gcc-msm8255.h>
  15. // EXTREMELY NEEDED STATIC STRUCTS FOR 1440+ LINES!
  16. static struct clk_rcg mdp_lcdc_pclk_clk;
  17. static struct clk_rcg mdp_lcdc_pad_pclk_clk;
  18. static struct clk_rcg mdp_vsync_clk;
  19. static struct clk_rcg mi2s_codec_rx_m_clk;
  20. static struct clk_gate mi2s_codec_rx_s_clk;
  21. static struct clk_rcg mi2s_codec_tx_m_clk;
  22. static struct clk_gate mi2s_codec_tx_s_clk;
  23. static struct clk_rcg mi2s_m_clk;
  24. static struct clk_gate mi2s_s_clk;
  25. static struct clk_regmap_mux acpu_clk;
  26. // DO NOT ABSOLUTE DELETE ANYTHING ABOVE THIS SPECIFIC COMMENT! unless its unused
  27. static const struct clk_parent_data gcc_msm8255_parent_data[] = {
  28.     { .fw_name = "cxo_board", .name = "cxo_board" },
  29.     { .fw_name = "pll1_clk", .name = "pll1_clk" },
  30.     { .fw_name = "pll4_clk", .name = "pll4_clk" },
  31.     { .fw_name = "pll3_clk", .name = "pll3_clk" },
  32. };
  33.  
  34. /* PLL1 */
  35. static struct clk_pll pll1_clk = {
  36.     .l_reg = 0x0264,
  37.     .status_reg = 0x0334,
  38.     .status_bit = 16,
  39.     .clkr = {
  40.         .enable_reg = 0x0264,
  41.         .enable_mask = BIT(1),
  42.         .hw.init = &(struct clk_init_data){
  43.             .name = "pll1_clk",
  44.             .parent_data = &(const struct clk_parent_data){
  45.                 .fw_name = "cxo_board",
  46.             },
  47.             .num_parents = 1,
  48.             .ops = &clk_pll_vote_ops,
  49.         },
  50.     },
  51. };
  52.  
  53. /* PLL2 */
  54. static struct clk_pll pll2_clk = {
  55.     .l_reg = 0x0264,
  56.     .status_reg = 0x0350,
  57.     .status_bit = 16,
  58.     .clkr = {
  59.         .enable_reg = 0x0264,
  60.         .enable_mask = BIT(2),
  61.         .hw.init = &(struct clk_init_data){
  62.             .name = "pll2_clk",
  63.             .parent_data = &(const struct clk_parent_data){
  64.                 .fw_name = "cxo_board",
  65.             },
  66.             .num_parents = 1,
  67.             .ops = &clk_pll_vote_ops,
  68.         },
  69.     },
  70. };
  71.  
  72. /* PLL3 */
  73. static struct clk_pll pll3_clk = {
  74.     .l_reg = 0x0264,
  75.     .status_reg = 0x036c,
  76.     .status_bit = 16,
  77.     .clkr = {
  78.         .enable_reg = 0x0264,
  79.         .enable_mask = BIT(3),
  80.         .hw.init = &(struct clk_init_data){
  81.             .name = "pll3_clk",
  82.             .parent_data = &(const struct clk_parent_data){
  83.                 .fw_name = "lpxo_board",
  84.             },
  85.             .num_parents = 1,
  86.             .ops = &clk_pll_vote_ops,
  87.         },
  88.     },
  89. };
  90.  
  91. /* PLL4 */
  92. static struct clk_pll pll4_clk = {
  93.     .l_reg = 0x0264,
  94.     .status_reg = 0x0254,
  95.     .status_bit = 16,
  96.     .clkr = {
  97.         .enable_reg = 0x0264,
  98.         .enable_mask = BIT(4),
  99.         .hw.init = &(struct clk_init_data){
  100.             .name = "pll4_clk",
  101.             .parent_data = &(const struct clk_parent_data){
  102.                 .fw_name = "cxo_board",
  103.             },
  104.             .num_parents = 1,
  105.             .ops = &clk_pll_vote_ops,
  106.         },
  107.     },
  108. };
  109.  
  110. static struct clk_gate glbl_root_clk = {
  111.     .reg = (void __iomem *)0x03bc,
  112.     .bit_idx = 29,
  113.     .hw.init = &(struct clk_init_data){
  114.         .name = "glbl_root_clk",
  115.         .parent_data = &(const struct clk_parent_data){
  116.             .fw_name = "lpxo_board",
  117.         },
  118.         .num_parents = 1,
  119.         .ops = &clk_gate_ops,
  120.     },
  121. };
  122.  
  123. static struct clk_gate axi_li_apps_clk = {
  124.     .reg = (void __iomem *)0x03bc,
  125.     .bit_idx = 2,
  126.     .hw.init = &(struct clk_init_data){
  127.         .name = "axi_li_apps_clk",
  128.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  129.         .num_parents = 1,
  130.         .ops = &clk_gate_ops,
  131.     },
  132. };
  133.  
  134. static struct clk_gate axi_li_adsp_a_clk = {
  135.     .reg = (void __iomem *)0x03c0,
  136.     .bit_idx = 14,
  137.     .hw.init = &(struct clk_init_data){
  138.         .name = "axi_li_adsp_a_clk",
  139.         .parent_hws = (const struct clk_hw *[]){ &axi_li_apps_clk.hw },
  140.         .num_parents = 1,
  141.         .ops = &clk_rcg2_gp_ops,
  142.     },
  143. };
  144.  
  145. static struct clk_gate axi_li_jpeg_clk = {
  146.     .reg = (void __iomem *)0x03c0,
  147.     .bit_idx = 19,
  148.     .hw.init = &(struct clk_init_data){
  149.         .name = "axi_li_jpeg_clk",
  150.         .parent_hws = (const struct clk_hw *[]){ &axi_li_apps_clk.hw },
  151.         .num_parents = 1,
  152.         .ops = &clk_gate_ops,
  153.     },
  154. };
  155.  
  156. static struct clk_gate axi_li_vfe_clk = {
  157.     .reg = (void __iomem *)0x03bc,
  158.     .bit_idx = 23,
  159.     .hw.init = &(struct clk_init_data){
  160.         .name = "axi_li_vfe_clk",
  161.         .parent_hws = (const struct clk_hw *[]){ &axi_li_apps_clk.hw },
  162.         .num_parents = 1,
  163.         .ops = &clk_gate_ops,
  164.     },
  165. };
  166.  
  167. static struct clk_gate axi_mdp_clk = {
  168.     .reg = (void __iomem *)0x03c0,
  169.     .bit_idx = 29,
  170.     .hw.init = &(struct clk_init_data){
  171.         .name = "axi_mdp_clk",
  172.         .parent_hws = (const struct clk_hw *[]){ &axi_li_apps_clk.hw },
  173.         .num_parents = 1,
  174.         .ops = &clk_gate_ops,
  175.     },
  176. };
  177.  
  178. static struct clk_gate axi_li_vg_clk = {
  179.     .reg = (void __iomem *)0x03bc,
  180.     .bit_idx = 3,
  181.     .hw.init = &(struct clk_init_data){
  182.         .name = "axi_li_vg_clk",
  183.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  184.         .num_parents = 1,
  185.         .ops = &clk_gate_ops,
  186.     },
  187. };
  188.  
  189. static struct clk_gate axi_grp_2d_clk = {
  190.     .reg = (void __iomem *)0x03bc,
  191.     .bit_idx = 21,
  192.     .hw.init = &(struct clk_init_data){
  193.         .name = "axi_grp_2d_clk",
  194.         .parent_hws = (const struct clk_hw *[]){ &axi_li_vg_clk.hw },
  195.         .num_parents = 1,
  196.         .ops = &clk_gate_ops,
  197.     },
  198. };
  199.  
  200. static struct clk_gate axi_li_grp_clk = {
  201.     .reg = (void __iomem *)0x03bc,
  202.     .bit_idx = 22,
  203.     .hw.init = &(struct clk_init_data){
  204.         .name = "axi_li_grp_clk",
  205.         .parent_hws = (const struct clk_hw *[]){ &axi_li_vg_clk.hw },
  206.         .num_parents = 1,
  207.         .ops = &clk_gate_ops,
  208.     },
  209. };
  210.  
  211. static struct clk_gate axi_mfc_clk = {
  212.     .reg = (void __iomem *)0x03c0,
  213.     .bit_idx = 20,
  214.     .hw.init = &(struct clk_init_data){
  215.         .name = "axi_mfc_clk",
  216.         .parent_hws = (const struct clk_hw *[]){ &axi_li_vg_clk.hw },
  217.         .num_parents = 1,
  218.         .ops = &clk_gate_ops,
  219.     },
  220. };
  221.  
  222. static struct clk_gate axi_rotator_clk = {
  223.     .reg = (void __iomem *)0x03c0,
  224.     .bit_idx = 22,
  225.     .hw.init = &(struct clk_init_data){
  226.         .name = "axi_rotator_clk",
  227.         .parent_hws = (const struct clk_hw *[]){ &axi_li_vg_clk.hw },
  228.         .num_parents = 1,
  229.         .ops = &clk_gate_ops,
  230.     },
  231. };
  232.  
  233. static struct clk_gate axi_vpe_clk = {
  234.     .reg = (void __iomem *)0x03c0,
  235.     .bit_idx = 21,
  236.     .hw.init = &(struct clk_init_data){
  237.         .name = "axi_vpe_clk",
  238.         .parent_hws = (const struct clk_hw *[]){ &axi_li_vg_clk.hw },
  239.         .num_parents = 1,
  240.         .ops = &clk_gate_ops,
  241.     },
  242. };
  243.  
  244. static struct clk_gate adm_clk = {
  245.     .reg = (void __iomem *)0x03bc,
  246.     .bit_idx = 5,
  247.     .hw.init = &(struct clk_init_data){
  248.         .name = "adm_clk",
  249.         .parent_hws = (const struct clk_hw *[]){ &axi_li_apps_clk.hw },
  250.         .num_parents = 1,
  251.         .ops = &clk_gate_ops,
  252.     },
  253. };
  254.  
  255. static struct clk_gate adm_p_clk = {
  256.     .reg = (void __iomem *)0x03c0,
  257.     .bit_idx = 15,
  258.     .hw.init = &(struct clk_init_data){
  259.         .name = "adm_p_clk",
  260.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  261.         .num_parents = 1,
  262.         .ops = &clk_gate_ops,
  263.     },
  264. };
  265.  
  266. static struct clk_gate ce_clk = {
  267.     .reg = (void __iomem *)0x03bc,
  268.     .bit_idx = 6,
  269.     .hw.init = &(struct clk_init_data){
  270.         .name = "ce_clk",
  271.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  272.         .num_parents = 1,
  273.         .ops = &clk_gate_ops,
  274.     },
  275. };
  276.  
  277. static struct clk_gate camif_pad_p_clk = {
  278.     .reg = (void __iomem *)0x03bc,
  279.     .bit_idx = 9,
  280.     .hw.init = &(struct clk_init_data){
  281.         .name = "camif_pad_p_clk",
  282.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  283.         .num_parents = 1,
  284.         .ops = &clk_gate_ops,
  285.     },
  286. };
  287.  
  288. static struct clk_gate csi0_p_clk = {
  289.     .reg = (void __iomem *)0x03bc,
  290.     .bit_idx = 30,
  291.     .hw.init = &(struct clk_init_data){
  292.         .name = "csi0_p_clk",
  293.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  294.         .num_parents = 1,
  295.         .ops = &clk_gate_ops,
  296.     },
  297. };
  298.  
  299. static struct clk_gate emdh_p_clk = {
  300.     .reg = (void __iomem *)0x03c0,
  301.     .bit_idx = 3,
  302.     .hw.init = &(struct clk_init_data){
  303.         .name = "emdh_p_clk",
  304.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  305.         .num_parents = 1,
  306.         .ops = &clk_gate_ops,
  307.     },
  308. };
  309.  
  310. static struct clk_gate grp_2d_p_clk = {
  311.     .reg = (void __iomem *)0x03bc,
  312.     .bit_idx = 24,
  313.     .hw.init = &(struct clk_init_data){
  314.         .name = "grp_2d_p_clk",
  315.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  316.         .num_parents = 1,
  317.         .ops = &clk_gate_ops,
  318.     },
  319. };
  320.  
  321. static struct clk_gate grp_3d_p_clk = {
  322.     .reg = (void __iomem *)0x03c0,
  323.     .bit_idx = 17,
  324.     .hw.init = &(struct clk_init_data){
  325.         .name = "grp_3d_p_clk",
  326.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  327.         .num_parents = 1,
  328.         .ops = &clk_gate_ops,
  329.     },
  330. };
  331.  
  332. static struct clk_gate jpeg_p_clk = {
  333.     .reg = (void __iomem *)0x03c0,
  334.     .bit_idx = 24,
  335.     .hw.init = &(struct clk_init_data){
  336.         .name = "jpeg_p_clk",
  337.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  338.         .num_parents = 1,
  339.         .ops = &clk_gate_ops,
  340.     },
  341. };
  342.  
  343. static struct clk_gate lpa_p_clk = {
  344.     .reg = (void __iomem *)0x03c0,
  345.     .bit_idx = 7,
  346.     .hw.init = &(struct clk_init_data){
  347.         .name = "lpa_p_clk",
  348.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  349.         .num_parents = 1,
  350.         .ops = &clk_gate_ops,
  351.     },
  352. };
  353.  
  354. static struct clk_gate mdp_p_clk = {
  355.     .reg = (void __iomem *)0x03c0,
  356.     .bit_idx = 6,
  357.     .hw.init = &(struct clk_init_data){
  358.         .name = "mdp_p_clk",
  359.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  360.         .num_parents = 1,
  361.         .ops = &clk_gate_ops,
  362.     },
  363. };
  364.  
  365. static struct clk_gate mfc_p_clk = {
  366.     .reg = (void __iomem *)0x03c0,
  367.     .bit_idx = 26,
  368.     .hw.init = &(struct clk_init_data){
  369.         .name = "mfc_p_clk",
  370.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  371.         .num_parents = 1,
  372.         .ops = &clk_gate_ops,
  373.     },
  374. };
  375.  
  376. static struct clk_gate pmdh_p_clk = {
  377.     .reg = (void __iomem *)0x03c0,
  378.     .bit_idx = 4,
  379.     .hw.init = &(struct clk_init_data){
  380.         .name = "pmdh_p_clk",
  381.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  382.         .num_parents = 1,
  383.         .ops = &clk_gate_ops,
  384.     },
  385. };
  386.  
  387. static struct clk_gate rotator_imem_clk = {
  388.     .reg = (void __iomem *)0x03c0,
  389.     .bit_idx = 23,
  390.     .hw.init = &(struct clk_init_data){
  391.         .name = "rotator_imem_clk",
  392.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  393.         .num_parents = 1,
  394.         .ops = &clk_gate_ops,
  395.     },
  396. };
  397.  
  398. static struct clk_gate rotator_p_clk = {
  399.     .reg = (void __iomem *)0x03c0,
  400.     .bit_idx = 25,
  401.     .hw.init = &(struct clk_init_data){
  402.         .name = "rotator_p_clk",
  403.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  404.         .num_parents = 1,
  405.         .ops = &clk_gate_ops,
  406.     },
  407. };
  408.  
  409. static struct clk_gate sdc1_p_clk = {
  410.     .reg = (void __iomem *)0x03bc,
  411.     .bit_idx = 7,
  412.     .hw.init = &(struct clk_init_data){
  413.         .name = "sdc1_p_clk",
  414.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  415.         .num_parents = 1,
  416.         .ops = &clk_gate_ops,
  417.     },
  418. };
  419.  
  420. static struct clk_gate sdc2_p_clk = {
  421.     .reg = (void __iomem *)0x03bc,
  422.     .bit_idx = 8,
  423.     .hw.init = &(struct clk_init_data){
  424.         .name = "sdc2_p_clk",
  425.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  426.         .num_parents = 1,
  427.         .ops = &clk_gate_ops,
  428.     },
  429. };
  430.  
  431. static struct clk_gate sdc3_p_clk = {
  432.     .reg = (void __iomem *)0x03bc,
  433.     .bit_idx = 27,
  434.     .hw.init = &(struct clk_init_data){
  435.         .name = "sdc3_p_clk",
  436.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  437.         .num_parents = 1,
  438.         .ops = &clk_gate_ops,
  439.     },
  440. };
  441.  
  442. static struct clk_gate sdc4_p_clk = {
  443.     .reg = (void __iomem *)0x03bc,
  444.     .bit_idx = 28,
  445.     .hw.init = &(struct clk_init_data){
  446.         .name = "sdc4_p_clk",
  447.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  448.         .num_parents = 1,
  449.         .ops = &clk_gate_ops,
  450.     },
  451. };
  452.  
  453. static struct clk_gate spi_p_clk = {
  454.     .reg = (void __iomem *)0x03c0,
  455.     .bit_idx = 10,
  456.     .hw.init = &(struct clk_init_data){
  457.         .name = "spi_p_clk",
  458.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  459.         .num_parents = 1,
  460.         .ops = &clk_gate_ops,
  461.     },
  462. };
  463.  
  464. static struct clk_gate tsif_p_clk = {
  465.     .reg = (void __iomem *)0x03bc,
  466.     .bit_idx = 18,
  467.     .hw.init = &(struct clk_init_data){
  468.         .name = "tsif_p_clk",
  469.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  470.         .num_parents = 1,
  471.         .ops = &clk_gate_ops,
  472.     },
  473. };
  474.  
  475. static struct clk_gate uart1dm_p_clk = {
  476.     .reg = (void __iomem *)0x03bc,
  477.     .bit_idx = 17,
  478.     .hw.init = &(struct clk_init_data){
  479.         .name = "uart1dm_p_clk",
  480.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  481.         .num_parents = 1,
  482.         .ops = &clk_gate_ops,
  483.     },
  484. };
  485.  
  486. static struct clk_gate uart2dm_p_clk = {
  487.     .reg = (void __iomem *)0x03bc,
  488.     .bit_idx = 26,
  489.     .hw.init = &(struct clk_init_data){
  490.         .name = "uart2dm_p_clk",
  491.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  492.         .num_parents = 1,
  493.         .ops = &clk_gate_ops,
  494.     },
  495. };
  496.  
  497. static struct clk_gate usb_hs2_p_clk = {
  498.     .reg = (void __iomem *)0x03c0,
  499.     .bit_idx = 8,
  500.     .hw.init = &(struct clk_init_data){
  501.         .name = "usb_hs2_p_clk",
  502.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  503.         .num_parents = 1,
  504.         .ops = &clk_gate_ops,
  505.     },
  506. };
  507.  
  508. static struct clk_gate usb_hs3_p_clk = {
  509.     .reg = (void __iomem *)0x03c0,
  510.     .bit_idx = 9,
  511.     .hw.init = &(struct clk_init_data){
  512.         .name = "usb_hs3_p_clk",
  513.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  514.         .num_parents = 1,
  515.         .ops = &clk_gate_ops,
  516.     },
  517. };
  518.  
  519. static struct clk_gate usb_hs_p_clk = {
  520.     .reg = (void __iomem *)0x03bc,
  521.     .bit_idx = 25,
  522.     .hw.init = &(struct clk_init_data){
  523.         .name = "usb_hs_p_clk",
  524.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  525.         .num_parents = 1,
  526.         .ops = &clk_gate_ops,
  527.     },
  528. };
  529.  
  530. static struct clk_gate vfe_p_clk = {
  531.     .reg = (void __iomem *)0x03c0,
  532.     .bit_idx = 27,
  533.     .hw.init = &(struct clk_init_data){
  534.         .name = "vfe_p_clk",
  535.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  536.         .num_parents = 1,
  537.         .ops = &clk_gate_ops,
  538.     },
  539. };
  540.  
  541. static const struct freq_tbl ftbl_gcc_csi_clk[] = {
  542.     F(153600000, 1, 2, 2, 5),
  543.     F(192000000, 1, 4, 0, 0),
  544.     F(384000000, 1, 2, 0, 0),
  545.     { }
  546. };
  547.  
  548. static struct clk_rcg csi0_clk = {
  549.     .ns_reg = 0x0174,
  550.     .md_reg = 0x0170,
  551.     .freq_tbl = ftbl_gcc_csi_clk,
  552.     .clkr = {
  553.         .enable_reg = 0x0174,
  554.         .enable_mask = BIT(9),
  555.         .hw.init = &(struct clk_init_data){
  556.             .name = "csi0_clk",
  557.             .parent_data = gcc_msm8255_parent_data,
  558.             .num_parents = 4,
  559.             .ops = &clk_rcg_ops,
  560.         },
  561.     },
  562. };
  563.  
  564. static struct clk_rcg i2c_clk = {
  565.     .ns_reg = 0x0068,
  566.     .clkr = {
  567.         .enable_reg = 0x0068,
  568.         .enable_mask = BIT(9),
  569.         .hw.init = &(struct clk_init_data){
  570.             .name = "i2c_clk",
  571.             .parent_data = gcc_msm8255_parent_data,
  572.             .num_parents = 4,
  573.             .ops = &clk_rcg_ops,
  574.         },
  575.     },
  576. };
  577.  
  578. static struct clk_rcg i2c_2_clk = {
  579.     .ns_reg = 0x02d8,
  580.     .clkr = {
  581.         .enable_reg = 0x02d8,
  582.         .enable_mask = BIT(0),
  583.         .hw.init = &(struct clk_init_data){
  584.             .name = "i2c_2_clk",
  585.             .parent_data = gcc_msm8255_parent_data,
  586.             .num_parents = 4,
  587.             .ops = &clk_rcg_ops,
  588.         },
  589.     },
  590. };
  591.  
  592. static struct clk_rcg qup_i2c_clk = {
  593.     .ns_reg = 0x04f0,
  594.     .clkr = {
  595.         .enable_reg = 0x04f0,
  596.         .enable_mask = BIT(0),
  597.         .hw.init = &(struct clk_init_data){
  598.             .name = "qup_i2c_clk",
  599.             .parent_data = gcc_msm8255_parent_data,
  600.             .num_parents = 4,
  601.             .ops = &clk_rcg_ops,
  602.         },
  603.     },
  604. };
  605.  
  606. static struct clk_rcg uart1_clk = {
  607.     .ns_reg = 0x00e0,
  608.     .clkr = {
  609.         .enable_reg = 0x00e0,
  610.         .enable_mask = BIT(5),
  611.         .hw.init = &(struct clk_init_data){
  612.             .name = "uart1_clk",
  613.             .parent_data = gcc_msm8255_parent_data,
  614.             .num_parents = 4,
  615.             .ops = &clk_rcg_ops,
  616.         },
  617.     },
  618. };
  619.  
  620. static const struct freq_tbl ftbl_gcc_uartdm_clk[] = {
  621.     { 3686400,  3, 5,  3,   200 },
  622.     { 7372800,  3, 5,  3,   100 },
  623.     { 14745600, 3, 5,  3,   50 },
  624.     { 32000000, 3, 5,  25,  192 },
  625.     { 40000000, 3, 5,  125, 768 },
  626.     { 46400000, 3, 5,  145, 768 },
  627.     { 48000000, 3, 5,  25,  128 },
  628.     { 51200000, 3, 5,  5,   24 },
  629.     { 56000000, 3, 5,  175, 768 },
  630.     { 58982400, 3, 5,  6,   25 },
  631.     { 64000000, 1, 7,  1,   3 },
  632.     { }
  633. };
  634.  
  635. static const struct freq_tbl ftbl_gcc_mdh_clk[] = {
  636.     { 49150000,  3, 29, 0, 0 },
  637.     { 92160000,  3, 15, 0, 0 },
  638.     { 122880000, 3, 11, 0, 0 },
  639.     { 184320000, 3, 7,  0, 0 },
  640.     { 245760000, 3, 5,  0, 0 },
  641.     { 368640000, 3, 3,  0, 0 },
  642.     { 384000000, 1, 3,  0, 0 },
  643.     { 445500000, 2, 3,  0, 0 },
  644.     { }
  645. };
  646.  
  647. static struct clk_rcg uart2_clk = {
  648.     .ns_reg = 0x0464,
  649.     .clkr = {
  650.         .enable_reg = 0x0464,
  651.         .enable_mask = BIT(5),
  652.         .hw.init = &(struct clk_init_data){
  653.             .name = "uart2_clk",
  654.             .parent_data = gcc_msm8255_parent_data,
  655.             .num_parents = 4,
  656.             .ops = &clk_rcg_ops,
  657.         },
  658.     },
  659. };
  660.  
  661. static struct clk_rcg uart1dm_clk = {
  662.     .ns_reg = 0x00d4,
  663.     .md_reg = 0x00d0,
  664.     .freq_tbl = ftbl_gcc_uartdm_clk,
  665.     .clkr = {
  666.         .enable_reg = 0x00d4,
  667.         .enable_mask = BIT(9),
  668.         .hw.init = &(struct clk_init_data){
  669.             .name = "uart1dm_clk",
  670.             .parent_data = gcc_msm8255_parent_data,
  671.             .num_parents = 4,
  672.             .ops = &clk_rcg_ops,
  673.         },
  674.     },
  675. };
  676.  
  677. static struct clk_rcg uart2dm_clk = {
  678.     .ns_reg = 0x00dc,
  679.     .md_reg = 0x00d8,
  680.     .freq_tbl = ftbl_gcc_uartdm_clk,
  681.     .clkr = {
  682.         .enable_reg = 0x00dc,
  683.         .enable_mask = BIT(9),
  684.         .hw.init = &(struct clk_init_data){
  685.             .name = "uart2dm_clk",
  686.             .parent_data = gcc_msm8255_parent_data,
  687.             .num_parents = 4,
  688.             .ops = &clk_rcg_ops,
  689.         },
  690.     },
  691. };
  692.  
  693. static const struct freq_tbl ftbl_gcc_grp_clk[] = {
  694.     { 24576000,  0, 1,  0, 0 },
  695.     { 46080000,  3, 31, 0, 0 },
  696.     { 49152000,  3, 29, 0, 0 },
  697.     { 52662875,  3, 27, 0, 0 },
  698.     { 56713846,  3, 25, 0, 0 },
  699.     { 61440000,  3, 23, 0, 0 },
  700.     { 67025454,  3, 21, 0, 0 },
  701.     { 73728000,  3, 19, 0, 0 },
  702.     { 81920000,  3, 17, 0, 0 },
  703.     { 92160000,  3, 15, 0, 0 },
  704.     { 105325714, 3, 13, 0, 0 },
  705.     { 122880000, 3, 11, 0, 0 },
  706.     { 147456000, 3, 9,  0, 0 },
  707.     { 184320000, 3, 7,  0, 0 },
  708.     { 192000000, 1, 7,  0, 0 },
  709.     { 245760000, 3, 5,  0, 0 },
  710.     { }
  711. };
  712.  
  713. static struct clk_rcg emdh_clk = {
  714.     .ns_reg = 0x0050,
  715.     .freq_tbl = ftbl_gcc_mdh_clk,
  716.     .clkr = {
  717.         .enable_reg = 0x0050,
  718.         .enable_mask = BIT(11),
  719.         .hw.init = &(struct clk_init_data){
  720.             .name = "emdh_clk",
  721.             .parent_data = gcc_msm8255_parent_data,
  722.             .num_parents = 4,
  723.             .ops = &clk_rcg_ops,
  724.         },
  725.     },
  726. };
  727.  
  728. static struct clk_rcg pmdh_clk = {
  729.     .ns_reg = 0x008c,
  730.     .freq_tbl = ftbl_gcc_mdh_clk,
  731.     .clkr = {
  732.         .enable_reg = 0x008c,
  733.         .enable_mask = BIT(11),
  734.         .hw.init = &(struct clk_init_data){
  735.             .name = "pmdh_clk",
  736.             .parent_data = gcc_msm8255_parent_data,
  737.             .num_parents = 4,
  738.             .ops = &clk_rcg_ops,
  739.         },
  740.     },
  741. };
  742.  
  743. static struct clk_rcg grp_2d_clk = {
  744.     .ns_reg = 0x0034,
  745.     .freq_tbl = ftbl_gcc_grp_clk,
  746.     .clkr = {
  747.         .enable_reg = 0x0034,
  748.         .enable_mask = BIT(7),
  749.         .hw.init = &(struct clk_init_data){
  750.             .name = "grp_2d_clk",
  751.             .parent_data = gcc_msm8255_parent_data,
  752.             .num_parents = 4,
  753.             .ops = &clk_rcg_ops,
  754.         },
  755.     },
  756. };
  757.  
  758. static struct clk_rcg grp_3d_src_clk = {
  759.     .ns_reg = 0x0084,
  760.     .freq_tbl = ftbl_gcc_grp_clk,
  761.     .clkr = {
  762.         .enable_reg = 0x0084,
  763.         .enable_mask = BIT(11),
  764.         .hw.init = &(struct clk_init_data){
  765.             .name = "grp_3d_src_clk",
  766.             .parent_data = gcc_msm8255_parent_data,
  767.             .num_parents = 4,
  768.             .ops = &clk_rcg_ops,
  769.         },
  770.     },
  771. };
  772.  
  773. static struct clk_gate imem_clk = {
  774.     .reg = (void __iomem *)0x0084,
  775.     .bit_idx = 9,
  776.     .hw.init = &(struct clk_init_data){
  777.         .name = "imem_clk",
  778.         .parent_hws = (const struct clk_hw *[]){ &grp_3d_src_clk.clkr.hw },
  779.         .num_parents = 1,
  780.         .ops = &clk_gate_ops,
  781.     },
  782. };
  783.  
  784. static struct clk_gate grp_3d_clk = {
  785.     .reg = (void __iomem *)0x0084,
  786.     .bit_idx = 7,
  787.     .hw.init = &(struct clk_init_data){
  788.         .name = "grp_3d_clk",
  789.         .parent_hws = (const struct clk_hw *[]){ &grp_3d_src_clk.clkr.hw },
  790.         .num_parents = 1,
  791.         .ops = &clk_gate_ops,
  792.     },
  793. };
  794.  
  795. static const struct freq_tbl ftbl_gcc_sdc1_3_clk[] = {
  796.     { 144000,   0, 1,  1,  171 },
  797.     { 400000,   0, 1,  2,  123 },
  798.     { 16027000, 3, 5,  14, 215 },
  799.     { 17000000, 3, 7,  19, 206 },
  800.     { 20480000, 3, 7,  23, 212 },
  801.     { 24576000, 0, 1,  0,  0 },
  802.     { 49152000, 3, 5,  1,  5 },
  803.     { }
  804. };
  805.  
  806. static struct clk_rcg sdc1_clk = {
  807.     .ns_reg = 0x00a4,
  808.     .md_reg = 0x00a0,
  809.     .freq_tbl = ftbl_gcc_sdc1_3_clk,
  810.     .clkr = {
  811.         .enable_reg = 0x00a4,
  812.         .enable_mask = BIT(9),
  813.         .hw.init = &(struct clk_init_data){
  814.             .name = "sdc1_clk",
  815.             .parent_data = gcc_msm8255_parent_data,
  816.             .num_parents = 4,
  817.             .ops = &clk_rcg_ops,
  818.         },
  819.     },
  820. };
  821.  
  822. static struct clk_rcg sdc3_clk = {
  823.     .ns_reg = 0x00b4,
  824.     .md_reg = 0x00b0,
  825.     .freq_tbl = ftbl_gcc_sdc1_3_clk,
  826.     .clkr = {
  827.         .enable_reg = 0x00b4,
  828.         .enable_mask = BIT(9),
  829.         .hw.init = &(struct clk_init_data){
  830.             .name = "sdc3_clk",
  831.             .parent_data = gcc_msm8255_parent_data,
  832.             .num_parents = 4,
  833.             .ops = &clk_rcg_ops,
  834.         },
  835.     },
  836. };
  837.  
  838. static const struct freq_tbl ftbl_gcc_sdc2_4_clk[] = {
  839.     { 144000,   0, 1,  1,  171 },
  840.     { 400000,   0, 1,  2,  123 },
  841.     { 16027000, 3, 5,  14, 215 },
  842.     { 17000000, 3, 7,  19, 206 },
  843.     { 20480000, 3, 7,  23, 212 },
  844.     { 24576000, 0, 1,  0,  0 },
  845.     { 49152000, 3, 5,  1,  5 },
  846.     { }
  847. };
  848.  
  849. static const struct freq_tbl ftbl_gcc_mdp_core_clk[] = {
  850.     { 24576000,  0, 1,  0, 0 },
  851.     { 46080000,  3, 31, 0, 0 },
  852.     { 49152000,  3, 29, 0, 0 },
  853.     { 52663000,  3, 27, 0, 0 },
  854.     { 92160000,  3, 15, 0, 0 },
  855.     { 122880000, 3, 11, 0, 0 },
  856.     { 147456000, 3, 9,  0, 0 },
  857.     { 153600000, 1, 9,  0, 0 },
  858.     { 192000000, 1, 7,  0, 0 },
  859.     { }
  860. };
  861.  
  862. static struct clk_rcg sdc2_clk = {
  863.     .ns_reg = 0x00ac,
  864.     .md_reg = 0x00a8,
  865.     .freq_tbl = ftbl_gcc_sdc2_4_clk,
  866.     .clkr = {
  867.         .enable_reg = 0x00ac,
  868.         .enable_mask = BIT(9),
  869.         .hw.init = &(struct clk_init_data){
  870.             .name = "sdc2_clk",
  871.             .parent_data = gcc_msm8255_parent_data,
  872.             .num_parents = 4,
  873.             .ops = &clk_rcg_ops,
  874.         },
  875.     },
  876. };
  877.  
  878. static struct clk_rcg sdc4_clk = {
  879.     .ns_reg = 0x00bc,
  880.     .md_reg = 0x00b8,
  881.     .freq_tbl = ftbl_gcc_sdc2_4_clk,
  882.     .clkr = {
  883.         .enable_reg = 0x00bc,
  884.         .enable_mask = BIT(9),
  885.         .hw.init = &(struct clk_init_data){
  886.             .name = "sdc4_clk",
  887.             .parent_data = gcc_msm8255_parent_data,
  888.             .num_parents = 4,
  889.             .ops = &clk_rcg_ops,
  890.         },
  891.     },
  892. };
  893.  
  894. static struct clk_rcg mdp_clk = {
  895.     .ns_reg = 0x014c,
  896.     .freq_tbl = ftbl_gcc_mdp_core_clk,
  897.     .clkr = {
  898.         .enable_reg = 0x014c,
  899.         .enable_mask = BIT(9),
  900.         .hw.init = &(struct clk_init_data){
  901.             .name = "mdp_clk",
  902.             .parent_data = gcc_msm8255_parent_data,
  903.             .num_parents = 4,
  904.             .ops = &clk_rcg_ops,
  905.         },
  906.     },
  907. };
  908.  
  909. static const struct freq_tbl ftbl_gcc_mdp_lcdc_clk[] = {
  910.     { 24576000, 0, 1, 0, 0 },
  911.     { 30720000, 3, 7, 1, 6 },
  912.     { 32768000, 3, 5, 2, 15 },
  913.     { 40960000, 3, 3, 1, 9 },
  914.     { 73728000, 3, 3, 1, 5 },
  915.     { }
  916. };
  917.  
  918. static const struct freq_tbl ftbl_gcc_mdp_vsync_clk[] = {
  919.     { 24576000, 0, 1, 0, 0 },
  920.     { }
  921. };
  922.  
  923. static const struct freq_tbl ftbl_gcc_mi2s_codec_clk[] = {
  924.     { 2048000,  0, 7, 1, 3 },
  925.     { 12288000, 0, 3, 0, 0 },
  926.     { }
  927. };
  928.  
  929. static const struct freq_tbl ftbl_gcc_mi2s_clk[] = {
  930.     { 12288000, 0, 3, 0, 0 },
  931.     { }
  932. };
  933.  
  934. static const struct freq_tbl ftbl_gcc_sdac_clk[] = {
  935.     { 256000,   0, 7,  1,   24 },
  936.     { 352800,   0, 1,  147, 10240 },
  937.     { 384000,   0, 7,  1,   16 },
  938.     { 512000,   0, 7,  1,   12 },
  939.     { 705600,   0, 1,  147, 5120 },
  940.     { 768000,   0, 7,  1,   8 },
  941.     { 1024000,  0, 7,  1,   6 },
  942.     { 1411200,  0, 1,  147, 2560 },
  943.     { 1536000,  0, 7,  1,   4 },
  944.     { }
  945. };
  946.  
  947. static const struct freq_tbl ftbl_gcc_tv_clk[] = {
  948.     { 27000000, 2, 3,  2, 33 },
  949.     { 74250000, 2, 3,  1, 6 },
  950.     { }
  951. };
  952.  
  953. static const struct freq_tbl ftbl_gcc_usb_clk[] = {
  954.     { 60000000, 1, 3,  5, 32 },
  955.     { }
  956. };
  957.  
  958. static struct clk_rcg sdac_clk = {
  959.     .ns_reg = 0x009c,
  960.     .md_reg = 0x0098,
  961.     .freq_tbl = ftbl_gcc_sdac_clk,
  962.     .clkr = {
  963.         .enable_reg = 0x009c,
  964.         .enable_mask = BIT(9),
  965.         .hw.init = &(struct clk_init_data){
  966.             .name = "sdac_clk",
  967.             .parent_data = gcc_msm8255_parent_data,
  968.             .num_parents = 4,
  969.             .ops = &clk_rcg_ops,
  970.         },
  971.     },
  972. };
  973.  
  974. static struct clk_gate sdac_m_clk = {
  975.     .reg = (void __iomem *)0x009c,
  976.     .bit_idx = 12,
  977.     .hw.init = &(struct clk_init_data){
  978.         .name = "sdac_m_clk",
  979.         .parent_hws = (const struct clk_hw *[]){ &sdac_clk.clkr.hw },
  980.         .num_parents = 1,
  981.         .ops = &clk_gate_ops,
  982.     },
  983. };
  984.  
  985. static struct clk_rcg tv_clk = {
  986.     .ns_reg = 0x00cc,
  987.     .md_reg = 0x00c8,
  988.     .freq_tbl = ftbl_gcc_tv_clk,
  989.     .clkr = {
  990.         .enable_reg = 0x00cc,
  991.         .enable_mask = BIT(9),
  992.         .hw.init = &(struct clk_init_data){
  993.             .name = "tv_clk",
  994.             .parent_data = gcc_msm8255_parent_data,
  995.             .num_parents = 4,
  996.             .ops = &clk_rcg_ops,
  997.         },
  998.     },
  999. };
  1000.  
  1001. static struct clk_gate hdmi_clk = {
  1002.     .reg = (void __iomem *)0x0484,
  1003.     .bit_idx = 9,
  1004.     .hw.init = &(struct clk_init_data){
  1005.         .name = "hdmi_clk",
  1006.         .parent_hws = (const struct clk_hw *[]){ &tv_clk.clkr.hw },
  1007.         .num_parents = 1,
  1008.         .ops = &clk_gate_ops,
  1009.     },
  1010. };
  1011.  
  1012. static struct clk_gate tv_dac_clk = {
  1013.     .reg = (void __iomem *)0x00cc,
  1014.     .bit_idx = 12,
  1015.     .hw.init = &(struct clk_init_data){
  1016.         .name = "tv_dac_clk",
  1017.         .parent_hws = (const struct clk_hw *[]){ &tv_clk.clkr.hw },
  1018.         .num_parents = 1,
  1019.         .ops = &clk_gate_ops,
  1020.     },
  1021. };
  1022.  
  1023. static struct clk_gate tv_enc_clk = {
  1024.     .reg = (void __iomem *)0x00cc,
  1025.     .bit_idx = 9,
  1026.     .hw.init = &(struct clk_init_data){
  1027.         .name = "tv_enc_clk",
  1028.         .parent_hws = (const struct clk_hw *[]){ &tv_clk.clkr.hw },
  1029.         .num_parents = 1,
  1030.         .ops = &clk_gate_ops,
  1031.     },
  1032. };
  1033.  
  1034. static struct clk_gate tsif_ref_clk = {
  1035.     .reg = (void __iomem *)0x00c4,
  1036.     .bit_idx = 9,
  1037.     .hw.init = &(struct clk_init_data){
  1038.         .name = "tsif_ref_clk",
  1039.         .parent_hws = (const struct clk_hw *[]){ &tv_clk.clkr.hw },
  1040.         .num_parents = 1,
  1041.         .ops = &clk_gate_ops,
  1042.     },
  1043. };
  1044.  
  1045. static struct clk_rcg usb_hs_src_clk = {
  1046.     .ns_reg = 0x02c0,
  1047.     .md_reg = 0x02bc,
  1048.     .freq_tbl = ftbl_gcc_usb_clk,
  1049.     .clkr = {
  1050.         .enable_reg = 0x02c0,
  1051.         .enable_mask = BIT(11),
  1052.         .hw.init = &(struct clk_init_data){
  1053.             .name = "usb_hs_src_clk",
  1054.             .parent_data = gcc_msm8255_parent_data,
  1055.             .num_parents = 4,
  1056.             .ops = &clk_rcg_ops,
  1057.         },
  1058.     },
  1059. };
  1060.  
  1061. static struct clk_gate usb_hs_clk = {
  1062.     .reg = (void __iomem *)0x02c0,
  1063.     .bit_idx = 9,
  1064.     .hw.init = &(struct clk_init_data){
  1065.         .name = "usb_hs_clk",
  1066.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1067.         .num_parents = 1,
  1068.         .ops = &clk_gate_ops,
  1069.     },
  1070. };
  1071.  
  1072. static struct clk_gate usb_hs_core_clk = {
  1073.     .reg = (void __iomem *)0x02c0,
  1074.     .bit_idx = 13,
  1075.     .hw.init = &(struct clk_init_data){
  1076.         .name = "usb_hs_core_clk",
  1077.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1078.         .num_parents = 1,
  1079.         .ops = &clk_gate_ops,
  1080.     },
  1081. };
  1082.  
  1083. static struct clk_gate usb_hs2_clk = {
  1084.     .reg = (void __iomem *)0x046c,
  1085.     .bit_idx = 9,
  1086.     .hw.init = &(struct clk_init_data){
  1087.         .name = "usb_hs2_clk",
  1088.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1089.         .num_parents = 1,
  1090.         .ops = &clk_gate_ops,
  1091.     },
  1092. };
  1093.  
  1094. static struct clk_gate usb_hs2_core_clk = {
  1095.     .reg = (void __iomem *)0x046c,
  1096.     .bit_idx = 4,
  1097.     .hw.init = &(struct clk_init_data){
  1098.         .name = "usb_hs2_core_clk",
  1099.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1100.         .num_parents = 1,
  1101.         .ops = &clk_gate_ops,
  1102.     },
  1103. };
  1104.  
  1105. static const struct freq_tbl ftbl_gcc_vfe_jpeg_clk[] = {
  1106.     { 24576000,  0, 1, 0, 0 },
  1107.     { 36864000,  3, 7, 1, 5 },
  1108.     { 46080000,  3, 7, 1, 4 },
  1109.     { 61440000,  3, 7, 1, 3 },
  1110.     { 73728000,  3, 3, 1, 5 },
  1111.     { 81920000,  3, 5, 1, 3 },
  1112.     { 92160000,  3, 7, 1, 2 },
  1113.     { 98304000,  3, 5, 2, 5 },
  1114.     { 105326000, 3, 3, 2, 7 },
  1115.     { 122880000, 3, 3, 1, 3 },
  1116.     { 147456000, 3, 3, 2, 5 },
  1117.     { 153600000, 1, 3, 2, 5 },
  1118.     { 192000000, 1, 7, 0, 0 },
  1119.     { }
  1120. };
  1121.  
  1122. static struct clk_gate usb_hs3_clk = {
  1123.     .reg = (void __iomem *)0x0470,
  1124.     .bit_idx = 9,
  1125.     .hw.init = &(struct clk_init_data){
  1126.         .name = "usb_hs3_clk",
  1127.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1128.         .num_parents = 1,
  1129.         .ops = &clk_gate_ops,
  1130.     },
  1131. };
  1132.  
  1133. static struct clk_gate usb_hs3_core_clk = {
  1134.     .reg = (void __iomem *)0x0470,
  1135.     .bit_idx = 4,
  1136.     .hw.init = &(struct clk_init_data){
  1137.         .name = "usb_hs3_core_clk",
  1138.         .parent_hws = (const struct clk_hw *[]){ &usb_hs_src_clk.clkr.hw },
  1139.         .num_parents = 1,
  1140.         .ops = &clk_gate_ops,
  1141.     },
  1142. };
  1143.  
  1144. static struct clk_rcg jpeg_clk = {
  1145.     .ns_reg = 0x0164,
  1146.     .md_reg = 0x0160,
  1147.     .freq_tbl = ftbl_gcc_vfe_jpeg_clk,
  1148.     .clkr = {
  1149.         .enable_reg = 0x0164,
  1150.         .enable_mask = BIT(9),
  1151.         .hw.init = &(struct clk_init_data){
  1152.             .name = "jpeg_clk",
  1153.             .parent_data = gcc_msm8255_parent_data,
  1154.             .num_parents = 4,
  1155.             .ops = &clk_rcg_ops,
  1156.         },
  1157.     },
  1158. };
  1159.  
  1160. static struct clk_rcg vfe_clk = {
  1161.     .ns_reg = 0x0044,
  1162.     .md_reg = 0x0040,
  1163.     .freq_tbl = ftbl_gcc_vfe_jpeg_clk,
  1164.     .clkr = {
  1165.         .enable_reg = 0x0044,
  1166.         .enable_mask = BIT(9),
  1167.         .hw.init = &(struct clk_init_data){
  1168.             .name = "vfe_clk",
  1169.             .parent_data = gcc_msm8255_parent_data,
  1170.             .num_parents = 4,
  1171.             .ops = &clk_rcg_ops,
  1172.         },
  1173.     },
  1174. };
  1175.  
  1176. static struct clk_gate vfe_mdc_clk = {
  1177.     .reg = (void __iomem *)0x0044,
  1178.     .bit_idx = 11,
  1179.     .hw.init = &(struct clk_init_data){
  1180.         .name = "vfe_mdc_clk",
  1181.         .parent_hws = (const struct clk_hw *[]){ &vfe_clk.clkr.hw },
  1182.         .num_parents = 1,
  1183.         .ops = &clk_gate_ops,
  1184.     },
  1185. };
  1186.  
  1187. static struct clk_gate vfe_camif_clk = {
  1188.     .reg = (void __iomem *)0x0044,
  1189.     .bit_idx = 15,
  1190.     .hw.init = &(struct clk_init_data){
  1191.         .name = "vfe_camif_clk",
  1192.         .parent_hws = (const struct clk_hw *[]){ &vfe_clk.clkr.hw },
  1193.         .num_parents = 1,
  1194.         .ops = &clk_gate_ops,
  1195.     },
  1196. };
  1197.  
  1198. static struct clk_gate csi0_vfe_clk = {
  1199.     .reg = (void __iomem *)0x0174,
  1200.     .bit_idx = 15,
  1201.     .hw.init = &(struct clk_init_data){
  1202.         .name = "csi0_vfe_clk",
  1203.         .parent_hws = (const struct clk_hw *[]){ &vfe_clk.clkr.hw },
  1204.         .num_parents = 1,
  1205.         .ops = &clk_gate_ops,
  1206.     },
  1207. };
  1208.  
  1209. // i must remember mdp4... i must remember mdp4...
  1210. // anyway heres a freq table, get ready for 4square
  1211. static const struct freq_tbl ftbl_mdp_clk[] = {
  1212.     { 24576000,  0, 1, 0, 0 },
  1213.     { 61440000,  3, 7, 1, 3 },
  1214.     { 81920000,  3, 5, 1, 3 },
  1215.     { 122880000, 3, 5, 1, 2 },
  1216.     { 153600000, 1, 1, 1, 5 },
  1217.     { }
  1218. };
  1219.  
  1220. static const struct freq_tbl ftbl_gcc_cam_clk[] = {
  1221.     { 6000000,  1, 7,  1, 32 },
  1222.     { 8000000,  1, 7,  1, 24 },
  1223.     { 12000000, 1, 7,  1, 16 },
  1224.     { 16000000, 1, 7,  1, 12 },
  1225.     { 19200000, 1, 7,  1, 10 },
  1226.     { 24000000, 1, 7,  1, 8 },
  1227.     { 32000000, 1, 7,  1, 6 },
  1228.     { 48000000, 1, 7,  1, 4 },
  1229.     { 64000000, 1, 7,  1, 3 },
  1230.     { }
  1231. };
  1232.  
  1233. static const struct freq_tbl ftbl_gcc_vpe_clk[] = {
  1234.     { 24576000,  0, 1, 0, 0 },
  1235.     { 30720000,  3, 7, 1, 6 },
  1236.     { 61440000,  3, 7, 1, 3 },
  1237.     { 81920000,  3, 5, 1, 3 },
  1238.     { 122880000, 3, 5, 1, 2 },
  1239.     { 147456000, 3, 1, 1, 5 },
  1240.     { 153600000, 1, 1, 1, 5 },
  1241.     { }
  1242. };
  1243.  
  1244. static const struct freq_tbl ftbl_gcc_mfc_clk[] = {
  1245.     { 24576000,  0, 1, 0, 0 },
  1246.     { 30720000,  3, 7, 1, 6 },
  1247.     { 61440000,  3, 7, 1, 3 },
  1248.     { 81920000,  3, 5, 1, 3 },
  1249.     { 122880000, 3, 5, 1, 2 },
  1250.     { 147456000, 3, 1, 1, 5 },
  1251.     { 153600000, 1, 1, 1, 5 },
  1252.     { 170667000, 1, 1, 2, 9 },
  1253.     { }
  1254. };
  1255.  
  1256. static struct clk_rcg cam_m_clk = {
  1257.     .ns_reg = 0x0374,
  1258.     .md_reg = 0x0370,
  1259.     .freq_tbl = ftbl_gcc_cam_clk,
  1260.     .clkr = {
  1261.         .enable_reg = 0x0374,
  1262.         .enable_mask = BIT(9),
  1263.         .hw.init = &(struct clk_init_data){
  1264.             .name = "cam_m_clk",
  1265.             .parent_data = gcc_msm8255_parent_data,
  1266.             .num_parents = 4,
  1267.             .ops = &clk_rcg_ops,
  1268.         },
  1269.     },
  1270. };
  1271.  
  1272. static struct clk_rcg vpe_clk = {
  1273.     .ns_reg = 0x015c,
  1274.     .md_reg = 0x0158,
  1275.     .freq_tbl = ftbl_gcc_vpe_clk,
  1276.     .clkr = {
  1277.         .enable_reg = 0x015c,
  1278.         .enable_mask = BIT(9),
  1279.         .hw.init = &(struct clk_init_data){
  1280.             .name = "vpe_clk",
  1281.             .parent_data = gcc_msm8255_parent_data,
  1282.             .num_parents = 4,
  1283.             .ops = &clk_rcg_ops,
  1284.         },
  1285.     },
  1286. };
  1287.  
  1288. static struct clk_rcg mfc_clk = {
  1289.     .ns_reg = 0x0154,
  1290.     .md_reg = 0x0150,
  1291.     .freq_tbl = ftbl_gcc_mfc_clk,
  1292.     .clkr = {
  1293.         .enable_reg = 0x0154,
  1294.         .enable_mask = BIT(9),
  1295.         .hw.init = &(struct clk_init_data){
  1296.             .name = "mfc_clk",
  1297.             .parent_data = gcc_msm8255_parent_data,
  1298.             .num_parents = 4,
  1299.             .ops = &clk_rcg_ops,
  1300.         },
  1301.     },
  1302. };
  1303.  
  1304. static const struct freq_tbl ftbl_gcc_spi_clk[] = {
  1305.     { 9963243,  3, 5, 2, 37 },
  1306.     { 24576000, 0, 1, 0, 0 },
  1307.     { 26331429, 3, 5, 1, 7 },
  1308.     { }
  1309. };
  1310.  
  1311. static const struct freq_tbl ftbl_gcc_lpa_codec_clk[] = {
  1312.     { 1, 1, 1, 0, 0 },
  1313.     { 2, 2, 1, 0, 0 },
  1314.     { 3, 3, 1, 0, 0 },
  1315.     { 4, 4, 1, 0, 0 },
  1316.     { }
  1317. };
  1318.  
  1319. static const struct freq_tbl ftbl_gcc_mdc_clk[] = {
  1320.     { 1, 0, 1, 0, 0 },
  1321.     { }
  1322. };
  1323.  
  1324. static struct clk_gate mfc_div2_clk = {
  1325.     .reg = (void __iomem *)0x0154,
  1326.     .bit_idx = 15,
  1327.     .hw.init = &(struct clk_init_data){
  1328.         .name = "mfc_div2_clk",
  1329.         .parent_hws = (const struct clk_hw *[]){ &mfc_clk.clkr.hw },
  1330.         .num_parents = 1,
  1331.         .ops = &clk_gate_ops,
  1332.     },
  1333. };
  1334.  
  1335. static struct clk_rcg spi_clk = {
  1336.     .ns_reg = 0x02c8,
  1337.     .md_reg = 0x02c4,
  1338.     .freq_tbl = ftbl_gcc_spi_clk,
  1339.     .clkr = {
  1340.         .enable_reg = 0x02c8,
  1341.         .enable_mask = BIT(9),
  1342.         .hw.init = &(struct clk_init_data){
  1343.             .name = "spi_clk",
  1344.             .parent_data = gcc_msm8255_parent_data,
  1345.             .num_parents = 4,
  1346.             .ops = &clk_rcg_ops,
  1347.         },
  1348.     },
  1349. };
  1350.  
  1351. static struct clk_rcg lpa_codec_clk = {
  1352.     .ns_reg = 0x02e8,
  1353.     .freq_tbl = ftbl_gcc_lpa_codec_clk,
  1354.     .clkr = {
  1355.         .enable_reg = 0x02e8,
  1356.         .enable_mask = BIT(9),
  1357.         .hw.init = &(struct clk_init_data){
  1358.             .name = "lpa_codec_clk",
  1359.             .parent_data = gcc_msm8255_parent_data,
  1360.             .num_parents = 4,
  1361.             .ops = &clk_rcg_ops,
  1362.         },
  1363.     },
  1364. };
  1365.  
  1366. static struct clk_rcg mdc_clk = {
  1367.     .ns_reg = 0x007c,
  1368.     .freq_tbl = ftbl_gcc_mdc_clk,
  1369.     .clkr = {
  1370.         .enable_reg = 0x007c,
  1371.         .enable_mask = BIT(9),
  1372.         .hw.init = &(struct clk_init_data){
  1373.             .name = "mdc_clk",
  1374.             .parent_data = gcc_msm8255_parent_data,
  1375.             .num_parents = 4,
  1376.             .ops = &clk_rcg_ops,
  1377.         },
  1378.     },
  1379. };
  1380.  
  1381. static struct clk_gate lpa_core_clk = {
  1382.     .reg = (void __iomem *)0x02e8,
  1383.     .bit_idx = 5,
  1384.     .hw.init = &(struct clk_init_data){
  1385.         .name = "lpa_core_clk",
  1386.         .parent_hws = (const struct clk_hw *[]){ &glbl_root_clk.hw },
  1387.         .num_parents = 1,
  1388.         .ops = &clk_gate_ops,
  1389.     },
  1390. };
  1391.  
  1392. static __maybe_unused struct clk_gate gcc_msm8255_debug_mux = {
  1393.     .reg = (void __iomem *)0x011c,
  1394.     .bit_idx = 0,
  1395.     .hw.init = &(struct clk_init_data){
  1396.         .name = "gcc_debug_mux",
  1397.         .ops = &clk_gate_ops,
  1398.     },
  1399. };
  1400.  
  1401. static struct clk_regmap *gcc_msm8255_clocks[] = {
  1402.     [PLL1_CLK]              = &pll1_clk.clkr,
  1403.     [PLL2_CLK]              = (struct clk_regmap *)&pll2_clk,
  1404.     [PLL3_CLK]              = &pll3_clk.clkr,
  1405.     [PLL4_CLK]              = &pll4_clk.clkr,
  1406.     [GLBL_ROOT_CLK]         = (struct clk_regmap *)&glbl_root_clk,
  1407.     [AXI_LI_APPS_CLK]       = (struct clk_regmap *)&axi_li_apps_clk,
  1408.     [AXI_LI_ADSP_A_CLK]     = (struct clk_regmap *)&axi_li_adsp_a_clk,
  1409.     [AXI_LI_JPEG_CLK]       = (struct clk_regmap *)&axi_li_jpeg_clk,
  1410.     [AXI_LI_VFE_CLK]        = (struct clk_regmap *)&axi_li_vfe_clk,
  1411.     [AXI_MDP_CLK]           = (struct clk_regmap *)&axi_mdp_clk,
  1412.     [AXI_LI_VG_CLK]         = (struct clk_regmap *)&axi_li_vg_clk,
  1413.     [AXI_GRP_2D_CLK]        = (struct clk_regmap *)&axi_grp_2d_clk,
  1414.     [AXI_LI_GRP_CLK]        = (struct clk_regmap *)&axi_li_grp_clk,
  1415.     [AXI_MFC_CLK]           = (struct clk_regmap *)&axi_mfc_clk,
  1416.     [AXI_ROTATOR_CLK]       = (struct clk_regmap *)&axi_rotator_clk,
  1417.     [AXI_VPE_CLK]           = (struct clk_regmap *)&axi_vpe_clk,
  1418.     [ADM_CLK]               = (struct clk_regmap *)&adm_clk,
  1419.     [ADM_P_CLK]             = (struct clk_regmap *)&adm_p_clk,
  1420.     [CE_CLK]                = (struct clk_regmap *)&ce_clk,
  1421.     [CAMIF_PAD_P_CLK]       = (struct clk_regmap *)&camif_pad_p_clk,
  1422.     [CSI0_P_CLK]            = (struct clk_regmap *)&csi0_p_clk,
  1423.     [EMDH_P_CLK]            = (struct clk_regmap *)&emdh_p_clk,
  1424.     [GRP_2D_P_CLK]          = (struct clk_regmap *)&grp_2d_p_clk,
  1425.     [GRP_3D_P_CLK]          = (struct clk_regmap *)&grp_3d_p_clk,
  1426.     [JPEG_P_CLK]            = (struct clk_regmap *)&jpeg_p_clk,
  1427.     [LPA_P_CLK]             = (struct clk_regmap *)&lpa_p_clk,
  1428.     [MDP_P_CLK]             = (struct clk_regmap *)&mdp_p_clk,
  1429.     [MFC_P_CLK]             = (struct clk_regmap *)&mfc_p_clk,
  1430.     [PMDH_P_CLK]            = (struct clk_regmap *)&pmdh_p_clk,
  1431.     [ROTATOR_IMEM_CLK]      = (struct clk_regmap *)&rotator_imem_clk,
  1432.     [ROTATOR_P_CLK]         = (struct clk_regmap *)&rotator_p_clk,
  1433.     [SDC1_P_CLK]            = (struct clk_regmap *)&sdc1_p_clk,
  1434.     [SDC2_P_CLK]            = (struct clk_regmap *)&sdc2_p_clk,
  1435.     [SDC3_P_CLK]            = (struct clk_regmap *)&sdc3_p_clk,
  1436.     [SDC4_P_CLK]            = (struct clk_regmap *)&sdc4_p_clk,
  1437.     [SPI_P_CLK]             = (struct clk_regmap *)&spi_p_clk,
  1438.     [TSIF_P_CLK]            = (struct clk_regmap *)&tsif_p_clk,
  1439.     [UART1DM_P_CLK]         = (struct clk_regmap *)&uart1dm_p_clk,
  1440.     [UART2DM_P_CLK]         = (struct clk_regmap *)&uart2dm_p_clk,
  1441.     [USB_HS2_P_CLK]         = (struct clk_regmap *)&usb_hs2_p_clk,
  1442.     [USB_HS3_P_CLK]         = (struct clk_regmap *)&usb_hs3_p_clk,
  1443.     [USB_HS_P_CLK]          = (struct clk_regmap *)&usb_hs_p_clk,
  1444.     [VFE_P_CLK]             = (struct clk_regmap *)&vfe_p_clk,
  1445.     [CSI0_CLK]              = &csi0_clk.clkr,
  1446.     [I2C_CLK]               = &i2c_clk.clkr,
  1447.     [I2C_2_CLK]             = &i2c_2_clk.clkr,
  1448.     [QUP_I2C_CLK]           = &qup_i2c_clk.clkr,
  1449.     [UART1_CLK]             = &uart1_clk.clkr,
  1450.     [UART2_CLK]             = &uart2_clk.clkr,
  1451.     [UART1DM_CLK]           = &uart1dm_clk.clkr,
  1452.     [UART2DM_CLK]           = &uart2dm_clk.clkr,
  1453.     [EMDH_CLK]              = &emdh_clk.clkr,
  1454.     [PMDH_CLK]              = &pmdh_clk.clkr,
  1455.     [GRP_2D_CLK]            = &grp_2d_clk.clkr,
  1456.     [GRP_3D_SRC_CLK]        = &grp_3d_src_clk.clkr,
  1457.     [GRP_3D_CLK]            = (struct clk_regmap *)&grp_3d_clk,
  1458.     [IMEM_CLK]              = (struct clk_regmap *)&imem_clk,
  1459.     [SDC1_CLK]              = &sdc1_clk.clkr,
  1460.     [SDC3_CLK]              = &sdc3_clk.clkr,
  1461.     [SDC2_CLK]              = &sdc2_clk.clkr,
  1462.     [SDC4_CLK]              = &sdc4_clk.clkr,
  1463.     [MDP_CLK]               = &mdp_clk.clkr,
  1464.     [MDP_LCDC_PCLK_CLK]     = &mdp_lcdc_pclk_clk.clkr,
  1465.     [MDP_LCDC_PAD_PCLK_CLK] = (struct clk_regmap *)&mdp_lcdc_pad_pclk_clk,
  1466.     [MDP_VSYNC_CLK]         = &mdp_vsync_clk.clkr,
  1467.     [MI2S_CODEC_RX_M_CLK]   = &mi2s_codec_rx_m_clk.clkr,
  1468.     [MI2S_CODEC_RX_S_CLK]   = (struct clk_regmap *)&mi2s_codec_rx_s_clk,
  1469.     [MI2S_CODEC_TX_M_CLK]   = &mi2s_codec_tx_m_clk.clkr,
  1470.     [MI2S_CODEC_TX_S_CLK]   = (struct clk_regmap *)&mi2s_codec_tx_s_clk,
  1471.     [MI2S_M_CLK]            = &mi2s_m_clk.clkr,
  1472.     [MI2S_S_CLK]            = (struct clk_regmap *)&mi2s_s_clk,
  1473.     [SDAC_CLK]              = &sdac_clk.clkr,
  1474.     [SDAC_M_CLK]            = (struct clk_regmap *)&sdac_m_clk,
  1475.     [TV_CLK]                = &tv_clk.clkr,
  1476.     [HDMI_CLK]              = (struct clk_regmap *)&hdmi_clk,
  1477.     [TV_DAC_CLK]            = (struct clk_regmap *)&tv_dac_clk,
  1478.     [TV_ENC_CLK]            = (struct clk_regmap *)&tv_enc_clk,
  1479.     [TSIF_REF_CLK]          = (struct clk_regmap *)&tsif_ref_clk,
  1480.     [USB_HS_SRC_CLK]        = &usb_hs_src_clk.clkr,
  1481.     [USB_HS_CLK]            = (struct clk_regmap *)&usb_hs_clk,
  1482.     [USB_HS_CORE_CLK]       = (struct clk_regmap *)&usb_hs_core_clk,
  1483.     [USB_HS2_CLK]           = (struct clk_regmap *)&usb_hs2_clk,
  1484.     [USB_HS2_CORE_CLK]      = (struct clk_regmap *)&usb_hs2_core_clk,
  1485.     [USB_HS3_CLK]           = (struct clk_regmap *)&usb_hs3_clk,
  1486.     [USB_HS3_CORE_CLK]      = (struct clk_regmap *)&usb_hs3_core_clk,
  1487.     [JPEG_CLK]              = &jpeg_clk.clkr,
  1488.     [VFE_CLK]               = &vfe_clk.clkr,
  1489.     [VFE_MDC_CLK]           = (struct clk_regmap *)&vfe_mdc_clk,
  1490.     [VFE_CAMIF_CLK]         = (struct clk_regmap *)&vfe_camif_clk,
  1491.     [CSI0_VFE_CLK]          = (struct clk_regmap *)&csi0_vfe_clk,
  1492.     [CAM_M_CLK]             = &cam_m_clk.clkr,
  1493.     [VPE_CLK]               = &vpe_clk.clkr,
  1494.     [MFC_CLK]               = &mfc_clk.clkr,
  1495.     [MFC_DIV2_CLK]          = (struct clk_regmap *)&mfc_div2_clk,
  1496.     [SPI_CLK]               = &spi_clk.clkr,
  1497.     [LPA_CODEC_CLK]         = &lpa_codec_clk.clkr,
  1498.     [MDC_CLK]               = &mdc_clk.clkr,
  1499.     [LPA_CORE_CLK]          = (struct clk_regmap *)&lpa_core_clk,
  1500.     [ACPU_CLK]              = (struct clk_regmap *)&acpu_clk,
  1501. };
  1502.  
  1503. // time for the translation to CCF from acpuclock-msm7x30.c
  1504. // NOTE: this is for cpu, gpu, whatever.
  1505. #define PLL2_L_VAL_ADDR     0x033c
  1506. #define PLL2_M_VAL_ADDR     0x0340
  1507. #define PLL2_N_VAL_ADDR     0x0344
  1508. #define PLL2_CONFIG_ADDR    0x034c
  1509.  
  1510. static const struct freq_tbl ftbl_gcc_acpu_clk[] = {
  1511.     { 24576000,   0, 1, 0, 0 },
  1512.     { 61440000,   3, 23, 0, 0 },
  1513.     { 122880000,  3, 11, 0, 0 },
  1514.     { 184320000,  3, 9, 0, 0 },
  1515.     { 245760000,  3, 5, 0, 0 },
  1516.     { 368640000,  3, 3, 0, 0 },
  1517.     { 460800000,  1, 1, 0, 0 },
  1518.     { 768000000,  1, 1, 0, 0 },
  1519.     { 806400000,  2, 1, 0, 0 },
  1520.     { 902400000,  2, 1, 0, 0 },
  1521.     { 1017600000, 2, 1, 0, 0 },
  1522.     { 1113600000, 2, 1, 0, 0 },
  1523.     { 1209600000, 2, 1, 0, 0 },
  1524.     { 1305600000, 2, 1, 0, 0 },
  1525.     { 1401600000, 2, 1, 0, 0 },
  1526.     { }
  1527. };
  1528.  
  1529. static struct clk_regmap_mux acpu_clk = {
  1530.     .reg = 0x0004,
  1531.     .shift = 0,
  1532.     .width = 4,
  1533.     .clkr = {
  1534.         .hw.init = &(struct clk_init_data){
  1535.             .name = "acpu_clk",
  1536.             .parent_data = gcc_msm8255_parent_data,
  1537.             .num_parents = 4,
  1538.             .ops = &clk_regmap_mux_closest_ops,
  1539.         },
  1540.     },
  1541. };
  1542.  
  1543. static const struct of_device_id gcc_msm8255_match_table[] = {
  1544.     { .compatible = "qcom,gcc-msm8255" },
  1545.     { }
  1546. };
  1547. MODULE_DEVICE_TABLE(of, gcc_msm8255_match_table);
  1548.  
  1549. static const struct regmap_config gcc_msm8255_regmap_config = {
  1550.     .reg_bits   = 32,
  1551.     .reg_stride = 4,
  1552.     .val_bits   = 32,
  1553.     .max_register   = 0x05ff,
  1554.     .fast_io    = true,
  1555. };
  1556.  
  1557. static const struct qcom_cc_desc gcc_msm8255_desc = {
  1558.     .config     = &gcc_msm8255_regmap_config,
  1559.     .clks       = gcc_msm8255_clocks,
  1560.     .num_clks   = ARRAY_SIZE(gcc_msm8255_clocks),
  1561. };
  1562.  
  1563. static int gcc_msm8255_probe(struct platform_device *pdev)
  1564. {
  1565.     struct device *dev = &pdev->dev;
  1566.     struct regmap *regmap;
  1567.     int ret;
  1568.  
  1569.     regmap = qcom_cc_map(pdev, &gcc_msm8255_desc);
  1570.     if (IS_ERR(regmap))
  1571.         return PTR_ERR(regmap);
  1572.     regmap_update_bits(regmap, 0x03c0, BIT(2), BIT(2));
  1573.     regmap_update_bits(regmap, 0x02c0, BIT(13) | BIT(9), 0);
  1574.     regmap_update_bits(regmap, 0x046c, BIT(9) | BIT(4), 0);
  1575.     regmap_update_bits(regmap, 0x0470, BIT(9) | BIT(4), 0);
  1576.     regmap_update_bits(regmap, 0x0050, GENMASK(18, 17), (0x3 << 17) & GENMASK(18, 17));
  1577.     regmap_update_bits(regmap, 0x008c, GENMASK(18, 17), (0x3 << 17) & GENMASK(18, 17));
  1578.     regmap_update_bits(regmap, 0x02bc, BIT(15), BIT(15));
  1579.     regmap_update_bits(regmap, 0x046c, BIT(6), BIT(6));
  1580.     regmap_update_bits(regmap, 0x0470, BIT(6), BIT(6));
  1581.     ret = qcom_cc_really_probe(dev, &gcc_msm8255_desc, regmap);
  1582.     if (ret)
  1583.         return ret;
  1584.     return 0;
  1585. }
  1586.  
  1587. static struct platform_driver gcc_msm8255_driver = {
  1588.     .probe      = gcc_msm8255_probe,
  1589.     .driver     = {
  1590.         .name   = "gcc-msm8255",
  1591.         .of_match_table = gcc_msm8255_match_table,
  1592.     },
  1593. };
  1594.  
  1595. builtin_platform_driver(gcc_msm8255_driver);
  1596. // do not say that anything here is deprecated,
  1597. // my arm-none-eabi didnt error!
  1598. //
  1599. //               =@@@
  1600. //                  @
  1601. //                _/@
  1602. //               /@@@
  1603. //               |@ @
  1604. //               |@_@
  1605. //               @@@@
  1606. //               &||&
  1607. //  CHECKPATCHPL SPETZNAZ    &&&&.
  1608. //         _         _   &||&&
  1609. //         \\ _________ //   &&&&&     $$$$$
  1610. //      \X         X/    @@&&&   $$$$$$$
  1611. //      /  =\   /=  \    @%%@@$$$$$$$$$
  1612. //      [   0   0   ]    @%%@@$$$$$$$
  1613. //      -------------    @%%@@$$$$
  1614. //      _____________    @@@@@@@
  1615. //      /=\ [       ] /=\@@@@@  @
  1616. //      [ ] [  gin ger  ] [ ]@@@@@= @
  1617. //      [ ] [   bread   ] [ ]@@@@@@&&&&&.
  1618. //      [ ] [   2.3.4   ] [ ]@@@@@@P&&&&&&.
  1619. //      [ ] \___________/ [ ]@@@@@    &&&/
  1620. //      \=/           \=/ @@@/
  1621. //        /=\   /=\   |##|
  1622. //        [ ]   [ ]   |###|
  1623. //        [ ]   [ ]   |####|
  1624. //                [ ]   [ ]   |####|
  1625. //                ===   ===       |#####|
  1626. //--------------------------------|#####|------
  1627.  
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