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  1. From a540854a5b29e1a70adff56a562b8ef06ba03cb6 Mon Sep 17 00:00:00 2001
  2. From: Armbian Builder <[email protected]>
  3. Date: Wed, 20 May 2026 15:33:25 +0000
  4. Subject: [PATCH] Add BSP support files afa7aabb90
  5.  
  6. ---
  7. .../boot/dts/allwinner/sun60iw2p1-cpu-vf.dtsi | 2176 +++++++
  8. arch/arm64/boot/dts/allwinner/sun60iw2p1.dtsi | 5006 +++++++++++++++++
  9. include/dt-bindings/clock/sun20iw5-aon-ccu.h | 43 +
  10. include/dt-bindings/clock/sun20iw5-app-ccu.h | 110 +
  11. include/dt-bindings/clock/sun50iw10-ccu.h | 159 +
  12. include/dt-bindings/clock/sun50iw10-r-ccu.h | 26 +
  13. include/dt-bindings/clock/sun50iw10-rtc.h | 16 +
  14. include/dt-bindings/clock/sun50iw12-ccu.h | 146 +
  15. include/dt-bindings/clock/sun50iw12-r-ccu.h | 33 +
  16. include/dt-bindings/clock/sun50iw12-rtc.h | 16 +
  17. include/dt-bindings/clock/sun50iw9-ccu-rtc.h | 16 +
  18. include/dt-bindings/clock/sun50iw9-ccu.h | 151 +
  19. include/dt-bindings/clock/sun50iw9-r-ccu.h | 20 +
  20. include/dt-bindings/clock/sun55iw3-ccu.h | 207 +
  21. .../dt-bindings/clock/sun55iw3-displl-ccu.h | 19 +
  22. include/dt-bindings/clock/sun55iw3-mcu-ccu.h | 58 +
  23. include/dt-bindings/clock/sun55iw3-r-ccu.h | 40 +
  24. include/dt-bindings/clock/sun55iw3-rtc.h | 24 +
  25. include/dt-bindings/clock/sun55iw5-ccu.h | 151 +
  26. include/dt-bindings/clock/sun55iw5-r-ccu.h | 40 +
  27. include/dt-bindings/clock/sun55iw5-rtc.h | 24 +
  28. include/dt-bindings/clock/sun55iw6-ccu.h | 227 +
  29. include/dt-bindings/clock/sun55iw6-r-ccu.h | 41 +
  30. include/dt-bindings/clock/sun55iw6-rtc.h | 24 +
  31. include/dt-bindings/clock/sun60iw1-ccu.h | 256 +
  32. include/dt-bindings/clock/sun60iw1-dsp-ccu.h | 49 +
  33. include/dt-bindings/clock/sun60iw1-r-ccu.h | 41 +
  34. include/dt-bindings/clock/sun60iw1-rtc.h | 23 +
  35. include/dt-bindings/clock/sun60iw2-ccu.h | 336 ++
  36. .../dt-bindings/clock/sun60iw2-cpupll-ccu.h | 18 +
  37. include/dt-bindings/clock/sun60iw2-r-ccu.h | 49 +
  38. include/dt-bindings/clock/sun60iw2-rtc.h | 26 +
  39. include/dt-bindings/clock/sun65iw1-ccu.h | 188 +
  40. include/dt-bindings/clock/sun65iw1-r-ccu.h | 37 +
  41. include/dt-bindings/clock/sun65iw1-rtc.h | 23 +
  42. include/dt-bindings/clock/sun8iw11-ccu.h | 182 +
  43. include/dt-bindings/clock/sun8iw18-ccu.h | 87 +
  44. include/dt-bindings/clock/sun8iw18-rtc.h | 16 +
  45. include/dt-bindings/clock/sun8iw20-ccu.h | 161 +
  46. include/dt-bindings/clock/sun8iw20-r-ccu.h | 22 +
  47. include/dt-bindings/clock/sun8iw20-rtc.h | 22 +
  48. include/dt-bindings/clock/sun8iw21-ccu.h | 139 +
  49. include/dt-bindings/clock/sun8iw21-r-ccu.h | 16 +
  50. include/dt-bindings/clock/sun8iw21-rtc.h | 24 +
  51. include/dt-bindings/clock/sunxi-ccu.h | 41 +
  52. include/dt-bindings/clock/sunxi-clk.h | 18 +
  53. include/dt-bindings/display/lcd_command.h | 48 +
  54. include/dt-bindings/display/sunxi-lcd.h | 33 +
  55. include/dt-bindings/gpio/sun4i-gpio.h | 28 +
  56. .../dt-bindings/gpio/sun55iw3-share-irq-dt.h | 99 +
  57. include/dt-bindings/gpio/sun8iw21-share-irq.h | 54 +
  58. include/dt-bindings/power/a523-power.h | 18 +
  59. include/dt-bindings/power/r528-power.h | 9 +
  60. include/dt-bindings/power/sun60iw2-power.h | 17 +
  61. include/dt-bindings/power/tv303-power.h | 11 +
  62. include/dt-bindings/power/v851-power.h | 9 +
  63. include/dt-bindings/power/v853-power.h | 9 +
  64. include/dt-bindings/reset/sun20iw5-aon-ccu.h | 12 +
  65. include/dt-bindings/reset/sun20iw5-app-ccu.h | 67 +
  66. include/dt-bindings/reset/sun50iw10-ccu.h | 79 +
  67. include/dt-bindings/reset/sun50iw10-r-ccu.h | 19 +
  68. include/dt-bindings/reset/sun50iw12-ccu.h | 69 +
  69. include/dt-bindings/reset/sun50iw12-r-ccu.h | 23 +
  70. include/dt-bindings/reset/sun50iw9-ccu.h | 77 +
  71. include/dt-bindings/reset/sun50iw9-r-ccu.h | 14 +
  72. include/dt-bindings/reset/sun55iw3-ccu.h | 88 +
  73. include/dt-bindings/reset/sun55iw3-mcu-ccu.h | 31 +
  74. include/dt-bindings/reset/sun55iw3-r-ccu.h | 27 +
  75. include/dt-bindings/reset/sun55iw5-ccu.h | 60 +
  76. include/dt-bindings/reset/sun55iw5-r-ccu.h | 24 +
  77. include/dt-bindings/reset/sun55iw6-ccu.h | 120 +
  78. include/dt-bindings/reset/sun55iw6-r-ccu.h | 23 +
  79. include/dt-bindings/reset/sun60iw1-ccu.h | 155 +
  80. include/dt-bindings/reset/sun60iw1-dsp-ccu.h | 30 +
  81. include/dt-bindings/reset/sun60iw1-r-ccu.h | 25 +
  82. include/dt-bindings/reset/sun60iw2-ccu.h | 131 +
  83. include/dt-bindings/reset/sun60iw2-r-ccu.h | 25 +
  84. include/dt-bindings/reset/sun65iw1-ccu.h | 86 +
  85. include/dt-bindings/reset/sun65iw1-r-ccu.h | 24 +
  86. include/dt-bindings/reset/sun8iw11-ccu.h | 90 +
  87. include/dt-bindings/reset/sun8iw18-ccu.h | 51 +
  88. include/dt-bindings/reset/sun8iw20-ccu.h | 79 +
  89. include/dt-bindings/reset/sun8iw20-r-ccu.h | 17 +
  90. include/dt-bindings/reset/sun8iw21-ccu.h | 60 +
  91. include/dt-bindings/reset/sun8iw21-r-ccu.h | 14 +
  92. include/dt-bindings/spi/sunxi-spi.h | 18 +
  93. 86 files changed, 12420 insertions(+)
  94. create mode 100644 arch/arm64/boot/dts/allwinner/sun60iw2p1-cpu-vf.dtsi
  95. create mode 100644 arch/arm64/boot/dts/allwinner/sun60iw2p1.dtsi
  96. create mode 100644 include/dt-bindings/clock/sun20iw5-aon-ccu.h
  97. create mode 100644 include/dt-bindings/clock/sun20iw5-app-ccu.h
  98. create mode 100644 include/dt-bindings/clock/sun50iw10-ccu.h
  99. create mode 100644 include/dt-bindings/clock/sun50iw10-r-ccu.h
  100. create mode 100644 include/dt-bindings/clock/sun50iw10-rtc.h
  101. create mode 100644 include/dt-bindings/clock/sun50iw12-ccu.h
  102. create mode 100644 include/dt-bindings/clock/sun50iw12-r-ccu.h
  103. create mode 100644 include/dt-bindings/clock/sun50iw12-rtc.h
  104. create mode 100644 include/dt-bindings/clock/sun50iw9-ccu-rtc.h
  105. create mode 100644 include/dt-bindings/clock/sun50iw9-ccu.h
  106. create mode 100644 include/dt-bindings/clock/sun50iw9-r-ccu.h
  107. create mode 100644 include/dt-bindings/clock/sun55iw3-ccu.h
  108. create mode 100644 include/dt-bindings/clock/sun55iw3-displl-ccu.h
  109. create mode 100644 include/dt-bindings/clock/sun55iw3-mcu-ccu.h
  110. create mode 100644 include/dt-bindings/clock/sun55iw3-r-ccu.h
  111. create mode 100644 include/dt-bindings/clock/sun55iw3-rtc.h
  112. create mode 100644 include/dt-bindings/clock/sun55iw5-ccu.h
  113. create mode 100644 include/dt-bindings/clock/sun55iw5-r-ccu.h
  114. create mode 100644 include/dt-bindings/clock/sun55iw5-rtc.h
  115. create mode 100644 include/dt-bindings/clock/sun55iw6-ccu.h
  116. create mode 100644 include/dt-bindings/clock/sun55iw6-r-ccu.h
  117. create mode 100644 include/dt-bindings/clock/sun55iw6-rtc.h
  118. create mode 100644 include/dt-bindings/clock/sun60iw1-ccu.h
  119. create mode 100644 include/dt-bindings/clock/sun60iw1-dsp-ccu.h
  120. create mode 100644 include/dt-bindings/clock/sun60iw1-r-ccu.h
  121. create mode 100644 include/dt-bindings/clock/sun60iw1-rtc.h
  122. create mode 100644 include/dt-bindings/clock/sun60iw2-ccu.h
  123. create mode 100644 include/dt-bindings/clock/sun60iw2-cpupll-ccu.h
  124. create mode 100644 include/dt-bindings/clock/sun60iw2-r-ccu.h
  125. create mode 100644 include/dt-bindings/clock/sun60iw2-rtc.h
  126. create mode 100644 include/dt-bindings/clock/sun65iw1-ccu.h
  127. create mode 100644 include/dt-bindings/clock/sun65iw1-r-ccu.h
  128. create mode 100644 include/dt-bindings/clock/sun65iw1-rtc.h
  129. create mode 100644 include/dt-bindings/clock/sun8iw11-ccu.h
  130. create mode 100644 include/dt-bindings/clock/sun8iw18-ccu.h
  131. create mode 100644 include/dt-bindings/clock/sun8iw18-rtc.h
  132. create mode 100644 include/dt-bindings/clock/sun8iw20-ccu.h
  133. create mode 100644 include/dt-bindings/clock/sun8iw20-r-ccu.h
  134. create mode 100644 include/dt-bindings/clock/sun8iw20-rtc.h
  135. create mode 100644 include/dt-bindings/clock/sun8iw21-ccu.h
  136. create mode 100644 include/dt-bindings/clock/sun8iw21-r-ccu.h
  137. create mode 100644 include/dt-bindings/clock/sun8iw21-rtc.h
  138. create mode 100644 include/dt-bindings/clock/sunxi-ccu.h
  139. create mode 100644 include/dt-bindings/clock/sunxi-clk.h
  140. create mode 100644 include/dt-bindings/display/lcd_command.h
  141. create mode 100644 include/dt-bindings/display/sunxi-lcd.h
  142. create mode 100644 include/dt-bindings/gpio/sun4i-gpio.h
  143. create mode 100644 include/dt-bindings/gpio/sun55iw3-share-irq-dt.h
  144. create mode 100644 include/dt-bindings/gpio/sun8iw21-share-irq.h
  145. create mode 100644 include/dt-bindings/power/a523-power.h
  146. create mode 100644 include/dt-bindings/power/r528-power.h
  147. create mode 100644 include/dt-bindings/power/sun60iw2-power.h
  148. create mode 100644 include/dt-bindings/power/tv303-power.h
  149. create mode 100644 include/dt-bindings/power/v851-power.h
  150. create mode 100644 include/dt-bindings/power/v853-power.h
  151. create mode 100644 include/dt-bindings/reset/sun20iw5-aon-ccu.h
  152. create mode 100644 include/dt-bindings/reset/sun20iw5-app-ccu.h
  153. create mode 100644 include/dt-bindings/reset/sun50iw10-ccu.h
  154. create mode 100644 include/dt-bindings/reset/sun50iw10-r-ccu.h
  155. create mode 100644 include/dt-bindings/reset/sun50iw12-ccu.h
  156. create mode 100644 include/dt-bindings/reset/sun50iw12-r-ccu.h
  157. create mode 100644 include/dt-bindings/reset/sun50iw9-ccu.h
  158. create mode 100644 include/dt-bindings/reset/sun50iw9-r-ccu.h
  159. create mode 100644 include/dt-bindings/reset/sun55iw3-ccu.h
  160. create mode 100644 include/dt-bindings/reset/sun55iw3-mcu-ccu.h
  161. create mode 100644 include/dt-bindings/reset/sun55iw3-r-ccu.h
  162. create mode 100644 include/dt-bindings/reset/sun55iw5-ccu.h
  163. create mode 100644 include/dt-bindings/reset/sun55iw5-r-ccu.h
  164. create mode 100644 include/dt-bindings/reset/sun55iw6-ccu.h
  165. create mode 100644 include/dt-bindings/reset/sun55iw6-r-ccu.h
  166. create mode 100644 include/dt-bindings/reset/sun60iw1-ccu.h
  167. create mode 100644 include/dt-bindings/reset/sun60iw1-dsp-ccu.h
  168. create mode 100644 include/dt-bindings/reset/sun60iw1-r-ccu.h
  169. create mode 100644 include/dt-bindings/reset/sun60iw2-ccu.h
  170. create mode 100644 include/dt-bindings/reset/sun60iw2-r-ccu.h
  171. create mode 100644 include/dt-bindings/reset/sun65iw1-ccu.h
  172. create mode 100644 include/dt-bindings/reset/sun65iw1-r-ccu.h
  173. create mode 100644 include/dt-bindings/reset/sun8iw11-ccu.h
  174. create mode 100644 include/dt-bindings/reset/sun8iw18-ccu.h
  175. create mode 100644 include/dt-bindings/reset/sun8iw20-ccu.h
  176. create mode 100644 include/dt-bindings/reset/sun8iw20-r-ccu.h
  177. create mode 100644 include/dt-bindings/reset/sun8iw21-ccu.h
  178. create mode 100644 include/dt-bindings/reset/sun8iw21-r-ccu.h
  179. create mode 100644 include/dt-bindings/spi/sunxi-spi.h
  180.  
  181. diff --git a/arch/arm64/boot/dts/allwinner/sun60iw2p1-cpu-vf.dtsi b/arch/arm64/boot/dts/allwinner/sun60iw2p1-cpu-vf.dtsi
  182. new file mode 100644
  183. index 000000000000..023105b45da1
  184. --- /dev/null
  185. +++ b/arch/arm64/boot/dts/allwinner/sun60iw2p1-cpu-vf.dtsi
  186. @@ -0,0 +1,2176 @@
  187. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  188. +/{
  189. + vf_mapping_table: vf_mapping_table {
  190. + vf-version = "V0.9";
  191. + table = <
  192. + 0x00 0x0000
  193. + 0x01 0x0100
  194. + 0x11 0x0101
  195. + 0x02 0x0200
  196. + 0x12 0x0201
  197. + 0x03 0x0300
  198. + 0x04 0x0400
  199. + 0x05 0x0500
  200. + 0x06 0x0600
  201. + 0x14 0x0401
  202. + 0x15 0x0501
  203. + >;
  204. + };
  205. +
  206. + cluster0_opp_table: cluster0-opp-table {
  207. + compatible = "allwinner,sun50i-operating-points";
  208. + opp-shared;
  209. +
  210. + opp@408000000 {
  211. + opp-hz = /bits/ 64 <408000000>;
  212. + clock-latency-ns = <244144>;
  213. + opp-microvolt-vf0000 = <800000>;
  214. + opp-microvolt-vf0100 = <800000>;
  215. + opp-microvolt-vf0200 = <800000>;
  216. + opp-microvolt-vf0300 = <800000>;
  217. + opp-microvolt-vf0400 = <800000>;
  218. + opp-microvolt-vf0500 = <800000>;
  219. + opp-microvolt-vf0600 = <800000>;
  220. + opp-microvolt-vf0401 = <800000>;
  221. + opp-microvolt-vf0501 = <800000>;
  222. + opp-microvolt-26m-vf0000 = <0>;
  223. + opp-microvolt-26m-vf0100 = <0>;
  224. + opp-microvolt-26m-vf0200 = <0>;
  225. + opp-microvolt-26m-vf0300 = <0>;
  226. + opp-microvolt-26m-vf0400 = <0>;
  227. + opp-microvolt-26m-vf0500 = <0>;
  228. + opp-microvolt-26m-vf0600 = <0>;
  229. + opp-microvolt-26m-vf0401 = <0>;
  230. + opp-microvolt-26m-vf0501 = <0>;
  231. + };
  232. +
  233. + opp@720000000 {
  234. + opp-hz = /bits/ 64 <720000000>;
  235. + clock-latency-ns = <244144>;
  236. + opp-microvolt-vf0000 = <800000>;
  237. + opp-microvolt-vf0100 = <0>;
  238. + opp-microvolt-vf0200 = <0>;
  239. + opp-microvolt-vf0300 = <0>;
  240. + opp-microvolt-vf0400 = <0>;
  241. + opp-microvolt-vf0500 = <0>;
  242. + opp-microvolt-vf0600 = <0>;
  243. + opp-microvolt-vf0401 = <0>;
  244. + opp-microvolt-vf0501 = <0>;
  245. + opp-microvolt-26m-vf0000 = <0>;
  246. + opp-microvolt-26m-vf0100 = <0>;
  247. + opp-microvolt-26m-vf0200 = <0>;
  248. + opp-microvolt-26m-vf0300 = <0>;
  249. + opp-microvolt-26m-vf0400 = <0>;
  250. + opp-microvolt-26m-vf0500 = <0>;
  251. + opp-microvolt-26m-vf0600 = <0>;
  252. + opp-microvolt-26m-vf0401 = <0>;
  253. + opp-microvolt-26m-vf0501 = <0>;
  254. + };
  255. +
  256. + opp@792000000 {
  257. + opp-hz = /bits/ 64 <792000000>;
  258. + clock-latency-ns = <244144>;
  259. + opp-microvolt-vf0000 = <0>;
  260. + opp-microvolt-vf0100 = <800000>;
  261. + opp-microvolt-vf0200 = <800000>;
  262. + opp-microvolt-vf0300 = <800000>;
  263. + opp-microvolt-vf0400 = <800000>;
  264. + opp-microvolt-vf0500 = <800000>;
  265. + opp-microvolt-vf0600 = <800000>;
  266. + opp-microvolt-vf0401 = <800000>;
  267. + opp-microvolt-vf0501 = <800000>;
  268. + opp-microvolt-26m-vf0000 = <0>;
  269. + opp-microvolt-26m-vf0100 = <0>;
  270. + opp-microvolt-26m-vf0200 = <0>;
  271. + opp-microvolt-26m-vf0300 = <0>;
  272. + opp-microvolt-26m-vf0400 = <0>;
  273. + opp-microvolt-26m-vf0500 = <0>;
  274. + opp-microvolt-26m-vf0600 = <0>;
  275. + opp-microvolt-26m-vf0401 = <0>;
  276. + opp-microvolt-26m-vf0501 = <0>;
  277. + };
  278. +
  279. + opp@1008000000 {
  280. + opp-hz = /bits/ 64 <1008000000>;
  281. + clock-latency-ns = <244144>;
  282. + opp-microvolt-vf0000 = <800000>;
  283. + opp-microvolt-vf0100 = <800000>;
  284. + opp-microvolt-vf0200 = <800000>;
  285. + opp-microvolt-vf0300 = <800000>;
  286. + opp-microvolt-vf0400 = <800000>;
  287. + opp-microvolt-vf0500 = <800000>;
  288. + opp-microvolt-vf0600 = <800000>;
  289. + opp-microvolt-vf0401 = <800000>;
  290. + opp-microvolt-vf0501 = <800000>;
  291. + opp-microvolt-26m-vf0000 = <0>;
  292. + opp-microvolt-26m-vf0100 = <0>;
  293. + opp-microvolt-26m-vf0200 = <0>;
  294. + opp-microvolt-26m-vf0300 = <0>;
  295. + opp-microvolt-26m-vf0400 = <0>;
  296. + opp-microvolt-26m-vf0500 = <0>;
  297. + opp-microvolt-26m-vf0600 = <0>;
  298. + opp-microvolt-26m-vf0401 = <0>;
  299. + opp-microvolt-26m-vf0501 = <0>;
  300. + };
  301. +
  302. + opp@1104000000 {
  303. + opp-hz = /bits/ 64 <1104000000>;
  304. + clock-latency-ns = <244144>;
  305. + opp-microvolt-vf0000 = <0>;
  306. + opp-microvolt-vf0100 = <800000>;
  307. + opp-microvolt-vf0200 = <0>;
  308. + opp-microvolt-vf0300 = <0>;
  309. + opp-microvolt-vf0400 = <0>;
  310. + opp-microvolt-vf0500 = <0>;
  311. + opp-microvolt-vf0600 = <0>;
  312. + opp-microvolt-vf0401 = <0>;
  313. + opp-microvolt-vf0501 = <0>;
  314. + opp-microvolt-26m-vf0000 = <0>;
  315. + opp-microvolt-26m-vf0100 = <0>;
  316. + opp-microvolt-26m-vf0200 = <0>;
  317. + opp-microvolt-26m-vf0300 = <0>;
  318. + opp-microvolt-26m-vf0400 = <0>;
  319. + opp-microvolt-26m-vf0500 = <0>;
  320. + opp-microvolt-26m-vf0600 = <0>;
  321. + opp-microvolt-26m-vf0401 = <0>;
  322. + opp-microvolt-26m-vf0501 = <0>;
  323. + };
  324. +
  325. + opp@1200000000 {
  326. + opp-hz = /bits/ 64 <1200000000>;
  327. + clock-latency-ns = <244144>;
  328. + opp-microvolt-vf0000 = <800000>;
  329. + opp-microvolt-vf0100 = <850000>;
  330. + opp-microvolt-vf0200 = <800000>;
  331. + opp-microvolt-vf0300 = <800000>;
  332. + opp-microvolt-vf0400 = <800000>;
  333. + opp-microvolt-vf0500 = <800000>;
  334. + opp-microvolt-vf0600 = <800000>;
  335. + opp-microvolt-vf0401 = <800000>;
  336. + opp-microvolt-vf0501 = <800000>;
  337. + opp-microvolt-26m-vf0000 = <0>;
  338. + opp-microvolt-26m-vf0100 = <0>;
  339. + opp-microvolt-26m-vf0200 = <0>;
  340. + opp-microvolt-26m-vf0300 = <0>;
  341. + opp-microvolt-26m-vf0400 = <0>;
  342. + opp-microvolt-26m-vf0500 = <0>;
  343. + opp-microvolt-26m-vf0600 = <0>;
  344. + opp-microvolt-26m-vf0401 = <0>;
  345. + opp-microvolt-26m-vf0501 = <0>;
  346. + };
  347. +
  348. + opp@1296000000 {
  349. + opp-hz = /bits/ 64 <1296000000>;
  350. + clock-latency-ns = <244144>;
  351. + opp-microvolt-vf0000 = <0>;
  352. + opp-microvolt-vf0100 = <900000>;
  353. + opp-microvolt-vf0200 = <800000>;
  354. + opp-microvolt-vf0300 = <0>;
  355. + opp-microvolt-vf0400 = <0>;
  356. + opp-microvolt-vf0500 = <0>;
  357. + opp-microvolt-vf0600 = <0>;
  358. + opp-microvolt-vf0401 = <0>;
  359. + opp-microvolt-vf0501 = <0>;
  360. + opp-microvolt-26m-vf0000 = <0>;
  361. + opp-microvolt-26m-vf0100 = <0>;
  362. + opp-microvolt-26m-vf0200 = <0>;
  363. + opp-microvolt-26m-vf0300 = <0>;
  364. + opp-microvolt-26m-vf0400 = <0>;
  365. + opp-microvolt-26m-vf0500 = <0>;
  366. + opp-microvolt-26m-vf0600 = <0>;
  367. + opp-microvolt-26m-vf0401 = <0>;
  368. + opp-microvolt-26m-vf0501 = <0>;
  369. + };
  370. +
  371. + opp@1392000000 {
  372. + opp-hz = /bits/ 64 <1392000000>;
  373. + clock-latency-ns = <244144>;
  374. + opp-microvolt-vf0000 = <0>;
  375. + opp-microvolt-vf0100 = <950000>;
  376. + opp-microvolt-vf0200 = <850000>;
  377. + opp-microvolt-vf0300 = <860000>;
  378. + opp-microvolt-vf0400 = <840000>;
  379. + opp-microvolt-vf0500 = <800000>;
  380. + opp-microvolt-vf0600 = <840000>;
  381. + opp-microvolt-vf0401 = <800000>;
  382. + opp-microvolt-vf0501 = <800000>;
  383. + opp-microvolt-26m-vf0000 = <0>;
  384. + opp-microvolt-26m-vf0100 = <0>;
  385. + opp-microvolt-26m-vf0200 = <0>;
  386. + opp-microvolt-26m-vf0300 = <0>;
  387. + opp-microvolt-26m-vf0400 = <0>;
  388. + opp-microvolt-26m-vf0500 = <0>;
  389. + opp-microvolt-26m-vf0600 = <0>;
  390. + opp-microvolt-26m-vf0401 = <0>;
  391. + opp-microvolt-26m-vf0501 = <0>;
  392. + };
  393. +
  394. + opp@1416000000 {
  395. + opp-hz = /bits/ 64 <1416000000>;
  396. + clock-latency-ns = <244144>;
  397. + opp-microvolt-vf0000 = <800000>;
  398. + opp-microvolt-vf0100 = <0>;
  399. + opp-microvolt-vf0200 = <0>;
  400. + opp-microvolt-vf0300 = <0>;
  401. + opp-microvolt-vf0400 = <0>;
  402. + opp-microvolt-vf0500 = <0>;
  403. + opp-microvolt-vf0600 = <0>;
  404. + opp-microvolt-vf0401 = <0>;
  405. + opp-microvolt-vf0501 = <0>;
  406. + opp-microvolt-26m-vf0000 = <0>;
  407. + opp-microvolt-26m-vf0100 = <0>;
  408. + opp-microvolt-26m-vf0200 = <0>;
  409. + opp-microvolt-26m-vf0300 = <0>;
  410. + opp-microvolt-26m-vf0400 = <0>;
  411. + opp-microvolt-26m-vf0500 = <0>;
  412. + opp-microvolt-26m-vf0600 = <0>;
  413. + opp-microvolt-26m-vf0401 = <0>;
  414. + opp-microvolt-26m-vf0501 = <0>;
  415. + };
  416. +
  417. + opp@1512000000 {
  418. + opp-hz = /bits/ 64 <1512000000>;
  419. + clock-latency-ns = <244144>;
  420. + opp-microvolt-vf0000 = <0>;
  421. + opp-microvolt-vf0100 = <1000000>;
  422. + opp-microvolt-vf0200 = <900000>;
  423. + opp-microvolt-vf0300 = <0>;
  424. + opp-microvolt-vf0400 = <880000>;
  425. + opp-microvolt-vf0500 = <820000>;
  426. + opp-microvolt-vf0600 = <0>;
  427. + opp-microvolt-vf0401 = <820000>;
  428. + opp-microvolt-vf0501 = <820000>;
  429. + opp-microvolt-26m-vf0000 = <0>;
  430. + opp-microvolt-26m-vf0100 = <0>;
  431. + opp-microvolt-26m-vf0200 = <0>;
  432. + opp-microvolt-26m-vf0300 = <0>;
  433. + opp-microvolt-26m-vf0400 = <0>;
  434. + opp-microvolt-26m-vf0500 = <0>;
  435. + opp-microvolt-26m-vf0600 = <0>;
  436. + opp-microvolt-26m-vf0401 = <0>;
  437. + opp-microvolt-26m-vf0501 = <0>;
  438. + };
  439. +
  440. + opp@1608000000 {
  441. + opp-hz = /bits/ 64 <1608000000>;
  442. + clock-latency-ns = <244144>;
  443. + opp-microvolt-vf0000 = <900000>;
  444. + opp-microvolt-vf0100 = <1050000>;
  445. + opp-microvolt-vf0200 = <950000>;
  446. + opp-microvolt-vf0300 = <0>;
  447. + opp-microvolt-vf0400 = <920000>;
  448. + opp-microvolt-vf0500 = <860000>;
  449. + opp-microvolt-vf0600 = <0>;
  450. + opp-microvolt-vf0401 = <860000>;
  451. + opp-microvolt-vf0501 = <840000>;
  452. + opp-microvolt-26m-vf0000 = <0>;
  453. + opp-microvolt-26m-vf0100 = <0>;
  454. + opp-microvolt-26m-vf0200 = <0>;
  455. + opp-microvolt-26m-vf0300 = <0>;
  456. + opp-microvolt-26m-vf0400 = <0>;
  457. + opp-microvolt-26m-vf0500 = <0>;
  458. + opp-microvolt-26m-vf0600 = <0>;
  459. + opp-microvolt-26m-vf0401 = <0>;
  460. + opp-microvolt-26m-vf0501 = <0>;
  461. + };
  462. +
  463. + opp@1704000000 {
  464. + opp-hz = /bits/ 64 <1704000000>;
  465. + clock-latency-ns = <244144>;
  466. + opp-microvolt-vf0000 = <0>;
  467. + opp-microvolt-vf0100 = <0>;
  468. + opp-microvolt-vf0200 = <1000000>;
  469. + opp-microvolt-vf0300 = <0>;
  470. + opp-microvolt-vf0400 = <960000>;
  471. + opp-microvolt-vf0500 = <900000>;
  472. + opp-microvolt-vf0600 = <0>;
  473. + opp-microvolt-vf0401 = <900000>;
  474. + opp-microvolt-vf0501 = <860000>;
  475. + opp-microvolt-26m-vf0000 = <0>;
  476. + opp-microvolt-26m-vf0100 = <0>;
  477. + opp-microvolt-26m-vf0200 = <0>;
  478. + opp-microvolt-26m-vf0300 = <0>;
  479. + opp-microvolt-26m-vf0400 = <0>;
  480. + opp-microvolt-26m-vf0500 = <0>;
  481. + opp-microvolt-26m-vf0600 = <0>;
  482. + opp-microvolt-26m-vf0401 = <0>;
  483. + opp-microvolt-26m-vf0501 = <0>;
  484. + };
  485. +
  486. + opp@1800000000 {
  487. + opp-hz = /bits/ 64 <1800000000>;
  488. + clock-latency-ns = <244144>;
  489. + opp-microvolt-vf0000 = <1000000>;
  490. + opp-microvolt-vf0100 = <0>;
  491. + opp-microvolt-vf0200 = <1050000>;
  492. + opp-microvolt-vf0300 = <0>;
  493. + opp-microvolt-vf0400 = <1000000>;
  494. + opp-microvolt-vf0500 = <950000>;
  495. + opp-microvolt-vf0600 = <0>;
  496. + opp-microvolt-vf0401 = <950000>;
  497. + opp-microvolt-vf0501 = <900000>;
  498. + opp-microvolt-26m-vf0000 = <0>;
  499. + opp-microvolt-26m-vf0100 = <0>;
  500. + opp-microvolt-26m-vf0200 = <0>;
  501. + opp-microvolt-26m-vf0300 = <0>;
  502. + opp-microvolt-26m-vf0400 = <0>;
  503. + opp-microvolt-26m-vf0500 = <0>;
  504. + opp-microvolt-26m-vf0600 = <0>;
  505. + opp-microvolt-26m-vf0401 = <0>;
  506. + opp-microvolt-26m-vf0501 = <0>;
  507. + };
  508. +
  509. + opp@416000000 {
  510. + opp-hz = /bits/ 64 <416000000>;
  511. + clock-latency-ns = <244144>;
  512. + opp-microvolt-vf0000 = <0>;
  513. + opp-microvolt-vf0100 = <0>;
  514. + opp-microvolt-vf0200 = <0>;
  515. + opp-microvolt-vf0300 = <0>;
  516. + opp-microvolt-vf0400 = <0>;
  517. + opp-microvolt-vf0500 = <0>;
  518. + opp-microvolt-vf0600 = <0>;
  519. + opp-microvolt-vf0401 = <0>;
  520. + opp-microvolt-vf0501 = <0>;
  521. + opp-microvolt-26m-vf0000 = <800000>;
  522. + opp-microvolt-26m-vf0100 = <800000>;
  523. + opp-microvolt-26m-vf0200 = <800000>;
  524. + opp-microvolt-26m-vf0300 = <800000>;
  525. + opp-microvolt-26m-vf0400 = <800000>;
  526. + opp-microvolt-26m-vf0500 = <800000>;
  527. + opp-microvolt-26m-vf0600 = <800000>;
  528. + opp-microvolt-26m-vf0401 = <800000>;
  529. + opp-microvolt-26m-vf0501 = <800000>;
  530. + };
  531. +
  532. + opp@728000000 {
  533. + opp-hz = /bits/ 64 <728000000>;
  534. + clock-latency-ns = <244144>;
  535. + opp-microvolt-vf0000 = <0>;
  536. + opp-microvolt-vf0100 = <0>;
  537. + opp-microvolt-vf0200 = <0>;
  538. + opp-microvolt-vf0300 = <0>;
  539. + opp-microvolt-vf0400 = <0>;
  540. + opp-microvolt-vf0500 = <0>;
  541. + opp-microvolt-vf0600 = <0>;
  542. + opp-microvolt-vf0401 = <0>;
  543. + opp-microvolt-vf0501 = <0>;
  544. + opp-microvolt-26m-vf0000 = <800000>;
  545. + opp-microvolt-26m-vf0100 = <0>;
  546. + opp-microvolt-26m-vf0200 = <0>;
  547. + opp-microvolt-26m-vf0300 = <0>;
  548. + opp-microvolt-26m-vf0400 = <0>;
  549. + opp-microvolt-26m-vf0500 = <0>;
  550. + opp-microvolt-26m-vf0600 = <0>;
  551. + opp-microvolt-26m-vf0401 = <0>;
  552. + opp-microvolt-26m-vf0501 = <0>;
  553. + };
  554. +
  555. + opp@780000000 {
  556. + opp-hz = /bits/ 64 <780000000>;
  557. + clock-latency-ns = <244144>;
  558. + opp-microvolt-vf0000 = <0>;
  559. + opp-microvolt-vf0100 = <0>;
  560. + opp-microvolt-vf0200 = <0>;
  561. + opp-microvolt-vf0300 = <0>;
  562. + opp-microvolt-vf0400 = <0>;
  563. + opp-microvolt-vf0500 = <0>;
  564. + opp-microvolt-vf0600 = <0>;
  565. + opp-microvolt-vf0401 = <0>;
  566. + opp-microvolt-vf0501 = <0>;
  567. + opp-microvolt-26m-vf0000 = <0>;
  568. + opp-microvolt-26m-vf0100 = <800000>;
  569. + opp-microvolt-26m-vf0200 = <800000>;
  570. + opp-microvolt-26m-vf0300 = <800000>;
  571. + opp-microvolt-26m-vf0400 = <800000>;
  572. + opp-microvolt-26m-vf0500 = <800000>;
  573. + opp-microvolt-26m-vf0600 = <800000>;
  574. + opp-microvolt-26m-vf0401 = <800000>;
  575. + opp-microvolt-26m-vf0501 = <800000>;
  576. + };
  577. +
  578. + opp@1014000000 {
  579. + opp-hz = /bits/ 64 <1014000000>;
  580. + clock-latency-ns = <244144>;
  581. + opp-microvolt-vf0000 = <0>;
  582. + opp-microvolt-vf0100 = <0>;
  583. + opp-microvolt-vf0200 = <0>;
  584. + opp-microvolt-vf0300 = <0>;
  585. + opp-microvolt-vf0400 = <0>;
  586. + opp-microvolt-vf0500 = <0>;
  587. + opp-microvolt-vf0600 = <0>;
  588. + opp-microvolt-vf0401 = <0>;
  589. + opp-microvolt-vf0501 = <0>;
  590. + opp-microvolt-26m-vf0000 = <800000>;
  591. + opp-microvolt-26m-vf0100 = <800000>;
  592. + opp-microvolt-26m-vf0200 = <800000>;
  593. + opp-microvolt-26m-vf0300 = <800000>;
  594. + opp-microvolt-26m-vf0400 = <800000>;
  595. + opp-microvolt-26m-vf0500 = <800000>;
  596. + opp-microvolt-26m-vf0600 = <800000>;
  597. + opp-microvolt-26m-vf0401 = <800000>;
  598. + opp-microvolt-26m-vf0501 = <800000>;
  599. + };
  600. +
  601. + opp@1092000000 {
  602. + opp-hz = /bits/ 64 <1092000000>;
  603. + clock-latency-ns = <244144>;
  604. + opp-microvolt-vf0000 = <0>;
  605. + opp-microvolt-vf0100 = <0>;
  606. + opp-microvolt-vf0200 = <0>;
  607. + opp-microvolt-vf0300 = <0>;
  608. + opp-microvolt-vf0400 = <0>;
  609. + opp-microvolt-vf0500 = <0>;
  610. + opp-microvolt-vf0600 = <0>;
  611. + opp-microvolt-vf0401 = <0>;
  612. + opp-microvolt-vf0501 = <0>;
  613. + opp-microvolt-26m-vf0000 = <0>;
  614. + opp-microvolt-26m-vf0100 = <800000>;
  615. + opp-microvolt-26m-vf0200 = <0>;
  616. + opp-microvolt-26m-vf0300 = <0>;
  617. + opp-microvolt-26m-vf0400 = <0>;
  618. + opp-microvolt-26m-vf0500 = <0>;
  619. + opp-microvolt-26m-vf0600 = <0>;
  620. + opp-microvolt-26m-vf0401 = <0>;
  621. + opp-microvolt-26m-vf0501 = <0>;
  622. + };
  623. +
  624. + opp@1196000000 {
  625. + opp-hz = /bits/ 64 <1196000000>;
  626. + clock-latency-ns = <244144>;
  627. + opp-microvolt-vf0000 = <0>;
  628. + opp-microvolt-vf0100 = <0>;
  629. + opp-microvolt-vf0200 = <0>;
  630. + opp-microvolt-vf0300 = <0>;
  631. + opp-microvolt-vf0400 = <0>;
  632. + opp-microvolt-vf0500 = <0>;
  633. + opp-microvolt-vf0600 = <0>;
  634. + opp-microvolt-vf0401 = <0>;
  635. + opp-microvolt-vf0501 = <0>;
  636. + opp-microvolt-26m-vf0000 = <800000>;
  637. + opp-microvolt-26m-vf0100 = <850000>;
  638. + opp-microvolt-26m-vf0200 = <800000>;
  639. + opp-microvolt-26m-vf0300 = <800000>;
  640. + opp-microvolt-26m-vf0400 = <800000>;
  641. + opp-microvolt-26m-vf0500 = <800000>;
  642. + opp-microvolt-26m-vf0600 = <800000>;
  643. + opp-microvolt-26m-vf0401 = <800000>;
  644. + opp-microvolt-26m-vf0501 = <800000>;
  645. + };
  646. +
  647. + opp@1300000000 {
  648. + opp-hz = /bits/ 64 <1300000000>;
  649. + clock-latency-ns = <244144>;
  650. + opp-microvolt-vf0000 = <0>;
  651. + opp-microvolt-vf0100 = <0>;
  652. + opp-microvolt-vf0200 = <0>;
  653. + opp-microvolt-vf0300 = <0>;
  654. + opp-microvolt-vf0400 = <0>;
  655. + opp-microvolt-vf0500 = <0>;
  656. + opp-microvolt-vf0600 = <0>;
  657. + opp-microvolt-vf0401 = <0>;
  658. + opp-microvolt-vf0501 = <0>;
  659. + opp-microvolt-26m-vf0000 = <0>;
  660. + opp-microvolt-26m-vf0100 = <900000>;
  661. + opp-microvolt-26m-vf0200 = <800000>;
  662. + opp-microvolt-26m-vf0300 = <0>;
  663. + opp-microvolt-26m-vf0400 = <0>;
  664. + opp-microvolt-26m-vf0500 = <0>;
  665. + opp-microvolt-26m-vf0600 = <0>;
  666. + opp-microvolt-26m-vf0401 = <0>;
  667. + opp-microvolt-26m-vf0501 = <0>;
  668. + };
  669. +
  670. + opp@1404000000 {
  671. + opp-hz = /bits/ 64 <1404000000>;
  672. + clock-latency-ns = <244144>;
  673. + opp-microvolt-vf0000 = <0>;
  674. + opp-microvolt-vf0100 = <0>;
  675. + opp-microvolt-vf0200 = <0>;
  676. + opp-microvolt-vf0300 = <0>;
  677. + opp-microvolt-vf0400 = <0>;
  678. + opp-microvolt-vf0500 = <0>;
  679. + opp-microvolt-vf0600 = <0>;
  680. + opp-microvolt-vf0401 = <0>;
  681. + opp-microvolt-vf0501 = <0>;
  682. + opp-microvolt-26m-vf0000 = <800000>;
  683. + opp-microvolt-26m-vf0100 = <950000>;
  684. + opp-microvolt-26m-vf0200 = <850000>;
  685. + opp-microvolt-26m-vf0300 = <860000>;
  686. + opp-microvolt-26m-vf0400 = <840000>;
  687. + opp-microvolt-26m-vf0500 = <800000>;
  688. + opp-microvolt-26m-vf0600 = <840000>;
  689. + opp-microvolt-26m-vf0401 = <800000>;
  690. + opp-microvolt-26m-vf0501 = <800000>;
  691. + };
  692. +
  693. + opp@1508000000 {
  694. + opp-hz = /bits/ 64 <1508000000>;
  695. + clock-latency-ns = <244144>;
  696. + opp-microvolt-vf0000 = <0>;
  697. + opp-microvolt-vf0100 = <0>;
  698. + opp-microvolt-vf0200 = <0>;
  699. + opp-microvolt-vf0300 = <0>;
  700. + opp-microvolt-vf0400 = <0>;
  701. + opp-microvolt-vf0500 = <0>;
  702. + opp-microvolt-vf0600 = <0>;
  703. + opp-microvolt-vf0401 = <0>;
  704. + opp-microvolt-vf0501 = <0>;
  705. + opp-microvolt-26m-vf0000 = <0>;
  706. + opp-microvolt-26m-vf0100 = <1000000>;
  707. + opp-microvolt-26m-vf0200 = <900000>;
  708. + opp-microvolt-26m-vf0300 = <0>;
  709. + opp-microvolt-26m-vf0400 = <880000>;
  710. + opp-microvolt-26m-vf0500 = <820000>;
  711. + opp-microvolt-26m-vf0600 = <0>;
  712. + opp-microvolt-26m-vf0401 = <820000>;
  713. + opp-microvolt-26m-vf0501 = <820000>;
  714. + };
  715. +
  716. + opp@1586000000 {
  717. + opp-hz = /bits/ 64 <1586000000>;
  718. + clock-latency-ns = <244144>;
  719. + opp-microvolt-vf0000 = <0>;
  720. + opp-microvolt-vf0100 = <0>;
  721. + opp-microvolt-vf0200 = <0>;
  722. + opp-microvolt-vf0300 = <0>;
  723. + opp-microvolt-vf0400 = <0>;
  724. + opp-microvolt-vf0500 = <0>;
  725. + opp-microvolt-vf0600 = <0>;
  726. + opp-microvolt-vf0401 = <0>;
  727. + opp-microvolt-vf0501 = <0>;
  728. + opp-microvolt-26m-vf0000 = <900000>;
  729. + opp-microvolt-26m-vf0100 = <0>;
  730. + opp-microvolt-26m-vf0200 = <0>;
  731. + opp-microvolt-26m-vf0300 = <0>;
  732. + opp-microvolt-26m-vf0400 = <0>;
  733. + opp-microvolt-26m-vf0500 = <0>;
  734. + opp-microvolt-26m-vf0600 = <0>;
  735. + opp-microvolt-26m-vf0401 = <0>;
  736. + opp-microvolt-26m-vf0501 = <0>;
  737. + };
  738. +
  739. + opp@1612000000 {
  740. + opp-hz = /bits/ 64 <1612000000>;
  741. + clock-latency-ns = <244144>;
  742. + opp-microvolt-vf0000 = <0>;
  743. + opp-microvolt-vf0100 = <0>;
  744. + opp-microvolt-vf0200 = <0>;
  745. + opp-microvolt-vf0300 = <0>;
  746. + opp-microvolt-vf0400 = <0>;
  747. + opp-microvolt-vf0500 = <0>;
  748. + opp-microvolt-vf0600 = <0>;
  749. + opp-microvolt-vf0401 = <0>;
  750. + opp-microvolt-vf0501 = <0>;
  751. + opp-microvolt-26m-vf0000 = <0>;
  752. + opp-microvolt-26m-vf0100 = <1050000>;
  753. + opp-microvolt-26m-vf0200 = <950000>;
  754. + opp-microvolt-26m-vf0300 = <0>;
  755. + opp-microvolt-26m-vf0400 = <920000>;
  756. + opp-microvolt-26m-vf0500 = <860000>;
  757. + opp-microvolt-26m-vf0600 = <0>;
  758. + opp-microvolt-26m-vf0401 = <860000>;
  759. + opp-microvolt-26m-vf0501 = <840000>;
  760. + };
  761. +
  762. + opp@1716000000 {
  763. + opp-hz = /bits/ 64 <1716000000>;
  764. + clock-latency-ns = <244144>;
  765. + opp-microvolt-vf0000 = <0>;
  766. + opp-microvolt-vf0100 = <0>;
  767. + opp-microvolt-vf0200 = <0>;
  768. + opp-microvolt-vf0300 = <0>;
  769. + opp-microvolt-vf0400 = <0>;
  770. + opp-microvolt-vf0500 = <0>;
  771. + opp-microvolt-vf0600 = <0>;
  772. + opp-microvolt-vf0401 = <0>;
  773. + opp-microvolt-vf0501 = <0>;
  774. + opp-microvolt-26m-vf0000 = <0>;
  775. + opp-microvolt-26m-vf0100 = <0>;
  776. + opp-microvolt-26m-vf0200 = <1000000>;
  777. + opp-microvolt-26m-vf0300 = <0>;
  778. + opp-microvolt-26m-vf0400 = <960000>;
  779. + opp-microvolt-26m-vf0500 = <900000>;
  780. + opp-microvolt-26m-vf0600 = <0>;
  781. + opp-microvolt-26m-vf0401 = <900000>;
  782. + opp-microvolt-26m-vf0501 = <860000>;
  783. + };
  784. +
  785. + opp@1794000000 {
  786. + opp-hz = /bits/ 64 <1794000000>;
  787. + clock-latency-ns = <244144>;
  788. + opp-microvolt-vf0000 = <0>;
  789. + opp-microvolt-vf0100 = <0>;
  790. + opp-microvolt-vf0200 = <0>;
  791. + opp-microvolt-vf0300 = <0>;
  792. + opp-microvolt-vf0400 = <0>;
  793. + opp-microvolt-vf0500 = <0>;
  794. + opp-microvolt-vf0600 = <0>;
  795. + opp-microvolt-vf0401 = <0>;
  796. + opp-microvolt-vf0501 = <0>;
  797. + opp-microvolt-26m-vf0000 = <1000000>;
  798. + opp-microvolt-26m-vf0100 = <0>;
  799. + opp-microvolt-26m-vf0200 = <1050000>;
  800. + opp-microvolt-26m-vf0300 = <0>;
  801. + opp-microvolt-26m-vf0400 = <1000000>;
  802. + opp-microvolt-26m-vf0500 = <950000>;
  803. + opp-microvolt-26m-vf0600 = <0>;
  804. + opp-microvolt-26m-vf0401 = <950000>;
  805. + opp-microvolt-26m-vf0501 = <900000>;
  806. + };
  807. + };
  808. +
  809. + cluster1_opp_table: cluster1-opp-table {
  810. + compatible = "allwinner,sun50i-operating-points";
  811. + opp-shared;
  812. +
  813. + opp@408000000 {
  814. + opp-hz = /bits/ 64 <408000000>;
  815. + clock-latency-ns = <244144>;
  816. + opp-microvolt-vf0000 = <800000>;
  817. + opp-microvolt-vf0100 = <800000>;
  818. + opp-microvolt-vf0200 = <800000>;
  819. + opp-microvolt-vf0300 = <800000>;
  820. + opp-microvolt-vf0400 = <800000>;
  821. + opp-microvolt-vf0500 = <800000>;
  822. + opp-microvolt-vf0600 = <800000>;
  823. + opp-microvolt-vf0401 = <800000>;
  824. + opp-microvolt-vf0501 = <800000>;
  825. + opp-microvolt-26m-vf0000 = <0>;
  826. + opp-microvolt-26m-vf0100 = <0>;
  827. + opp-microvolt-26m-vf0200 = <0>;
  828. + opp-microvolt-26m-vf0300 = <0>;
  829. + opp-microvolt-26m-vf0400 = <0>;
  830. + opp-microvolt-26m-vf0500 = <0>;
  831. + opp-microvolt-26m-vf0600 = <0>;
  832. + opp-microvolt-26m-vf0401 = <0>;
  833. + opp-microvolt-26m-vf0501 = <0>;
  834. + };
  835. +
  836. + opp@720000000 {
  837. + opp-hz = /bits/ 64 <720000000>;
  838. + clock-latency-ns = <244144>;
  839. + opp-microvolt-vf0000 = <800000>;
  840. + opp-microvolt-vf0100 = <0>;
  841. + opp-microvolt-vf0200 = <0>;
  842. + opp-microvolt-vf0300 = <0>;
  843. + opp-microvolt-vf0400 = <0>;
  844. + opp-microvolt-vf0500 = <0>;
  845. + opp-microvolt-vf0600 = <0>;
  846. + opp-microvolt-vf0401 = <0>;
  847. + opp-microvolt-vf0501 = <0>;
  848. + opp-microvolt-26m-vf0000 = <0>;
  849. + opp-microvolt-26m-vf0100 = <0>;
  850. + opp-microvolt-26m-vf0200 = <0>;
  851. + opp-microvolt-26m-vf0300 = <0>;
  852. + opp-microvolt-26m-vf0400 = <0>;
  853. + opp-microvolt-26m-vf0500 = <0>;
  854. + opp-microvolt-26m-vf0600 = <0>;
  855. + opp-microvolt-26m-vf0401 = <0>;
  856. + opp-microvolt-26m-vf0501 = <0>;
  857. + };
  858. +
  859. + opp@792000000 {
  860. + opp-hz = /bits/ 64 <792000000>;
  861. + clock-latency-ns = <244144>;
  862. + opp-microvolt-vf0000 = <0>;
  863. + opp-microvolt-vf0100 = <800000>;
  864. + opp-microvolt-vf0200 = <800000>;
  865. + opp-microvolt-vf0300 = <800000>;
  866. + opp-microvolt-vf0400 = <800000>;
  867. + opp-microvolt-vf0500 = <800000>;
  868. + opp-microvolt-vf0600 = <800000>;
  869. + opp-microvolt-vf0401 = <800000>;
  870. + opp-microvolt-vf0501 = <800000>;
  871. + opp-microvolt-26m-vf0000 = <0>;
  872. + opp-microvolt-26m-vf0100 = <0>;
  873. + opp-microvolt-26m-vf0200 = <0>;
  874. + opp-microvolt-26m-vf0300 = <0>;
  875. + opp-microvolt-26m-vf0400 = <0>;
  876. + opp-microvolt-26m-vf0500 = <0>;
  877. + opp-microvolt-26m-vf0600 = <0>;
  878. + opp-microvolt-26m-vf0401 = <0>;
  879. + opp-microvolt-26m-vf0501 = <0>;
  880. + };
  881. +
  882. + opp@1008000000 {
  883. + opp-hz = /bits/ 64 <1008000000>;
  884. + clock-latency-ns = <244144>;
  885. + opp-microvolt-vf0000 = <800000>;
  886. + opp-microvolt-vf0100 = <800000>;
  887. + opp-microvolt-vf0200 = <800000>;
  888. + opp-microvolt-vf0300 = <800000>;
  889. + opp-microvolt-vf0400 = <800000>;
  890. + opp-microvolt-vf0500 = <800000>;
  891. + opp-microvolt-vf0600 = <800000>;
  892. + opp-microvolt-vf0401 = <800000>;
  893. + opp-microvolt-vf0501 = <800000>;
  894. + opp-microvolt-26m-vf0000 = <0>;
  895. + opp-microvolt-26m-vf0100 = <0>;
  896. + opp-microvolt-26m-vf0200 = <0>;
  897. + opp-microvolt-26m-vf0300 = <0>;
  898. + opp-microvolt-26m-vf0400 = <0>;
  899. + opp-microvolt-26m-vf0500 = <0>;
  900. + opp-microvolt-26m-vf0600 = <0>;
  901. + opp-microvolt-26m-vf0401 = <0>;
  902. + opp-microvolt-26m-vf0501 = <0>;
  903. + };
  904. +
  905. + opp@1200000000 {
  906. + opp-hz = /bits/ 64 <1200000000>;
  907. + clock-latency-ns = <244144>;
  908. + opp-microvolt-vf0000 = <800000>;
  909. + opp-microvolt-vf0100 = <800000>;
  910. + opp-microvolt-vf0200 = <800000>;
  911. + opp-microvolt-vf0300 = <800000>;
  912. + opp-microvolt-vf0400 = <800000>;
  913. + opp-microvolt-vf0500 = <800000>;
  914. + opp-microvolt-vf0600 = <800000>;
  915. + opp-microvolt-vf0401 = <800000>;
  916. + opp-microvolt-vf0501 = <800000>;
  917. + opp-microvolt-26m-vf0000 = <0>;
  918. + opp-microvolt-26m-vf0100 = <0>;
  919. + opp-microvolt-26m-vf0200 = <0>;
  920. + opp-microvolt-26m-vf0300 = <0>;
  921. + opp-microvolt-26m-vf0400 = <0>;
  922. + opp-microvolt-26m-vf0500 = <0>;
  923. + opp-microvolt-26m-vf0600 = <0>;
  924. + opp-microvolt-26m-vf0401 = <0>;
  925. + opp-microvolt-26m-vf0501 = <0>;
  926. + };
  927. +
  928. + opp@1296000000 {
  929. + opp-hz = /bits/ 64 <1296000000>;
  930. + clock-latency-ns = <244144>;
  931. + opp-microvolt-vf0000 = <0>;
  932. + opp-microvolt-vf0100 = <800000>;
  933. + opp-microvolt-vf0200 = <0>;
  934. + opp-microvolt-vf0300 = <0>;
  935. + opp-microvolt-vf0400 = <0>;
  936. + opp-microvolt-vf0500 = <0>;
  937. + opp-microvolt-vf0600 = <0>;
  938. + opp-microvolt-vf0401 = <0>;
  939. + opp-microvolt-vf0501 = <0>;
  940. + opp-microvolt-26m-vf0000 = <0>;
  941. + opp-microvolt-26m-vf0100 = <0>;
  942. + opp-microvolt-26m-vf0200 = <0>;
  943. + opp-microvolt-26m-vf0300 = <0>;
  944. + opp-microvolt-26m-vf0400 = <0>;
  945. + opp-microvolt-26m-vf0500 = <0>;
  946. + opp-microvolt-26m-vf0600 = <0>;
  947. + opp-microvolt-26m-vf0401 = <0>;
  948. + opp-microvolt-26m-vf0501 = <0>;
  949. + };
  950. +
  951. + opp@1392000000 {
  952. + opp-hz = /bits/ 64 <1392000000>;
  953. + clock-latency-ns = <244144>;
  954. + opp-microvolt-vf0000 = <800000>;
  955. + opp-microvolt-vf0100 = <850000>;
  956. + opp-microvolt-vf0200 = <800000>;
  957. + opp-microvolt-vf0300 = <820000>;
  958. + opp-microvolt-vf0400 = <800000>;
  959. + opp-microvolt-vf0500 = <800000>;
  960. + opp-microvolt-vf0600 = <800000>;
  961. + opp-microvolt-vf0401 = <800000>;
  962. + opp-microvolt-vf0501 = <800000>;
  963. + opp-microvolt-26m-vf0000 = <0>;
  964. + opp-microvolt-26m-vf0100 = <0>;
  965. + opp-microvolt-26m-vf0200 = <0>;
  966. + opp-microvolt-26m-vf0300 = <0>;
  967. + opp-microvolt-26m-vf0400 = <0>;
  968. + opp-microvolt-26m-vf0500 = <0>;
  969. + opp-microvolt-26m-vf0600 = <0>;
  970. + opp-microvolt-26m-vf0401 = <0>;
  971. + opp-microvolt-26m-vf0501 = <0>;
  972. + };
  973. +
  974. + opp@1512000000 {
  975. + opp-hz = /bits/ 64 <1512000000>;
  976. + clock-latency-ns = <244144>;
  977. + opp-microvolt-vf0000 = <800000>;
  978. + opp-microvolt-vf0100 = <900000>;
  979. + opp-microvolt-vf0200 = <800000>;
  980. + opp-microvolt-vf0300 = <860000>;
  981. + opp-microvolt-vf0400 = <820000>;
  982. + opp-microvolt-vf0500 = <800000>;
  983. + opp-microvolt-vf0600 = <800000>;
  984. + opp-microvolt-vf0401 = <800000>;
  985. + opp-microvolt-vf0501 = <800000>;
  986. + opp-microvolt-26m-vf0000 = <0>;
  987. + opp-microvolt-26m-vf0100 = <0>;
  988. + opp-microvolt-26m-vf0200 = <0>;
  989. + opp-microvolt-26m-vf0300 = <0>;
  990. + opp-microvolt-26m-vf0400 = <0>;
  991. + opp-microvolt-26m-vf0500 = <0>;
  992. + opp-microvolt-26m-vf0600 = <0>;
  993. + opp-microvolt-26m-vf0401 = <0>;
  994. + opp-microvolt-26m-vf0501 = <0>;
  995. + };
  996. +
  997. + opp@1608000000 {
  998. + opp-hz = /bits/ 64 <1608000000>;
  999. + clock-latency-ns = <244144>;
  1000. + opp-microvolt-vf0000 = <850000>;
  1001. + opp-microvolt-vf0100 = <950000>;
  1002. + opp-microvolt-vf0200 = <850000>;
  1003. + opp-microvolt-vf0300 = <900000>;
  1004. + opp-microvolt-vf0400 = <840000>;
  1005. + opp-microvolt-vf0500 = <820000>;
  1006. + opp-microvolt-vf0600 = <850000>;
  1007. + opp-microvolt-vf0401 = <820000>;
  1008. + opp-microvolt-vf0501 = <820000>;
  1009. + opp-microvolt-26m-vf0000 = <0>;
  1010. + opp-microvolt-26m-vf0100 = <0>;
  1011. + opp-microvolt-26m-vf0200 = <0>;
  1012. + opp-microvolt-26m-vf0300 = <0>;
  1013. + opp-microvolt-26m-vf0400 = <0>;
  1014. + opp-microvolt-26m-vf0500 = <0>;
  1015. + opp-microvolt-26m-vf0600 = <0>;
  1016. + opp-microvolt-26m-vf0401 = <0>;
  1017. + opp-microvolt-26m-vf0501 = <0>;
  1018. + };
  1019. +
  1020. + opp@1704000000 {
  1021. + opp-hz = /bits/ 64 <1704000000>;
  1022. + clock-latency-ns = <244144>;
  1023. + opp-microvolt-vf0000 = <900000>;
  1024. + opp-microvolt-vf0100 = <1000000>;
  1025. + opp-microvolt-vf0200 = <900000>;
  1026. + opp-microvolt-vf0300 = <0>;
  1027. + opp-microvolt-vf0400 = <870000>;
  1028. + opp-microvolt-vf0500 = <850000>;
  1029. + opp-microvolt-vf0600 = <0>;
  1030. + opp-microvolt-vf0401 = <850000>;
  1031. + opp-microvolt-vf0501 = <840000>;
  1032. + opp-microvolt-26m-vf0000 = <0>;
  1033. + opp-microvolt-26m-vf0100 = <0>;
  1034. + opp-microvolt-26m-vf0200 = <0>;
  1035. + opp-microvolt-26m-vf0300 = <0>;
  1036. + opp-microvolt-26m-vf0400 = <0>;
  1037. + opp-microvolt-26m-vf0500 = <0>;
  1038. + opp-microvolt-26m-vf0600 = <0>;
  1039. + opp-microvolt-26m-vf0401 = <0>;
  1040. + opp-microvolt-26m-vf0501 = <0>;
  1041. + };
  1042. +
  1043. + opp@1800000000 {
  1044. + opp-hz = /bits/ 64 <1800000000>;
  1045. + clock-latency-ns = <244144>;
  1046. + opp-microvolt-vf0000 = <950000>;
  1047. + opp-microvolt-vf0100 = <1050000>;
  1048. + opp-microvolt-vf0200 = <950000>;
  1049. + opp-microvolt-vf0300 = <0>;
  1050. + opp-microvolt-vf0400 = <920000>;
  1051. + opp-microvolt-vf0500 = <900000>;
  1052. + opp-microvolt-vf0600 = <0>;
  1053. + opp-microvolt-vf0401 = <900000>;
  1054. + opp-microvolt-vf0501 = <870000>;
  1055. + opp-microvolt-26m-vf0000 = <0>;
  1056. + opp-microvolt-26m-vf0100 = <0>;
  1057. + opp-microvolt-26m-vf0200 = <0>;
  1058. + opp-microvolt-26m-vf0300 = <0>;
  1059. + opp-microvolt-26m-vf0400 = <0>;
  1060. + opp-microvolt-26m-vf0500 = <0>;
  1061. + opp-microvolt-26m-vf0600 = <0>;
  1062. + opp-microvolt-26m-vf0401 = <0>;
  1063. + opp-microvolt-26m-vf0501 = <0>;
  1064. + };
  1065. +
  1066. + opp@1896000000 {
  1067. + opp-hz = /bits/ 64 <1896000000>;
  1068. + clock-latency-ns = <244144>;
  1069. + opp-microvolt-vf0000 = <0>;
  1070. + opp-microvolt-vf0100 = <0>;
  1071. + opp-microvolt-vf0200 = <1000000>;
  1072. + opp-microvolt-vf0300 = <0>;
  1073. + opp-microvolt-vf0400 = <970000>;
  1074. + opp-microvolt-vf0500 = <940000>;
  1075. + opp-microvolt-vf0600 = <0>;
  1076. + opp-microvolt-vf0401 = <940000>;
  1077. + opp-microvolt-vf0501 = <900000>;
  1078. + opp-microvolt-26m-vf0000 = <0>;
  1079. + opp-microvolt-26m-vf0100 = <0>;
  1080. + opp-microvolt-26m-vf0200 = <0>;
  1081. + opp-microvolt-26m-vf0300 = <0>;
  1082. + opp-microvolt-26m-vf0400 = <0>;
  1083. + opp-microvolt-26m-vf0500 = <0>;
  1084. + opp-microvolt-26m-vf0600 = <0>;
  1085. + opp-microvolt-26m-vf0401 = <0>;
  1086. + opp-microvolt-26m-vf0501 = <0>;
  1087. + };
  1088. +
  1089. + opp@1920000000 {
  1090. + opp-hz = /bits/ 64 <1920000000>;
  1091. + clock-latency-ns = <244144>;
  1092. + opp-microvolt-vf0000 = <1000000>;
  1093. + opp-microvolt-vf0100 = <0>;
  1094. + opp-microvolt-vf0200 = <0>;
  1095. + opp-microvolt-vf0300 = <0>;
  1096. + opp-microvolt-vf0400 = <0>;
  1097. + opp-microvolt-vf0500 = <0>;
  1098. + opp-microvolt-vf0600 = <0>;
  1099. + opp-microvolt-vf0401 = <0>;
  1100. + opp-microvolt-vf0501 = <0>;
  1101. + opp-microvolt-26m-vf0000 = <0>;
  1102. + opp-microvolt-26m-vf0100 = <0>;
  1103. + opp-microvolt-26m-vf0200 = <0>;
  1104. + opp-microvolt-26m-vf0300 = <0>;
  1105. + opp-microvolt-26m-vf0400 = <0>;
  1106. + opp-microvolt-26m-vf0500 = <0>;
  1107. + opp-microvolt-26m-vf0600 = <0>;
  1108. + opp-microvolt-26m-vf0401 = <0>;
  1109. + opp-microvolt-26m-vf0501 = <0>;
  1110. + };
  1111. +
  1112. + opp@1944000000 {
  1113. + opp-hz = /bits/ 64 <1944000000>;
  1114. + clock-latency-ns = <244144>;
  1115. + opp-microvolt-vf0000 = <0>;
  1116. + opp-microvolt-vf0100 = <0>;
  1117. + opp-microvolt-vf0200 = <0>;
  1118. + opp-microvolt-vf0300 = <0>;
  1119. + opp-microvolt-vf0400 = <1000000>;
  1120. + opp-microvolt-vf0500 = <970000>;
  1121. + opp-microvolt-vf0600 = <0>;
  1122. + opp-microvolt-vf0401 = <970000>;
  1123. + opp-microvolt-vf0501 = <930000>;
  1124. + opp-microvolt-26m-vf0000 = <0>;
  1125. + opp-microvolt-26m-vf0100 = <0>;
  1126. + opp-microvolt-26m-vf0200 = <0>;
  1127. + opp-microvolt-26m-vf0300 = <0>;
  1128. + opp-microvolt-26m-vf0400 = <0>;
  1129. + opp-microvolt-26m-vf0500 = <0>;
  1130. + opp-microvolt-26m-vf0600 = <0>;
  1131. + opp-microvolt-26m-vf0401 = <0>;
  1132. + opp-microvolt-26m-vf0501 = <0>;
  1133. + };
  1134. +
  1135. + opp@1992000000 {
  1136. + opp-hz = /bits/ 64 <1992000000>;
  1137. + clock-latency-ns = <244144>;
  1138. + opp-microvolt-vf0000 = <1050000>;
  1139. + opp-microvolt-vf0100 = <0>;
  1140. + opp-microvolt-vf0200 = <0>;
  1141. + opp-microvolt-vf0300 = <0>;
  1142. + opp-microvolt-vf0400 = <1050000>;
  1143. + opp-microvolt-vf0500 = <1000000>;
  1144. + opp-microvolt-vf0600 = <0>;
  1145. + opp-microvolt-vf0401 = <1000000>;
  1146. + opp-microvolt-vf0501 = <960000>;
  1147. + opp-microvolt-26m-vf0000 = <0>;
  1148. + opp-microvolt-26m-vf0100 = <0>;
  1149. + opp-microvolt-26m-vf0200 = <0>;
  1150. + opp-microvolt-26m-vf0300 = <0>;
  1151. + opp-microvolt-26m-vf0400 = <0>;
  1152. + opp-microvolt-26m-vf0500 = <0>;
  1153. + opp-microvolt-26m-vf0600 = <0>;
  1154. + opp-microvolt-26m-vf0401 = <0>;
  1155. + opp-microvolt-26m-vf0501 = <0>;
  1156. + };
  1157. +
  1158. + opp@416000000 {
  1159. + opp-hz = /bits/ 64 <416000000>;
  1160. + clock-latency-ns = <244144>;
  1161. + opp-microvolt-vf0000 = <0>;
  1162. + opp-microvolt-vf0100 = <0>;
  1163. + opp-microvolt-vf0200 = <0>;
  1164. + opp-microvolt-vf0300 = <0>;
  1165. + opp-microvolt-vf0400 = <0>;
  1166. + opp-microvolt-vf0500 = <0>;
  1167. + opp-microvolt-vf0600 = <0>;
  1168. + opp-microvolt-vf0401 = <0>;
  1169. + opp-microvolt-vf0501 = <0>;
  1170. + opp-microvolt-26m-vf0000 = <800000>;
  1171. + opp-microvolt-26m-vf0100 = <800000>;
  1172. + opp-microvolt-26m-vf0200 = <800000>;
  1173. + opp-microvolt-26m-vf0300 = <800000>;
  1174. + opp-microvolt-26m-vf0400 = <800000>;
  1175. + opp-microvolt-26m-vf0500 = <800000>;
  1176. + opp-microvolt-26m-vf0600 = <800000>;
  1177. + opp-microvolt-26m-vf0401 = <800000>;
  1178. + opp-microvolt-26m-vf0501 = <800000>;
  1179. + };
  1180. +
  1181. + opp@728000000 {
  1182. + opp-hz = /bits/ 64 <728000000>;
  1183. + clock-latency-ns = <244144>;
  1184. + opp-microvolt-vf0000 = <0>;
  1185. + opp-microvolt-vf0100 = <0>;
  1186. + opp-microvolt-vf0200 = <0>;
  1187. + opp-microvolt-vf0300 = <0>;
  1188. + opp-microvolt-vf0400 = <0>;
  1189. + opp-microvolt-vf0500 = <0>;
  1190. + opp-microvolt-vf0600 = <0>;
  1191. + opp-microvolt-vf0401 = <0>;
  1192. + opp-microvolt-vf0501 = <0>;
  1193. + opp-microvolt-26m-vf0000 = <800000>;
  1194. + opp-microvolt-26m-vf0100 = <0>;
  1195. + opp-microvolt-26m-vf0200 = <0>;
  1196. + opp-microvolt-26m-vf0300 = <0>;
  1197. + opp-microvolt-26m-vf0400 = <0>;
  1198. + opp-microvolt-26m-vf0500 = <0>;
  1199. + opp-microvolt-26m-vf0600 = <0>;
  1200. + opp-microvolt-26m-vf0401 = <0>;
  1201. + opp-microvolt-26m-vf0501 = <0>;
  1202. + };
  1203. +
  1204. + opp@780000000 {
  1205. + opp-hz = /bits/ 64 <780000000>;
  1206. + clock-latency-ns = <244144>;
  1207. + opp-microvolt-vf0000 = <0>;
  1208. + opp-microvolt-vf0100 = <0>;
  1209. + opp-microvolt-vf0200 = <0>;
  1210. + opp-microvolt-vf0300 = <0>;
  1211. + opp-microvolt-vf0400 = <0>;
  1212. + opp-microvolt-vf0500 = <0>;
  1213. + opp-microvolt-vf0600 = <0>;
  1214. + opp-microvolt-vf0401 = <0>;
  1215. + opp-microvolt-vf0501 = <0>;
  1216. + opp-microvolt-26m-vf0000 = <0>;
  1217. + opp-microvolt-26m-vf0100 = <800000>;
  1218. + opp-microvolt-26m-vf0200 = <800000>;
  1219. + opp-microvolt-26m-vf0300 = <800000>;
  1220. + opp-microvolt-26m-vf0400 = <800000>;
  1221. + opp-microvolt-26m-vf0500 = <800000>;
  1222. + opp-microvolt-26m-vf0600 = <800000>;
  1223. + opp-microvolt-26m-vf0401 = <800000>;
  1224. + opp-microvolt-26m-vf0501 = <800000>;
  1225. + };
  1226. +
  1227. + opp@1014000000 {
  1228. + opp-hz = /bits/ 64 <1014000000>;
  1229. + clock-latency-ns = <244144>;
  1230. + opp-microvolt-vf0000 = <0>;
  1231. + opp-microvolt-vf0100 = <0>;
  1232. + opp-microvolt-vf0200 = <0>;
  1233. + opp-microvolt-vf0300 = <0>;
  1234. + opp-microvolt-vf0400 = <0>;
  1235. + opp-microvolt-vf0500 = <0>;
  1236. + opp-microvolt-vf0600 = <0>;
  1237. + opp-microvolt-vf0401 = <0>;
  1238. + opp-microvolt-vf0501 = <0>;
  1239. + opp-microvolt-26m-vf0000 = <800000>;
  1240. + opp-microvolt-26m-vf0100 = <800000>;
  1241. + opp-microvolt-26m-vf0200 = <800000>;
  1242. + opp-microvolt-26m-vf0300 = <800000>;
  1243. + opp-microvolt-26m-vf0400 = <800000>;
  1244. + opp-microvolt-26m-vf0500 = <800000>;
  1245. + opp-microvolt-26m-vf0600 = <800000>;
  1246. + opp-microvolt-26m-vf0401 = <800000>;
  1247. + opp-microvolt-26m-vf0501 = <800000>;
  1248. + };
  1249. +
  1250. + opp@1196000000 {
  1251. + opp-hz = /bits/ 64 <1196000000>;
  1252. + clock-latency-ns = <244144>;
  1253. + opp-microvolt-vf0000 = <0>;
  1254. + opp-microvolt-vf0100 = <0>;
  1255. + opp-microvolt-vf0200 = <0>;
  1256. + opp-microvolt-vf0300 = <0>;
  1257. + opp-microvolt-vf0400 = <0>;
  1258. + opp-microvolt-vf0500 = <0>;
  1259. + opp-microvolt-vf0600 = <0>;
  1260. + opp-microvolt-vf0401 = <0>;
  1261. + opp-microvolt-vf0501 = <0>;
  1262. + opp-microvolt-26m-vf0000 = <800000>;
  1263. + opp-microvolt-26m-vf0100 = <800000>;
  1264. + opp-microvolt-26m-vf0200 = <800000>;
  1265. + opp-microvolt-26m-vf0300 = <800000>;
  1266. + opp-microvolt-26m-vf0400 = <800000>;
  1267. + opp-microvolt-26m-vf0500 = <800000>;
  1268. + opp-microvolt-26m-vf0600 = <800000>;
  1269. + opp-microvolt-26m-vf0401 = <800000>;
  1270. + opp-microvolt-26m-vf0501 = <800000>;
  1271. + };
  1272. +
  1273. + opp@1300000000 {
  1274. + opp-hz = /bits/ 64 <1300000000>;
  1275. + clock-latency-ns = <244144>;
  1276. + opp-microvolt-vf0000 = <0>;
  1277. + opp-microvolt-vf0100 = <0>;
  1278. + opp-microvolt-vf0200 = <0>;
  1279. + opp-microvolt-vf0300 = <0>;
  1280. + opp-microvolt-vf0400 = <0>;
  1281. + opp-microvolt-vf0500 = <0>;
  1282. + opp-microvolt-vf0600 = <0>;
  1283. + opp-microvolt-vf0401 = <0>;
  1284. + opp-microvolt-vf0501 = <0>;
  1285. + opp-microvolt-26m-vf0000 = <0>;
  1286. + opp-microvolt-26m-vf0100 = <800000>;
  1287. + opp-microvolt-26m-vf0200 = <0>;
  1288. + opp-microvolt-26m-vf0300 = <0>;
  1289. + opp-microvolt-26m-vf0400 = <0>;
  1290. + opp-microvolt-26m-vf0500 = <0>;
  1291. + opp-microvolt-26m-vf0600 = <0>;
  1292. + opp-microvolt-26m-vf0401 = <0>;
  1293. + opp-microvolt-26m-vf0501 = <0>;
  1294. + };
  1295. +
  1296. + opp@1404000000 {
  1297. + opp-hz = /bits/ 64 <1404000000>;
  1298. + clock-latency-ns = <244144>;
  1299. + opp-microvolt-vf0000 = <0>;
  1300. + opp-microvolt-vf0100 = <0>;
  1301. + opp-microvolt-vf0200 = <0>;
  1302. + opp-microvolt-vf0300 = <0>;
  1303. + opp-microvolt-vf0400 = <0>;
  1304. + opp-microvolt-vf0500 = <0>;
  1305. + opp-microvolt-vf0600 = <0>;
  1306. + opp-microvolt-vf0401 = <0>;
  1307. + opp-microvolt-vf0501 = <0>;
  1308. + opp-microvolt-26m-vf0000 = <800000>;
  1309. + opp-microvolt-26m-vf0100 = <850000>;
  1310. + opp-microvolt-26m-vf0200 = <800000>;
  1311. + opp-microvolt-26m-vf0300 = <820000>;
  1312. + opp-microvolt-26m-vf0400 = <800000>;
  1313. + opp-microvolt-26m-vf0500 = <800000>;
  1314. + opp-microvolt-26m-vf0600 = <800000>;
  1315. + opp-microvolt-26m-vf0401 = <800000>;
  1316. + opp-microvolt-26m-vf0501 = <800000>;
  1317. + };
  1318. +
  1319. + opp@1508000000 {
  1320. + opp-hz = /bits/ 64 <1508000000>;
  1321. + clock-latency-ns = <244144>;
  1322. + opp-microvolt-vf0000 = <0>;
  1323. + opp-microvolt-vf0100 = <0>;
  1324. + opp-microvolt-vf0200 = <0>;
  1325. + opp-microvolt-vf0300 = <0>;
  1326. + opp-microvolt-vf0400 = <0>;
  1327. + opp-microvolt-vf0500 = <0>;
  1328. + opp-microvolt-vf0600 = <0>;
  1329. + opp-microvolt-vf0401 = <0>;
  1330. + opp-microvolt-vf0501 = <0>;
  1331. + opp-microvolt-26m-vf0000 = <800000>;
  1332. + opp-microvolt-26m-vf0100 = <900000>;
  1333. + opp-microvolt-26m-vf0200 = <800000>;
  1334. + opp-microvolt-26m-vf0300 = <860000>;
  1335. + opp-microvolt-26m-vf0400 = <820000>;
  1336. + opp-microvolt-26m-vf0500 = <800000>;
  1337. + opp-microvolt-26m-vf0600 = <800000>;
  1338. + opp-microvolt-26m-vf0401 = <800000>;
  1339. + opp-microvolt-26m-vf0501 = <800000>;
  1340. + };
  1341. +
  1342. + opp@1586000000 {
  1343. + opp-hz = /bits/ 64 <1586000000>;
  1344. + clock-latency-ns = <244144>;
  1345. + opp-microvolt-vf0000 = <0>;
  1346. + opp-microvolt-vf0100 = <0>;
  1347. + opp-microvolt-vf0200 = <0>;
  1348. + opp-microvolt-vf0300 = <0>;
  1349. + opp-microvolt-vf0400 = <0>;
  1350. + opp-microvolt-vf0500 = <0>;
  1351. + opp-microvolt-vf0600 = <0>;
  1352. + opp-microvolt-vf0401 = <0>;
  1353. + opp-microvolt-vf0501 = <0>;
  1354. + opp-microvolt-26m-vf0000 = <850000>;
  1355. + opp-microvolt-26m-vf0100 = <0>;
  1356. + opp-microvolt-26m-vf0200 = <0>;
  1357. + opp-microvolt-26m-vf0300 = <0>;
  1358. + opp-microvolt-26m-vf0400 = <0>;
  1359. + opp-microvolt-26m-vf0500 = <0>;
  1360. + opp-microvolt-26m-vf0600 = <0>;
  1361. + opp-microvolt-26m-vf0401 = <0>;
  1362. + opp-microvolt-26m-vf0501 = <0>;
  1363. + };
  1364. +
  1365. + opp@1612000000 {
  1366. + opp-hz = /bits/ 64 <1612000000>;
  1367. + clock-latency-ns = <244144>;
  1368. + opp-microvolt-vf0000 = <0>;
  1369. + opp-microvolt-vf0100 = <0>;
  1370. + opp-microvolt-vf0200 = <0>;
  1371. + opp-microvolt-vf0300 = <0>;
  1372. + opp-microvolt-vf0400 = <0>;
  1373. + opp-microvolt-vf0500 = <0>;
  1374. + opp-microvolt-vf0600 = <0>;
  1375. + opp-microvolt-vf0401 = <0>;
  1376. + opp-microvolt-vf0501 = <0>;
  1377. + opp-microvolt-26m-vf0000 = <0>;
  1378. + opp-microvolt-26m-vf0100 = <950000>;
  1379. + opp-microvolt-26m-vf0200 = <850000>;
  1380. + opp-microvolt-26m-vf0300 = <900000>;
  1381. + opp-microvolt-26m-vf0400 = <840000>;
  1382. + opp-microvolt-26m-vf0500 = <820000>;
  1383. + opp-microvolt-26m-vf0600 = <850000>;
  1384. + opp-microvolt-26m-vf0401 = <820000>;
  1385. + opp-microvolt-26m-vf0501 = <820000>;
  1386. + };
  1387. +
  1388. + opp@1690000000 {
  1389. + opp-hz = /bits/ 64 <1690000000>;
  1390. + clock-latency-ns = <244144>;
  1391. + opp-microvolt-vf0000 = <0>;
  1392. + opp-microvolt-vf0100 = <0>;
  1393. + opp-microvolt-vf0200 = <0>;
  1394. + opp-microvolt-vf0300 = <0>;
  1395. + opp-microvolt-vf0400 = <0>;
  1396. + opp-microvolt-vf0500 = <0>;
  1397. + opp-microvolt-vf0600 = <0>;
  1398. + opp-microvolt-vf0401 = <0>;
  1399. + opp-microvolt-vf0501 = <0>;
  1400. + opp-microvolt-26m-vf0000 = <900000>;
  1401. + opp-microvolt-26m-vf0100 = <0>;
  1402. + opp-microvolt-26m-vf0200 = <0>;
  1403. + opp-microvolt-26m-vf0300 = <0>;
  1404. + opp-microvolt-26m-vf0400 = <0>;
  1405. + opp-microvolt-26m-vf0500 = <0>;
  1406. + opp-microvolt-26m-vf0600 = <0>;
  1407. + opp-microvolt-26m-vf0401 = <0>;
  1408. + opp-microvolt-26m-vf0501 = <0>;
  1409. + };
  1410. +
  1411. + opp@1716000000 {
  1412. + opp-hz = /bits/ 64 <1716000000>;
  1413. + clock-latency-ns = <244144>;
  1414. + opp-microvolt-vf0000 = <0>;
  1415. + opp-microvolt-vf0100 = <0>;
  1416. + opp-microvolt-vf0200 = <0>;
  1417. + opp-microvolt-vf0300 = <0>;
  1418. + opp-microvolt-vf0400 = <0>;
  1419. + opp-microvolt-vf0500 = <0>;
  1420. + opp-microvolt-vf0600 = <0>;
  1421. + opp-microvolt-vf0401 = <0>;
  1422. + opp-microvolt-vf0501 = <0>;
  1423. + opp-microvolt-26m-vf0000 = <0>;
  1424. + opp-microvolt-26m-vf0100 = <1000000>;
  1425. + opp-microvolt-26m-vf0200 = <900000>;
  1426. + opp-microvolt-26m-vf0300 = <0>;
  1427. + opp-microvolt-26m-vf0400 = <870000>;
  1428. + opp-microvolt-26m-vf0500 = <850000>;
  1429. + opp-microvolt-26m-vf0600 = <0>;
  1430. + opp-microvolt-26m-vf0401 = <850000>;
  1431. + opp-microvolt-26m-vf0501 = <840000>;
  1432. + };
  1433. +
  1434. + opp@1794000000 {
  1435. + opp-hz = /bits/ 64 <1794000000>;
  1436. + clock-latency-ns = <244144>;
  1437. + opp-microvolt-vf0000 = <0>;
  1438. + opp-microvolt-vf0100 = <0>;
  1439. + opp-microvolt-vf0200 = <0>;
  1440. + opp-microvolt-vf0300 = <0>;
  1441. + opp-microvolt-vf0400 = <0>;
  1442. + opp-microvolt-vf0500 = <0>;
  1443. + opp-microvolt-vf0600 = <0>;
  1444. + opp-microvolt-vf0401 = <0>;
  1445. + opp-microvolt-vf0501 = <0>;
  1446. + opp-microvolt-26m-vf0000 = <950000>;
  1447. + opp-microvolt-26m-vf0100 = <1050000>;
  1448. + opp-microvolt-26m-vf0200 = <950000>;
  1449. + opp-microvolt-26m-vf0300 = <0>;
  1450. + opp-microvolt-26m-vf0400 = <920000>;
  1451. + opp-microvolt-26m-vf0500 = <900000>;
  1452. + opp-microvolt-26m-vf0600 = <0>;
  1453. + opp-microvolt-26m-vf0401 = <900000>;
  1454. + opp-microvolt-26m-vf0501 = <870000>;
  1455. + };
  1456. +
  1457. + opp@1898000000 {
  1458. + opp-hz = /bits/ 64 <1898000000>;
  1459. + clock-latency-ns = <244144>;
  1460. + opp-microvolt-vf0000 = <0>;
  1461. + opp-microvolt-vf0100 = <0>;
  1462. + opp-microvolt-vf0200 = <0>;
  1463. + opp-microvolt-vf0300 = <0>;
  1464. + opp-microvolt-vf0400 = <0>;
  1465. + opp-microvolt-vf0500 = <0>;
  1466. + opp-microvolt-vf0600 = <0>;
  1467. + opp-microvolt-vf0401 = <0>;
  1468. + opp-microvolt-vf0501 = <0>;
  1469. + opp-microvolt-26m-vf0000 = <1000000>;
  1470. + opp-microvolt-26m-vf0100 = <0>;
  1471. + opp-microvolt-26m-vf0200 = <1000000>;
  1472. + opp-microvolt-26m-vf0300 = <0>;
  1473. + opp-microvolt-26m-vf0400 = <970000>;
  1474. + opp-microvolt-26m-vf0500 = <940000>;
  1475. + opp-microvolt-26m-vf0600 = <0>;
  1476. + opp-microvolt-26m-vf0401 = <940000>;
  1477. + opp-microvolt-26m-vf0501 = <900000>;
  1478. + };
  1479. +
  1480. + opp@1950000000 {
  1481. + opp-hz = /bits/ 64 <1950000000>;
  1482. + clock-latency-ns = <244144>;
  1483. + opp-microvolt-vf0000 = <0>;
  1484. + opp-microvolt-vf0100 = <0>;
  1485. + opp-microvolt-vf0200 = <0>;
  1486. + opp-microvolt-vf0300 = <0>;
  1487. + opp-microvolt-vf0400 = <0>;
  1488. + opp-microvolt-vf0500 = <0>;
  1489. + opp-microvolt-vf0600 = <0>;
  1490. + opp-microvolt-vf0401 = <0>;
  1491. + opp-microvolt-vf0501 = <0>;
  1492. + opp-microvolt-26m-vf0000 = <0>;
  1493. + opp-microvolt-26m-vf0100 = <0>;
  1494. + opp-microvolt-26m-vf0200 = <0>;
  1495. + opp-microvolt-26m-vf0300 = <0>;
  1496. + opp-microvolt-26m-vf0400 = <1000000>;
  1497. + opp-microvolt-26m-vf0500 = <970000>;
  1498. + opp-microvolt-26m-vf0600 = <0>;
  1499. + opp-microvolt-26m-vf0401 = <970000>;
  1500. + opp-microvolt-26m-vf0501 = <930000>;
  1501. + };
  1502. +
  1503. + opp@1976000000 {
  1504. + opp-hz = /bits/ 64 <1976000000>;
  1505. + clock-latency-ns = <244144>;
  1506. + opp-microvolt-vf0000 = <0>;
  1507. + opp-microvolt-vf0100 = <0>;
  1508. + opp-microvolt-vf0200 = <0>;
  1509. + opp-microvolt-vf0300 = <0>;
  1510. + opp-microvolt-vf0400 = <0>;
  1511. + opp-microvolt-vf0500 = <0>;
  1512. + opp-microvolt-vf0600 = <0>;
  1513. + opp-microvolt-vf0401 = <0>;
  1514. + opp-microvolt-vf0501 = <0>;
  1515. + opp-microvolt-26m-vf0000 = <1050000>;
  1516. + opp-microvolt-26m-vf0100 = <0>;
  1517. + opp-microvolt-26m-vf0200 = <0>;
  1518. + opp-microvolt-26m-vf0300 = <0>;
  1519. + opp-microvolt-26m-vf0400 = <0>;
  1520. + opp-microvolt-26m-vf0500 = <0>;
  1521. + opp-microvolt-26m-vf0600 = <0>;
  1522. + opp-microvolt-26m-vf0401 = <0>;
  1523. + opp-microvolt-26m-vf0501 = <0>;
  1524. + };
  1525. +
  1526. + opp@2002000000 {
  1527. + opp-hz = /bits/ 64 <2002000000>;
  1528. + clock-latency-ns = <244144>;
  1529. + opp-microvolt-vf0000 = <0>;
  1530. + opp-microvolt-vf0100 = <0>;
  1531. + opp-microvolt-vf0200 = <0>;
  1532. + opp-microvolt-vf0300 = <0>;
  1533. + opp-microvolt-vf0400 = <0>;
  1534. + opp-microvolt-vf0500 = <0>;
  1535. + opp-microvolt-vf0600 = <0>;
  1536. + opp-microvolt-vf0401 = <0>;
  1537. + opp-microvolt-vf0501 = <0>;
  1538. + opp-microvolt-26m-vf0000 = <0>;
  1539. + opp-microvolt-26m-vf0100 = <0>;
  1540. + opp-microvolt-26m-vf0200 = <1050000>;
  1541. + opp-microvolt-26m-vf0300 = <0>;
  1542. + opp-microvolt-26m-vf0400 = <1050000>;
  1543. + opp-microvolt-26m-vf0500 = <1000000>;
  1544. + opp-microvolt-26m-vf0600 = <0>;
  1545. + opp-microvolt-26m-vf0401 = <1000000>;
  1546. + opp-microvolt-26m-vf0501 = <960000>;
  1547. + };
  1548. +
  1549. + };
  1550. +
  1551. + dsu_opp_table: dsu-opp-table {
  1552. + compatible = "allwinner,dsu-operating-points";
  1553. +
  1554. + opp@288000000 {
  1555. + opp-hz = /bits/ 64 <288000000>;
  1556. + clock-latency-ns = <244144>;
  1557. + opp-microvolt-vf0000 = <800000>;
  1558. + opp-microvolt-vf0100 = <0>;
  1559. + opp-microvolt-vf0200 = <0>;
  1560. + opp-microvolt-vf0300 = <0>;
  1561. + opp-microvolt-vf0400 = <0>;
  1562. + opp-microvolt-vf0500 = <0>;
  1563. + opp-microvolt-vf0600 = <0>;
  1564. + opp-microvolt-vf0401 = <0>;
  1565. + opp-microvolt-vf0501 = <0>;
  1566. + opp-microvolt-26m-vf0000 = <0>;
  1567. + opp-microvolt-26m-vf0100 = <0>;
  1568. + opp-microvolt-26m-vf0200 = <0>;
  1569. + opp-microvolt-26m-vf0300 = <0>;
  1570. + opp-microvolt-26m-vf0400 = <0>;
  1571. + opp-microvolt-26m-vf0500 = <0>;
  1572. + opp-microvolt-26m-vf0600 = <0>;
  1573. + opp-microvolt-26m-vf0401 = <0>;
  1574. + opp-microvolt-26m-vf0501 = <0>;
  1575. + };
  1576. +
  1577. + opp@312000000 {
  1578. + opp-hz = /bits/ 64 <312000000>;
  1579. + clock-latency-ns = <244144>;
  1580. + opp-microvolt-vf0000 = <0>;
  1581. + opp-microvolt-vf0100 = <800000>;
  1582. + opp-microvolt-vf0200 = <800000>;
  1583. + opp-microvolt-vf0300 = <800000>;
  1584. + opp-microvolt-vf0400 = <800000>;
  1585. + opp-microvolt-vf0500 = <800000>;
  1586. + opp-microvolt-vf0600 = <800000>;
  1587. + opp-microvolt-vf0401 = <800000>;
  1588. + opp-microvolt-vf0501 = <800000>;
  1589. + opp-microvolt-26m-vf0000 = <800000>;
  1590. + opp-microvolt-26m-vf0100 = <800000>;
  1591. + opp-microvolt-26m-vf0200 = <800000>;
  1592. + opp-microvolt-26m-vf0300 = <800000>;
  1593. + opp-microvolt-26m-vf0400 = <800000>;
  1594. + opp-microvolt-26m-vf0500 = <800000>;
  1595. + opp-microvolt-26m-vf0600 = <800000>;
  1596. + opp-microvolt-26m-vf0401 = <800000>;
  1597. + opp-microvolt-26m-vf0501 = <800000>;
  1598. + };
  1599. +
  1600. + opp@528000000 {
  1601. + opp-hz = /bits/ 64 <528000000>;
  1602. + clock-latency-ns = <244144>;
  1603. + opp-microvolt-vf0000 = <800000>;
  1604. + opp-microvolt-vf0100 = <0>;
  1605. + opp-microvolt-vf0200 = <0>;
  1606. + opp-microvolt-vf0300 = <0>;
  1607. + opp-microvolt-vf0400 = <0>;
  1608. + opp-microvolt-vf0500 = <0>;
  1609. + opp-microvolt-vf0600 = <0>;
  1610. + opp-microvolt-vf0401 = <0>;
  1611. + opp-microvolt-vf0501 = <0>;
  1612. + opp-microvolt-26m-vf0000 = <0>;
  1613. + opp-microvolt-26m-vf0100 = <0>;
  1614. + opp-microvolt-26m-vf0200 = <0>;
  1615. + opp-microvolt-26m-vf0300 = <0>;
  1616. + opp-microvolt-26m-vf0400 = <0>;
  1617. + opp-microvolt-26m-vf0500 = <0>;
  1618. + opp-microvolt-26m-vf0600 = <0>;
  1619. + opp-microvolt-26m-vf0401 = <0>;
  1620. + opp-microvolt-26m-vf0501 = <0>;
  1621. + };
  1622. +
  1623. + opp@600000000 {
  1624. + opp-hz = /bits/ 64 <600000000>;
  1625. + clock-latency-ns = <244144>;
  1626. + opp-microvolt-vf0000 = <0>;
  1627. + opp-microvolt-vf0100 = <800000>;
  1628. + opp-microvolt-vf0200 = <800000>;
  1629. + opp-microvolt-vf0300 = <800000>;
  1630. + opp-microvolt-vf0400 = <800000>;
  1631. + opp-microvolt-vf0500 = <800000>;
  1632. + opp-microvolt-vf0600 = <800000>;
  1633. + opp-microvolt-vf0401 = <800000>;
  1634. + opp-microvolt-vf0501 = <800000>;
  1635. + opp-microvolt-26m-vf0000 = <0>;
  1636. + opp-microvolt-26m-vf0100 = <0>;
  1637. + opp-microvolt-26m-vf0200 = <0>;
  1638. + opp-microvolt-26m-vf0300 = <0>;
  1639. + opp-microvolt-26m-vf0400 = <0>;
  1640. + opp-microvolt-26m-vf0500 = <0>;
  1641. + opp-microvolt-26m-vf0600 = <0>;
  1642. + opp-microvolt-26m-vf0401 = <0>;
  1643. + opp-microvolt-26m-vf0501 = <0>;
  1644. + };
  1645. +
  1646. + opp@744000000 {
  1647. + opp-hz = /bits/ 64 <744000000>;
  1648. + clock-latency-ns = <244144>;
  1649. + opp-microvolt-vf0000 = <800000>;
  1650. + opp-microvolt-vf0100 = <0>;
  1651. + opp-microvolt-vf0200 = <0>;
  1652. + opp-microvolt-vf0300 = <0>;
  1653. + opp-microvolt-vf0400 = <0>;
  1654. + opp-microvolt-vf0500 = <0>;
  1655. + opp-microvolt-vf0600 = <0>;
  1656. + opp-microvolt-vf0401 = <0>;
  1657. + opp-microvolt-vf0501 = <0>;
  1658. + opp-microvolt-26m-vf0000 = <0>;
  1659. + opp-microvolt-26m-vf0100 = <0>;
  1660. + opp-microvolt-26m-vf0200 = <0>;
  1661. + opp-microvolt-26m-vf0300 = <0>;
  1662. + opp-microvolt-26m-vf0400 = <0>;
  1663. + opp-microvolt-26m-vf0500 = <0>;
  1664. + opp-microvolt-26m-vf0600 = <0>;
  1665. + opp-microvolt-26m-vf0401 = <0>;
  1666. + opp-microvolt-26m-vf0501 = <0>;
  1667. + };
  1668. +
  1669. + opp@792000000 {
  1670. + opp-hz = /bits/ 64 <792000000>;
  1671. + clock-latency-ns = <244144>;
  1672. + opp-microvolt-vf0000 = <0>;
  1673. + opp-microvolt-vf0100 = <800000>;
  1674. + opp-microvolt-vf0200 = <800000>;
  1675. + opp-microvolt-vf0300 = <800000>;
  1676. + opp-microvolt-vf0400 = <800000>;
  1677. + opp-microvolt-vf0500 = <800000>;
  1678. + opp-microvolt-vf0600 = <800000>;
  1679. + opp-microvolt-vf0401 = <800000>;
  1680. + opp-microvolt-vf0501 = <800000>;
  1681. + opp-microvolt-26m-vf0000 = <0>;
  1682. + opp-microvolt-26m-vf0100 = <0>;
  1683. + opp-microvolt-26m-vf0200 = <0>;
  1684. + opp-microvolt-26m-vf0300 = <0>;
  1685. + opp-microvolt-26m-vf0400 = <0>;
  1686. + opp-microvolt-26m-vf0500 = <0>;
  1687. + opp-microvolt-26m-vf0600 = <0>;
  1688. + opp-microvolt-26m-vf0401 = <0>;
  1689. + opp-microvolt-26m-vf0501 = <0>;
  1690. + };
  1691. +
  1692. + opp@840000000 {
  1693. + opp-hz = /bits/ 64 <840000000>;
  1694. + clock-latency-ns = <244144>;
  1695. + opp-microvolt-vf0000 = <0>;
  1696. + opp-microvolt-vf0100 = <800000>;
  1697. + opp-microvolt-vf0200 = <0>;
  1698. + opp-microvolt-vf0300 = <0>;
  1699. + opp-microvolt-vf0400 = <0>;
  1700. + opp-microvolt-vf0500 = <0>;
  1701. + opp-microvolt-vf0600 = <0>;
  1702. + opp-microvolt-vf0401 = <0>;
  1703. + opp-microvolt-vf0501 = <0>;
  1704. + opp-microvolt-26m-vf0000 = <0>;
  1705. + opp-microvolt-26m-vf0100 = <0>;
  1706. + opp-microvolt-26m-vf0200 = <0>;
  1707. + opp-microvolt-26m-vf0300 = <0>;
  1708. + opp-microvolt-26m-vf0400 = <0>;
  1709. + opp-microvolt-26m-vf0500 = <0>;
  1710. + opp-microvolt-26m-vf0600 = <0>;
  1711. + opp-microvolt-26m-vf0401 = <0>;
  1712. + opp-microvolt-26m-vf0501 = <0>;
  1713. + };
  1714. +
  1715. + opp@888000000 {
  1716. + opp-hz = /bits/ 64 <888000000>;
  1717. + clock-latency-ns = <244144>;
  1718. + opp-microvolt-vf0000 = <800000>;
  1719. + opp-microvolt-vf0100 = <0>;
  1720. + opp-microvolt-vf0200 = <0>;
  1721. + opp-microvolt-vf0300 = <0>;
  1722. + opp-microvolt-vf0400 = <0>;
  1723. + opp-microvolt-vf0500 = <0>;
  1724. + opp-microvolt-vf0600 = <0>;
  1725. + opp-microvolt-vf0401 = <0>;
  1726. + opp-microvolt-vf0501 = <0>;
  1727. + opp-microvolt-26m-vf0000 = <0>;
  1728. + opp-microvolt-26m-vf0100 = <0>;
  1729. + opp-microvolt-26m-vf0200 = <0>;
  1730. + opp-microvolt-26m-vf0300 = <0>;
  1731. + opp-microvolt-26m-vf0400 = <0>;
  1732. + opp-microvolt-26m-vf0500 = <0>;
  1733. + opp-microvolt-26m-vf0600 = <0>;
  1734. + opp-microvolt-26m-vf0401 = <0>;
  1735. + opp-microvolt-26m-vf0501 = <0>;
  1736. + };
  1737. +
  1738. + opp@912000000 {
  1739. + opp-hz = /bits/ 64 <912000000>;
  1740. + clock-latency-ns = <244144>;
  1741. + opp-microvolt-vf0000 = <0>;
  1742. + opp-microvolt-vf0100 = <850000>;
  1743. + opp-microvolt-vf0200 = <800000>;
  1744. + opp-microvolt-vf0300 = <800000>;
  1745. + opp-microvolt-vf0400 = <800000>;
  1746. + opp-microvolt-vf0500 = <800000>;
  1747. + opp-microvolt-vf0600 = <800000>;
  1748. + opp-microvolt-vf0401 = <800000>;
  1749. + opp-microvolt-vf0501 = <800000>;
  1750. + opp-microvolt-26m-vf0000 = <0>;
  1751. + opp-microvolt-26m-vf0100 = <0>;
  1752. + opp-microvolt-26m-vf0200 = <0>;
  1753. + opp-microvolt-26m-vf0300 = <0>;
  1754. + opp-microvolt-26m-vf0400 = <0>;
  1755. + opp-microvolt-26m-vf0500 = <0>;
  1756. + opp-microvolt-26m-vf0600 = <0>;
  1757. + opp-microvolt-26m-vf0401 = <0>;
  1758. + opp-microvolt-26m-vf0501 = <0>;
  1759. + };
  1760. +
  1761. + opp@984000000 {
  1762. + opp-hz = /bits/ 64 <984000000>;
  1763. + clock-latency-ns = <244144>;
  1764. + opp-microvolt-vf0000 = <0>;
  1765. + opp-microvolt-vf0100 = <900000>;
  1766. + opp-microvolt-vf0200 = <800000>;
  1767. + opp-microvolt-vf0300 = <0>;
  1768. + opp-microvolt-vf0400 = <0>;
  1769. + opp-microvolt-vf0500 = <0>;
  1770. + opp-microvolt-vf0600 = <0>;
  1771. + opp-microvolt-vf0401 = <0>;
  1772. + opp-microvolt-vf0501 = <0>;
  1773. + opp-microvolt-26m-vf0000 = <0>;
  1774. + opp-microvolt-26m-vf0100 = <0>;
  1775. + opp-microvolt-26m-vf0200 = <0>;
  1776. + opp-microvolt-26m-vf0300 = <0>;
  1777. + opp-microvolt-26m-vf0400 = <0>;
  1778. + opp-microvolt-26m-vf0500 = <0>;
  1779. + opp-microvolt-26m-vf0600 = <0>;
  1780. + opp-microvolt-26m-vf0401 = <0>;
  1781. + opp-microvolt-26m-vf0501 = <0>;
  1782. + };
  1783. +
  1784. + opp@1032000000 {
  1785. + opp-hz = /bits/ 64 <1032000000>;
  1786. + clock-latency-ns = <244144>;
  1787. + opp-microvolt-vf0000 = <800000>;
  1788. + opp-microvolt-vf0100 = <0>;
  1789. + opp-microvolt-vf0200 = <0>;
  1790. + opp-microvolt-vf0300 = <0>;
  1791. + opp-microvolt-vf0400 = <0>;
  1792. + opp-microvolt-vf0500 = <0>;
  1793. + opp-microvolt-vf0600 = <0>;
  1794. + opp-microvolt-vf0401 = <0>;
  1795. + opp-microvolt-vf0501 = <0>;
  1796. + opp-microvolt-26m-vf0000 = <0>;
  1797. + opp-microvolt-26m-vf0100 = <0>;
  1798. + opp-microvolt-26m-vf0200 = <0>;
  1799. + opp-microvolt-26m-vf0300 = <0>;
  1800. + opp-microvolt-26m-vf0400 = <0>;
  1801. + opp-microvolt-26m-vf0500 = <0>;
  1802. + opp-microvolt-26m-vf0600 = <0>;
  1803. + opp-microvolt-26m-vf0401 = <0>;
  1804. + opp-microvolt-26m-vf0501 = <0>;
  1805. + };
  1806. +
  1807. + opp@1056000000 {
  1808. + opp-hz = /bits/ 64 <1056000000>;
  1809. + clock-latency-ns = <244144>;
  1810. + opp-microvolt-vf0000 = <0>;
  1811. + opp-microvolt-vf0100 = <950000>;
  1812. + opp-microvolt-vf0200 = <850000>;
  1813. + opp-microvolt-vf0300 = <860000>;
  1814. + opp-microvolt-vf0400 = <840000>;
  1815. + opp-microvolt-vf0500 = <800000>;
  1816. + opp-microvolt-vf0600 = <840000>;
  1817. + opp-microvolt-vf0401 = <800000>;
  1818. + opp-microvolt-vf0501 = <800000>;
  1819. + opp-microvolt-26m-vf0000 = <0>;
  1820. + opp-microvolt-26m-vf0100 = <0>;
  1821. + opp-microvolt-26m-vf0200 = <0>;
  1822. + opp-microvolt-26m-vf0300 = <0>;
  1823. + opp-microvolt-26m-vf0400 = <0>;
  1824. + opp-microvolt-26m-vf0500 = <0>;
  1825. + opp-microvolt-26m-vf0600 = <0>;
  1826. + opp-microvolt-26m-vf0401 = <0>;
  1827. + opp-microvolt-26m-vf0501 = <0>;
  1828. + };
  1829. +
  1830. + opp@1152000000 {
  1831. + opp-hz = /bits/ 64 <1152000000>;
  1832. + clock-latency-ns = <244144>;
  1833. + opp-microvolt-vf0000 = <900000>;
  1834. + opp-microvolt-vf0100 = <1000000>;
  1835. + opp-microvolt-vf0200 = <900000>;
  1836. + opp-microvolt-vf0300 = <0>;
  1837. + opp-microvolt-vf0400 = <880000>;
  1838. + opp-microvolt-vf0500 = <820000>;
  1839. + opp-microvolt-vf0600 = <0>;
  1840. + opp-microvolt-vf0401 = <820000>;
  1841. + opp-microvolt-vf0501 = <820000>;
  1842. + opp-microvolt-26m-vf0000 = <0>;
  1843. + opp-microvolt-26m-vf0100 = <0>;
  1844. + opp-microvolt-26m-vf0200 = <0>;
  1845. + opp-microvolt-26m-vf0300 = <0>;
  1846. + opp-microvolt-26m-vf0400 = <0>;
  1847. + opp-microvolt-26m-vf0500 = <0>;
  1848. + opp-microvolt-26m-vf0600 = <0>;
  1849. + opp-microvolt-26m-vf0401 = <0>;
  1850. + opp-microvolt-26m-vf0501 = <0>;
  1851. + };
  1852. +
  1853. + opp@1200000000 {
  1854. + opp-hz = /bits/ 64 <1200000000>;
  1855. + clock-latency-ns = <244144>;
  1856. + opp-microvolt-vf0000 = <0>;
  1857. + opp-microvolt-vf0100 = <1050000>;
  1858. + opp-microvolt-vf0200 = <950000>;
  1859. + opp-microvolt-vf0300 = <0>;
  1860. + opp-microvolt-vf0400 = <920000>;
  1861. + opp-microvolt-vf0500 = <860000>;
  1862. + opp-microvolt-vf0600 = <0>;
  1863. + opp-microvolt-vf0401 = <860000>;
  1864. + opp-microvolt-vf0501 = <840000>;
  1865. + opp-microvolt-26m-vf0000 = <0>;
  1866. + opp-microvolt-26m-vf0100 = <0>;
  1867. + opp-microvolt-26m-vf0200 = <0>;
  1868. + opp-microvolt-26m-vf0300 = <0>;
  1869. + opp-microvolt-26m-vf0400 = <0>;
  1870. + opp-microvolt-26m-vf0500 = <0>;
  1871. + opp-microvolt-26m-vf0600 = <0>;
  1872. + opp-microvolt-26m-vf0401 = <0>;
  1873. + opp-microvolt-26m-vf0501 = <0>;
  1874. + };
  1875. +
  1876. + opp@1224000000 {
  1877. + opp-hz = /bits/ 64 <1224000000>;
  1878. + clock-latency-ns = <244144>;
  1879. + opp-microvolt-vf0000 = <0>;
  1880. + opp-microvolt-vf0100 = <0>;
  1881. + opp-microvolt-vf0200 = <1000000>;
  1882. + opp-microvolt-vf0300 = <0>;
  1883. + opp-microvolt-vf0400 = <960000>;
  1884. + opp-microvolt-vf0500 = <900000>;
  1885. + opp-microvolt-vf0600 = <0>;
  1886. + opp-microvolt-vf0401 = <900000>;
  1887. + opp-microvolt-vf0501 = <860000>;
  1888. + opp-microvolt-26m-vf0000 = <0>;
  1889. + opp-microvolt-26m-vf0100 = <0>;
  1890. + opp-microvolt-26m-vf0200 = <0>;
  1891. + opp-microvolt-26m-vf0300 = <0>;
  1892. + opp-microvolt-26m-vf0400 = <0>;
  1893. + opp-microvolt-26m-vf0500 = <0>;
  1894. + opp-microvolt-26m-vf0600 = <0>;
  1895. + opp-microvolt-26m-vf0401 = <0>;
  1896. + opp-microvolt-26m-vf0501 = <0>;
  1897. + };
  1898. +
  1899. + opp@1248000000 {
  1900. + opp-hz = /bits/ 64 <1248000000>;
  1901. + clock-latency-ns = <244144>;
  1902. + opp-microvolt-vf0000 = <0>;
  1903. + opp-microvolt-vf0100 = <0>;
  1904. + opp-microvolt-vf0200 = <1050000>;
  1905. + opp-microvolt-vf0300 = <0>;
  1906. + opp-microvolt-vf0400 = <1000000>;
  1907. + opp-microvolt-vf0500 = <950000>;
  1908. + opp-microvolt-vf0600 = <0>;
  1909. + opp-microvolt-vf0401 = <950000>;
  1910. + opp-microvolt-vf0501 = <900000>;
  1911. + opp-microvolt-26m-vf0000 = <0>;
  1912. + opp-microvolt-26m-vf0100 = <0>;
  1913. + opp-microvolt-26m-vf0200 = <1000000>;
  1914. + opp-microvolt-26m-vf0300 = <0>;
  1915. + opp-microvolt-26m-vf0400 = <960000>;
  1916. + opp-microvolt-26m-vf0500 = <900000>;
  1917. + opp-microvolt-26m-vf0600 = <0>;
  1918. + opp-microvolt-26m-vf0401 = <900000>;
  1919. + opp-microvolt-26m-vf0501 = <860000>;
  1920. + };
  1921. +
  1922. + opp@1296000000 {
  1923. + opp-hz = /bits/ 64 <1296000000>;
  1924. + clock-latency-ns = <244144>;
  1925. + opp-microvolt-vf0000 = <1000000>;
  1926. + opp-microvolt-vf0100 = <0>;
  1927. + opp-microvolt-vf0200 = <0>;
  1928. + opp-microvolt-vf0300 = <0>;
  1929. + opp-microvolt-vf0400 = <0>;
  1930. + opp-microvolt-vf0500 = <0>;
  1931. + opp-microvolt-vf0600 = <0>;
  1932. + opp-microvolt-vf0401 = <0>;
  1933. + opp-microvolt-vf0501 = <0>;
  1934. + opp-microvolt-26m-vf0000 = <0>;
  1935. + opp-microvolt-26m-vf0100 = <0>;
  1936. + opp-microvolt-26m-vf0200 = <0>;
  1937. + opp-microvolt-26m-vf0300 = <0>;
  1938. + opp-microvolt-26m-vf0400 = <0>;
  1939. + opp-microvolt-26m-vf0500 = <0>;
  1940. + opp-microvolt-26m-vf0600 = <0>;
  1941. + opp-microvolt-26m-vf0401 = <0>;
  1942. + opp-microvolt-26m-vf0501 = <0>;
  1943. + };
  1944. +
  1945. + opp@546000000 {
  1946. + opp-hz = /bits/ 64 <546000000>;
  1947. + clock-latency-ns = <244144>;
  1948. + opp-microvolt-vf0000 = <0>;
  1949. + opp-microvolt-vf0100 = <0>;
  1950. + opp-microvolt-vf0200 = <0>;
  1951. + opp-microvolt-vf0300 = <0>;
  1952. + opp-microvolt-vf0400 = <0>;
  1953. + opp-microvolt-vf0500 = <0>;
  1954. + opp-microvolt-vf0600 = <0>;
  1955. + opp-microvolt-vf0401 = <0>;
  1956. + opp-microvolt-vf0501 = <0>;
  1957. + opp-microvolt-26m-vf0000 = <800000>;
  1958. + opp-microvolt-26m-vf0100 = <0>;
  1959. + opp-microvolt-26m-vf0200 = <0>;
  1960. + opp-microvolt-26m-vf0300 = <0>;
  1961. + opp-microvolt-26m-vf0400 = <0>;
  1962. + opp-microvolt-26m-vf0500 = <0>;
  1963. + opp-microvolt-26m-vf0600 = <0>;
  1964. + opp-microvolt-26m-vf0401 = <0>;
  1965. + opp-microvolt-26m-vf0501 = <0>;
  1966. + };
  1967. +
  1968. + opp@598000000 {
  1969. + opp-hz = /bits/ 64 <598000000>;
  1970. + clock-latency-ns = <244144>;
  1971. + opp-microvolt-vf0000 = <0>;
  1972. + opp-microvolt-vf0100 = <0>;
  1973. + opp-microvolt-vf0200 = <0>;
  1974. + opp-microvolt-vf0300 = <0>;
  1975. + opp-microvolt-vf0400 = <0>;
  1976. + opp-microvolt-vf0500 = <0>;
  1977. + opp-microvolt-vf0600 = <0>;
  1978. + opp-microvolt-vf0401 = <0>;
  1979. + opp-microvolt-vf0501 = <0>;
  1980. + opp-microvolt-26m-vf0000 = <0>;
  1981. + opp-microvolt-26m-vf0100 = <800000>;
  1982. + opp-microvolt-26m-vf0200 = <800000>;
  1983. + opp-microvolt-26m-vf0300 = <800000>;
  1984. + opp-microvolt-26m-vf0400 = <800000>;
  1985. + opp-microvolt-26m-vf0500 = <800000>;
  1986. + opp-microvolt-26m-vf0600 = <800000>;
  1987. + opp-microvolt-26m-vf0401 = <800000>;
  1988. + opp-microvolt-26m-vf0501 = <800000>;
  1989. + };
  1990. +
  1991. + opp@780000000 {
  1992. + opp-hz = /bits/ 64 <780000000>;
  1993. + clock-latency-ns = <244144>;
  1994. + opp-microvolt-vf0000 = <0>;
  1995. + opp-microvolt-vf0100 = <0>;
  1996. + opp-microvolt-vf0200 = <0>;
  1997. + opp-microvolt-vf0300 = <0>;
  1998. + opp-microvolt-vf0400 = <0>;
  1999. + opp-microvolt-vf0500 = <0>;
  2000. + opp-microvolt-vf0600 = <0>;
  2001. + opp-microvolt-vf0401 = <0>;
  2002. + opp-microvolt-vf0501 = <0>;
  2003. + opp-microvolt-26m-vf0000 = <800000>;
  2004. + opp-microvolt-26m-vf0100 = <800000>;
  2005. + opp-microvolt-26m-vf0200 = <800000>;
  2006. + opp-microvolt-26m-vf0300 = <800000>;
  2007. + opp-microvolt-26m-vf0400 = <800000>;
  2008. + opp-microvolt-26m-vf0500 = <800000>;
  2009. + opp-microvolt-26m-vf0600 = <800000>;
  2010. + opp-microvolt-26m-vf0401 = <800000>;
  2011. + opp-microvolt-26m-vf0501 = <800000>;
  2012. + };
  2013. +
  2014. + opp@832000000 {
  2015. + opp-hz = /bits/ 64 <832000000>;
  2016. + clock-latency-ns = <244144>;
  2017. + opp-microvolt-vf0000 = <0>;
  2018. + opp-microvolt-vf0100 = <0>;
  2019. + opp-microvolt-vf0200 = <0>;
  2020. + opp-microvolt-vf0300 = <0>;
  2021. + opp-microvolt-vf0400 = <0>;
  2022. + opp-microvolt-vf0500 = <0>;
  2023. + opp-microvolt-vf0600 = <0>;
  2024. + opp-microvolt-vf0401 = <0>;
  2025. + opp-microvolt-vf0501 = <0>;
  2026. + opp-microvolt-26m-vf0000 = <0>;
  2027. + opp-microvolt-26m-vf0100 = <800000>;
  2028. + opp-microvolt-26m-vf0200 = <0>;
  2029. + opp-microvolt-26m-vf0300 = <0>;
  2030. + opp-microvolt-26m-vf0400 = <0>;
  2031. + opp-microvolt-26m-vf0500 = <0>;
  2032. + opp-microvolt-26m-vf0600 = <0>;
  2033. + opp-microvolt-26m-vf0401 = <0>;
  2034. + opp-microvolt-26m-vf0501 = <0>;
  2035. + };
  2036. +
  2037. + opp@910000000 {
  2038. + opp-hz = /bits/ 64 <910000000>;
  2039. + clock-latency-ns = <244144>;
  2040. + opp-microvolt-vf0000 = <0>;
  2041. + opp-microvolt-vf0100 = <0>;
  2042. + opp-microvolt-vf0200 = <0>;
  2043. + opp-microvolt-vf0300 = <0>;
  2044. + opp-microvolt-vf0400 = <0>;
  2045. + opp-microvolt-vf0500 = <0>;
  2046. + opp-microvolt-vf0600 = <0>;
  2047. + opp-microvolt-vf0401 = <0>;
  2048. + opp-microvolt-vf0501 = <0>;
  2049. + opp-microvolt-26m-vf0000 = <800000>;
  2050. + opp-microvolt-26m-vf0100 = <850000>;
  2051. + opp-microvolt-26m-vf0200 = <800000>;
  2052. + opp-microvolt-26m-vf0300 = <800000>;
  2053. + opp-microvolt-26m-vf0400 = <800000>;
  2054. + opp-microvolt-26m-vf0500 = <800000>;
  2055. + opp-microvolt-26m-vf0600 = <800000>;
  2056. + opp-microvolt-26m-vf0401 = <800000>;
  2057. + opp-microvolt-26m-vf0501 = <800000>;
  2058. + };
  2059. +
  2060. + opp@988000000 {
  2061. + opp-hz = /bits/ 64 <988000000>;
  2062. + clock-latency-ns = <244144>;
  2063. + opp-microvolt-vf0000 = <0>;
  2064. + opp-microvolt-vf0100 = <0>;
  2065. + opp-microvolt-vf0200 = <0>;
  2066. + opp-microvolt-vf0300 = <0>;
  2067. + opp-microvolt-vf0400 = <0>;
  2068. + opp-microvolt-vf0500 = <0>;
  2069. + opp-microvolt-vf0600 = <0>;
  2070. + opp-microvolt-vf0401 = <0>;
  2071. + opp-microvolt-vf0501 = <0>;
  2072. + opp-microvolt-26m-vf0000 = <0>;
  2073. + opp-microvolt-26m-vf0100 = <900000>;
  2074. + opp-microvolt-26m-vf0200 = <800000>;
  2075. + opp-microvolt-26m-vf0300 = <0>;
  2076. + opp-microvolt-26m-vf0400 = <0>;
  2077. + opp-microvolt-26m-vf0500 = <0>;
  2078. + opp-microvolt-26m-vf0600 = <0>;
  2079. + opp-microvolt-26m-vf0401 = <0>;
  2080. + opp-microvolt-26m-vf0501 = <0>;
  2081. + };
  2082. +
  2083. + opp@1066000000 {
  2084. + opp-hz = /bits/ 64 <1066000000>;
  2085. + clock-latency-ns = <244144>;
  2086. + opp-microvolt-vf0000 = <0>;
  2087. + opp-microvolt-vf0100 = <0>;
  2088. + opp-microvolt-vf0200 = <0>;
  2089. + opp-microvolt-vf0300 = <0>;
  2090. + opp-microvolt-vf0400 = <0>;
  2091. + opp-microvolt-vf0500 = <0>;
  2092. + opp-microvolt-vf0600 = <0>;
  2093. + opp-microvolt-vf0401 = <0>;
  2094. + opp-microvolt-vf0501 = <0>;
  2095. + opp-microvolt-26m-vf0000 = <800000>;
  2096. + opp-microvolt-26m-vf0100 = <950000>;
  2097. + opp-microvolt-26m-vf0200 = <850000>;
  2098. + opp-microvolt-26m-vf0300 = <860000>;
  2099. + opp-microvolt-26m-vf0400 = <840000>;
  2100. + opp-microvolt-26m-vf0500 = <800000>;
  2101. + opp-microvolt-26m-vf0600 = <840000>;
  2102. + opp-microvolt-26m-vf0401 = <800000>;
  2103. + opp-microvolt-26m-vf0501 = <800000>;
  2104. + };
  2105. +
  2106. + opp@1144000000 {
  2107. + opp-hz = /bits/ 64 <1144000000>;
  2108. + clock-latency-ns = <244144>;
  2109. + opp-microvolt-vf0000 = <0>;
  2110. + opp-microvolt-vf0100 = <0>;
  2111. + opp-microvolt-vf0200 = <0>;
  2112. + opp-microvolt-vf0300 = <0>;
  2113. + opp-microvolt-vf0400 = <0>;
  2114. + opp-microvolt-vf0500 = <0>;
  2115. + opp-microvolt-vf0600 = <0>;
  2116. + opp-microvolt-vf0401 = <0>;
  2117. + opp-microvolt-vf0501 = <0>;
  2118. + opp-microvolt-26m-vf0000 = <0>;
  2119. + opp-microvolt-26m-vf0100 = <1000000>;
  2120. + opp-microvolt-26m-vf0200 = <900000>;
  2121. + opp-microvolt-26m-vf0300 = <0>;
  2122. + opp-microvolt-26m-vf0400 = <880000>;
  2123. + opp-microvolt-26m-vf0500 = <820000>;
  2124. + opp-microvolt-26m-vf0600 = <0>;
  2125. + opp-microvolt-26m-vf0401 = <820000>;
  2126. + opp-microvolt-26m-vf0501 = <820000>;
  2127. + };
  2128. +
  2129. + opp@1196000000 {
  2130. + opp-hz = /bits/ 64 <1196000000>;
  2131. + clock-latency-ns = <244144>;
  2132. + opp-microvolt-vf0000 = <0>;
  2133. + opp-microvolt-vf0100 = <0>;
  2134. + opp-microvolt-vf0200 = <0>;
  2135. + opp-microvolt-vf0300 = <0>;
  2136. + opp-microvolt-vf0400 = <0>;
  2137. + opp-microvolt-vf0500 = <0>;
  2138. + opp-microvolt-vf0600 = <0>;
  2139. + opp-microvolt-vf0401 = <0>;
  2140. + opp-microvolt-vf0501 = <0>;
  2141. + opp-microvolt-26m-vf0000 = <900000>;
  2142. + opp-microvolt-26m-vf0100 = <0>;
  2143. + opp-microvolt-26m-vf0200 = <0>;
  2144. + opp-microvolt-26m-vf0300 = <0>;
  2145. + opp-microvolt-26m-vf0400 = <0>;
  2146. + opp-microvolt-26m-vf0500 = <0>;
  2147. + opp-microvolt-26m-vf0600 = <0>;
  2148. + opp-microvolt-26m-vf0401 = <0>;
  2149. + opp-microvolt-26m-vf0501 = <0>;
  2150. + };
  2151. +
  2152. + opp@1222000000 {
  2153. + opp-hz = /bits/ 64 <1222000000>;
  2154. + clock-latency-ns = <244144>;
  2155. + opp-microvolt-vf0000 = <0>;
  2156. + opp-microvolt-vf0100 = <0>;
  2157. + opp-microvolt-vf0200 = <0>;
  2158. + opp-microvolt-vf0300 = <0>;
  2159. + opp-microvolt-vf0400 = <0>;
  2160. + opp-microvolt-vf0500 = <0>;
  2161. + opp-microvolt-vf0600 = <0>;
  2162. + opp-microvolt-vf0401 = <0>;
  2163. + opp-microvolt-vf0501 = <0>;
  2164. + opp-microvolt-26m-vf0000 = <0>;
  2165. + opp-microvolt-26m-vf0100 = <1050000>;
  2166. + opp-microvolt-26m-vf0200 = <950000>;
  2167. + opp-microvolt-26m-vf0300 = <0>;
  2168. + opp-microvolt-26m-vf0400 = <920000>;
  2169. + opp-microvolt-26m-vf0500 = <860000>;
  2170. + opp-microvolt-26m-vf0600 = <0>;
  2171. + opp-microvolt-26m-vf0401 = <860000>;
  2172. + opp-microvolt-26m-vf0501 = <840000>;
  2173. + };
  2174. +
  2175. + opp@1274000000 {
  2176. + opp-hz = /bits/ 64 <1274000000>;
  2177. + clock-latency-ns = <244144>;
  2178. + opp-microvolt-vf0000 = <0>;
  2179. + opp-microvolt-vf0100 = <0>;
  2180. + opp-microvolt-vf0200 = <0>;
  2181. + opp-microvolt-vf0300 = <0>;
  2182. + opp-microvolt-vf0400 = <0>;
  2183. + opp-microvolt-vf0500 = <0>;
  2184. + opp-microvolt-vf0600 = <0>;
  2185. + opp-microvolt-vf0401 = <0>;
  2186. + opp-microvolt-vf0501 = <0>;
  2187. + opp-microvolt-26m-vf0000 = <0>;
  2188. + opp-microvolt-26m-vf0100 = <0>;
  2189. + opp-microvolt-26m-vf0200 = <1050000>;
  2190. + opp-microvolt-26m-vf0300 = <0>;
  2191. + opp-microvolt-26m-vf0400 = <1000000>;
  2192. + opp-microvolt-26m-vf0500 = <950000>;
  2193. + opp-microvolt-26m-vf0600 = <0>;
  2194. + opp-microvolt-26m-vf0401 = <950000>;
  2195. + opp-microvolt-26m-vf0501 = <900000>;
  2196. + };
  2197. +
  2198. + opp@1352000000 {
  2199. + opp-hz = /bits/ 64 <1352000000>;
  2200. + clock-latency-ns = <244144>;
  2201. + opp-microvolt-vf0000 = <0>;
  2202. + opp-microvolt-vf0100 = <0>;
  2203. + opp-microvolt-vf0200 = <0>;
  2204. + opp-microvolt-vf0300 = <0>;
  2205. + opp-microvolt-vf0400 = <0>;
  2206. + opp-microvolt-vf0500 = <0>;
  2207. + opp-microvolt-vf0600 = <0>;
  2208. + opp-microvolt-vf0401 = <0>;
  2209. + opp-microvolt-vf0501 = <0>;
  2210. + opp-microvolt-26m-vf0000 = <1000000>;
  2211. + opp-microvolt-26m-vf0100 = <0>;
  2212. + opp-microvolt-26m-vf0200 = <0>;
  2213. + opp-microvolt-26m-vf0300 = <0>;
  2214. + opp-microvolt-26m-vf0400 = <0>;
  2215. + opp-microvolt-26m-vf0500 = <0>;
  2216. + opp-microvolt-26m-vf0600 = <0>;
  2217. + opp-microvolt-26m-vf0401 = <0>;
  2218. + opp-microvolt-26m-vf0501 = <0>;
  2219. + };
  2220. + };
  2221. +
  2222. + npu_opp_table: npu-opp-table {
  2223. + compatible = "allwinner,npu-operating-points";
  2224. +
  2225. + npu_opp_table_492: opp-492 {
  2226. + opp-hz = /bits/ 64 <492000000>;
  2227. + opp-microvolt-vf0000 = <800000>;
  2228. + opp-microvolt-vf0200 = <800000>;
  2229. + opp-microvolt-vf0201 = <800000>;
  2230. + opp-microvolt-vf0202 = <800000>;
  2231. + opp-microvolt-vf0203 = <800000>;
  2232. + opp-microvolt-vf0204 = <800000>;
  2233. + opp-microvolt-vf0205 = <800000>;
  2234. + opp-microvolt-vf0206 = <800000>;
  2235. + opp-microvolt-vf0300 = <800000>;
  2236. + opp-microvolt-vf0400 = <800000>;
  2237. + opp-microvolt-vf0401 = <800000>;
  2238. + opp-microvolt-vf0500 = <800000>;
  2239. + opp-microvolt-vf0501 = <800000>;
  2240. + opp-microvolt-26m-vf0000 = <800000>;
  2241. + opp-microvolt-26m-vf0200 = <800000>;
  2242. + opp-microvolt-26m-vf0201 = <800000>;
  2243. + opp-microvolt-26m-vf0202 = <800000>;
  2244. + opp-microvolt-26m-vf0203 = <800000>;
  2245. + opp-microvolt-26m-vf0204 = <800000>;
  2246. + opp-microvolt-26m-vf0205 = <800000>;
  2247. + opp-microvolt-26m-vf0206 = <800000>;
  2248. + opp-microvolt-26m-vf0300 = <800000>;
  2249. + opp-microvolt-26m-vf0400 = <800000>;
  2250. + opp-microvolt-26m-vf0401 = <800000>;
  2251. + opp-microvolt-26m-vf0500 = <800000>;
  2252. + opp-microvolt-26m-vf0501 = <800000>;
  2253. + };
  2254. +
  2255. + npu_opp_table_852: opp-852 {
  2256. + opp-hz = /bits/ 64 <852000000>;
  2257. + opp-microvolt-vf0000 = <800000>;
  2258. + opp-microvolt-vf0200 = <800000>;
  2259. + opp-microvolt-vf0201 = <800000>;
  2260. + opp-microvolt-vf0202 = <880000>;
  2261. + opp-microvolt-vf0203 = <880000>;
  2262. + opp-microvolt-vf0204 = <880000>;
  2263. + opp-microvolt-vf0400 = <800000>;
  2264. + opp-microvolt-vf0401 = <820000>;
  2265. + opp-microvolt-vf0500 = <800000>;
  2266. + opp-microvolt-vf0501 = <800000>;
  2267. + opp-microvolt-26m-vf0000 = <800000>;
  2268. + opp-microvolt-26m-vf0200 = <800000>;
  2269. + opp-microvolt-26m-vf0201 = <800000>;
  2270. + opp-microvolt-26m-vf0202 = <880000>;
  2271. + opp-microvolt-26m-vf0203 = <880000>;
  2272. + opp-microvolt-26m-vf0204 = <800000>;
  2273. + opp-microvolt-26m-vf0400 = <800000>;
  2274. + opp-microvolt-26m-vf0401 = <820000>;
  2275. + opp-microvolt-26m-vf0500 = <800000>;
  2276. + opp-microvolt-26m-vf0501 = <800000>;
  2277. + };
  2278. +
  2279. + npu_opp_table_1008: opp-1008 {
  2280. + opp-hz = /bits/ 64 <1008000000>;
  2281. + opp-microvolt-vf0000 = <960000>;
  2282. + opp-microvolt-vf0200 = <960000>;
  2283. + opp-microvolt-vf0202 = <1030000>;
  2284. + opp-microvolt-vf0203 = <1030000>;
  2285. + opp-microvolt-vf0204 = <1000000>;
  2286. + opp-microvolt-vf0205 = <960000>;
  2287. + opp-microvolt-vf0206 = <900000>;
  2288. + opp-microvolt-vf0300 = <900000>;
  2289. + opp-microvolt-vf0401 = <960000>;
  2290. + opp-microvolt-vf0501 = <900000>;
  2291. + opp-microvolt-26m-vf0000 = <960000>;
  2292. + opp-microvolt-26m-vf0200 = <960000>;
  2293. + opp-microvolt-26m-vf0202 = <1030000>;
  2294. + opp-microvolt-26m-vf0203 = <1030000>;
  2295. + opp-microvolt-26m-vf0204 = <1000000>;
  2296. + opp-microvolt-26m-vf0205 = <960000>;
  2297. + opp-microvolt-26m-vf0206 = <900000>;
  2298. + opp-microvolt-26m-vf0300 = <900000>;
  2299. + opp-microvolt-26m-vf0401 = <960000>;
  2300. + opp-microvolt-26m-vf0501 = <900000>;
  2301. + };
  2302. +
  2303. + npu_opp_table_1120: opp-1120 {
  2304. + opp-hz = /bits/ 64 <1120000000>;
  2305. + opp-microvolt-vf0205 = <1080000>;
  2306. + opp-microvolt-vf0206 = <1040000>;
  2307. + opp-microvolt-vf0300 = <1040000>;
  2308. + opp-microvolt-26m-vf0205 = <1080000>;
  2309. + opp-microvolt-26m-vf0206 = <1040000>;
  2310. + opp-microvolt-26m-vf0300 = <1040000>;
  2311. + };
  2312. + };
  2313. +
  2314. + ve_opp_table: ve-opp-table {
  2315. + compatible = "allwinner,ve-operating-points";
  2316. +
  2317. + opp-vf0000 {
  2318. + opp-hz-0 = /bits/ 64 <624000000>;
  2319. + opp-microvolt-0 = <800000>;
  2320. + };
  2321. + opp-vf0100 {
  2322. + opp-hz-0 = /bits/ 64 <624000000>;
  2323. + opp-microvolt-0 = <800000>;
  2324. + };
  2325. + opp-vf0101 {
  2326. + opp-hz-0 = /bits/ 64 <624000000>;
  2327. + opp-microvolt-0 = <800000>;
  2328. + };
  2329. + opp-vf0200 {
  2330. + opp-hz-0 = /bits/ 64 <624000000>;
  2331. + opp-microvolt-0 = <800000>;
  2332. + };
  2333. + opp-vf0201 {
  2334. + opp-hz-0 = /bits/ 64 <624000000>;
  2335. + opp-microvolt-0 = <800000>;
  2336. + };
  2337. + opp-vf0300 {
  2338. + opp-hz-0 = /bits/ 64 <624000000>;
  2339. + opp-microvolt-0 = <800000>;
  2340. + };
  2341. + opp-vf0400 {
  2342. + opp-hz-0 = /bits/ 64 <624000000>;
  2343. + opp-microvolt-0 = <800000>;
  2344. + };
  2345. + opp-vf0500 {
  2346. + opp-hz-0 = /bits/ 64 <624000000>;
  2347. + opp-microvolt-0 = <800000>;
  2348. + };
  2349. + opp-vf0600 {
  2350. + opp-hz-0 = /bits/ 64 <624000000>;
  2351. + opp-microvolt-0 = <800000>;
  2352. + };
  2353. + opp-vf0401 {
  2354. + opp-hz-0 = /bits/ 64 <624000000>;
  2355. + opp-microvolt-0 = <800000>;
  2356. + };
  2357. + opp-vf0501 {
  2358. + opp-hz-0 = /bits/ 64 <624000000>;
  2359. + opp-microvolt-0 = <800000>;
  2360. + };
  2361. + };
  2362. +};
  2363. diff --git a/arch/arm64/boot/dts/allwinner/sun60iw2p1.dtsi b/arch/arm64/boot/dts/allwinner/sun60iw2p1.dtsi
  2364. new file mode 100644
  2365. index 000000000000..cc75d8dd6250
  2366. --- /dev/null
  2367. +++ b/arch/arm64/boot/dts/allwinner/sun60iw2p1.dtsi
  2368. @@ -0,0 +1,5006 @@
  2369. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  2370. +#include <dt-bindings/clock/sun60iw2-ccu.h>
  2371. +#include <dt-bindings/clock/sun60iw2-rtc.h>
  2372. +// #include <dt-bindings/clock/sun60i-a733-rtc.h>
  2373. +#include <dt-bindings/clock/sun60iw2-r-ccu.h>
  2374. +#include <dt-bindings/clock/sun60iw2-cpupll-ccu.h>
  2375. +#include <dt-bindings/clock/sunxi-ccu.h>
  2376. +#include <dt-bindings/gpio/gpio.h>
  2377. +#include <dt-bindings/gpio/sun4i-gpio.h>
  2378. +#include <dt-bindings/interrupt-controller/arm-gic.h>
  2379. +#include <dt-bindings/reset/sun60iw2-ccu.h>
  2380. +#include <dt-bindings/reset/sun60iw2-r-ccu.h>
  2381. +// #include <dt-bindings/power/sun60iw2-power.h>
  2382. +#include <dt-bindings/power/allwinner,sun60i-a733-pck-600.h>
  2383. +#include <dt-bindings/phy/phy.h>
  2384. +#include <dt-bindings/usb/pd.h>
  2385. +#include <dt-bindings/thermal/thermal.h>
  2386. +#include <dt-bindings/display/sunxi-lcd.h>
  2387. +#include <dt-bindings/spi/sunxi-spi.h>
  2388. +#include "sun60iw2p1-cpu-vf.dtsi"
  2389. +
  2390. +/ {
  2391. + model = "sun60iw2";
  2392. + interrupt-parent = <&wakeupgen>;
  2393. + #address-cells = <2>;
  2394. + #size-cells = <2>;
  2395. +
  2396. + aliases {
  2397. + ethernet0 = &gmac0;
  2398. + ethernet1 = &gmac1;
  2399. + sunxi-mmc0 = &sdc0;
  2400. + sunxi-mmc2 = &sdc3;
  2401. + pwm0 = &pwm0;
  2402. + pwm1 = &pwm1;
  2403. + pwm2 = &s_pwm0;
  2404. + spi0 = &spi0;
  2405. + spi1 = &spi1;
  2406. + spi2 = &spi2;
  2407. + spi3 = &spi3;
  2408. + spi4 = &spi4;
  2409. + spi5 = &r_spi;
  2410. + gpadc0 = &gpadc0;
  2411. + ir0 = &irrx;
  2412. + ir1 = &s_irrx;
  2413. + ir2 = &irtx;
  2414. + };
  2415. +
  2416. + cpus {
  2417. + #address-cells = <1>;
  2418. + #size-cells = <0>;
  2419. +
  2420. + cpu0: cpu@0 {
  2421. + device_type = "cpu";
  2422. + compatible = "arm,cortex-a55";
  2423. + reg = <0x000>;
  2424. + enable-method = "psci";
  2425. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2426. + capacity-dmips-mhz = <430>;
  2427. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2428. + operating-points-v2 = <&cluster0_opp_table>;
  2429. + dynamic-power-coefficient = <162>;
  2430. + #cooling-cells = <2>;
  2431. + };
  2432. +
  2433. + cpu1: cpu@100 {
  2434. + device_type = "cpu";
  2435. + compatible = "arm,cortex-a55";
  2436. + reg = <0x100>;
  2437. + enable-method = "psci";
  2438. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2439. + capacity-dmips-mhz = <430>;
  2440. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2441. + operating-points-v2 = <&cluster0_opp_table>;
  2442. + dynamic-power-coefficient = <162>;
  2443. + #cooling-cells = <2>;
  2444. + };
  2445. +
  2446. + cpu2: cpu@200 {
  2447. + device_type = "cpu";
  2448. + compatible = "arm,cortex-a55";
  2449. + reg = <0x200>;
  2450. + enable-method = "psci";
  2451. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2452. + capacity-dmips-mhz = <430>;
  2453. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2454. + operating-points-v2 = <&cluster0_opp_table>;
  2455. + dynamic-power-coefficient = <162>;
  2456. + #cooling-cells = <2>;
  2457. +
  2458. + cpu2_idle: thermal-idle {
  2459. + #cooling-cells = <2>;
  2460. + duration-us = <10000>;
  2461. + exit-latency-us = <500>;
  2462. + };
  2463. + };
  2464. +
  2465. + cpu3: cpu@300 {
  2466. + device_type = "cpu";
  2467. + compatible = "arm,cortex-a55";
  2468. + reg = <0x300>;
  2469. + enable-method = "psci";
  2470. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2471. + capacity-dmips-mhz = <430>;
  2472. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2473. + operating-points-v2 = <&cluster0_opp_table>;
  2474. + dynamic-power-coefficient = <162>;
  2475. + #cooling-cells = <2>;
  2476. +
  2477. + cpu3_idle: thermal-idle {
  2478. + #cooling-cells = <2>;
  2479. + duration-us = <10000>;
  2480. + exit-latency-us = <500>;
  2481. + };
  2482. + };
  2483. +
  2484. + cpu4: cpu@400 {
  2485. + device_type = "cpu";
  2486. + compatible = "arm,cortex-a55";
  2487. + reg = <0x400>;
  2488. + enable-method = "psci";
  2489. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2490. + capacity-dmips-mhz = <430>;
  2491. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2492. + operating-points-v2 = <&cluster0_opp_table>;
  2493. + dynamic-power-coefficient = <162>;
  2494. + #cooling-cells = <2>;
  2495. +
  2496. + cpu4_idle: thermal-idle {
  2497. + #cooling-cells = <2>;
  2498. + duration-us = <10000>;
  2499. + exit-latency-us = <500>;
  2500. + };
  2501. + };
  2502. +
  2503. + cpu5: cpu@500 {
  2504. + device_type = "cpu";
  2505. + compatible = "arm,cortex-a55";
  2506. + reg = <0x500>;
  2507. + enable-method = "psci";
  2508. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2509. + capacity-dmips-mhz = <430>;
  2510. + clocks = <&cpupll_ccu CLK_PLL_CPU_L>;
  2511. + operating-points-v2 = <&cluster0_opp_table>;
  2512. + dynamic-power-coefficient = <162>;
  2513. + #cooling-cells = <2>;
  2514. +
  2515. + cpu5_idle: thermal-idle {
  2516. + #cooling-cells = <2>;
  2517. + duration-us = <10000>;
  2518. + exit-latency-us = <500>;
  2519. + };
  2520. + };
  2521. +
  2522. + cpu6: cpu@600 {
  2523. + device_type = "cpu";
  2524. + compatible = "arm,cortex-a76";
  2525. + reg = <0x600>;
  2526. + enable-method = "psci";
  2527. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2528. + capacity-dmips-mhz = <1024>;
  2529. + clocks = <&cpupll_ccu CLK_PLL_CPU_B>;
  2530. + operating-points-v2 = <&cluster1_opp_table>;
  2531. + dynamic-power-coefficient = <598>;
  2532. + #cooling-cells = <2>;
  2533. +
  2534. + cpu6_idle: thermal-idle {
  2535. + #cooling-cells = <2>;
  2536. + duration-us = <10000>;
  2537. + exit-latency-us = <500>;
  2538. + };
  2539. + };
  2540. +
  2541. + cpu7: cpu@700 {
  2542. + device_type = "cpu";
  2543. + compatible = "arm,cortex-a76";
  2544. + reg = <0x700>;
  2545. + enable-method = "psci";
  2546. + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  2547. + capacity-dmips-mhz = <1024>;
  2548. + clocks = <&cpupll_ccu CLK_PLL_CPU_B>;
  2549. + operating-points-v2 = <&cluster1_opp_table>;
  2550. + dynamic-power-coefficient = <598>;
  2551. + #cooling-cells = <2>;
  2552. +
  2553. + cpu7_idle: thermal-idle {
  2554. + #cooling-cells = <2>;
  2555. + duration-us = <10000>;
  2556. + exit-latency-us = <500>;
  2557. + };
  2558. + };
  2559. +
  2560. + cpu-map {
  2561. + cluster0 {
  2562. + core0 {
  2563. + cpu = <&cpu0>;
  2564. + };
  2565. + core1 {
  2566. + cpu = <&cpu1>;
  2567. + };
  2568. + core2 {
  2569. + cpu = <&cpu2>;
  2570. + };
  2571. + core3 {
  2572. + cpu = <&cpu3>;
  2573. + };
  2574. + core4 {
  2575. + cpu = <&cpu4>;
  2576. + };
  2577. + core5 {
  2578. + cpu = <&cpu5>;
  2579. + };
  2580. + };
  2581. +
  2582. + cluster1 {
  2583. + core0 {
  2584. + cpu = <&cpu6>;
  2585. + };
  2586. + core1 {
  2587. + cpu = <&cpu7>;
  2588. + };
  2589. + };
  2590. + };
  2591. +
  2592. + idle-states {
  2593. + entry-method = "psci";
  2594. +
  2595. + CPU_SLEEP_0: cpu-sleep-0 {
  2596. + compatible = "arm,idle-state";
  2597. + arm,psci-suspend-param = <0x0010000>;
  2598. + entry-latency-us = <46>;
  2599. + exit-latency-us = <59>;
  2600. + min-residency-us = <3570>;
  2601. + local-timer-stop;
  2602. + };
  2603. +
  2604. + CLUSTER_SLEEP_0: cluster-sleep-0 {
  2605. + compatible = "arm,idle-state";
  2606. + arm,psci-suspend-param = <0x1010000>;
  2607. + entry-latency-us = <47>;
  2608. + exit-latency-us = <74>;
  2609. + min-residency-us = <5000>;
  2610. + local-timer-stop;
  2611. + };
  2612. + };
  2613. + };
  2614. +
  2615. + pmu-a55 {
  2616. + compatible = "arm,cortex-a55-pmu";
  2617. + interrupt-parent = <&gic>;
  2618. + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  2619. + };
  2620. +
  2621. + pmu-a76 {
  2622. + compatible = "arm,cortex-a76-pmu";
  2623. + interrupt-parent = <&gic>;
  2624. + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  2625. + };
  2626. +
  2627. + psci {
  2628. + compatible = "arm,psci-1.0";
  2629. + method = "smc";
  2630. + };
  2631. +
  2632. + timer {
  2633. + compatible = "arm,armv8-timer";
  2634. + arm,no-tick-in-suspend;
  2635. + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
  2636. + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
  2637. + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
  2638. + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
  2639. + interrupt-parent = <&gic>;
  2640. + clock-frequency = <24000000>;
  2641. + };
  2642. +
  2643. + reg_vdd_sys: vdd-sys {
  2644. + compatible = "regulator-fixed";
  2645. + regulator-name = "vdd_sys";
  2646. + regulator-min-microvolt = <900000>;
  2647. + regulator-max-microvolt = <900000>;
  2648. + regulator-boot-on;
  2649. + regulator-always-on;
  2650. + };
  2651. +
  2652. + reserved-memory {
  2653. + #address-cells = <2>;
  2654. + #size-cells = <2>;
  2655. + ranges;
  2656. +
  2657. + bl31 {
  2658. + reg = <0x0 0x48000000 0x0 0x01000000>;
  2659. + };
  2660. + };
  2661. +
  2662. + chosen {
  2663. + bootargs = "earlyprintk=sunxi-uart,0x2500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init";
  2664. + linux,initrd-start = <0x0 0x0>;
  2665. + linux,initrd-end = <0x0 0x0>;
  2666. + rng-seed; /* This random value should be provided by bootloader */
  2667. + kaslr-seed; /* This random value should be provided by bootloader */
  2668. + };
  2669. +
  2670. + /* avoid panic when memory-node err(from uboot) */
  2671. + memory@40000000 {
  2672. + device_type = "memory";
  2673. + reg = <0x0 0x40000000 0x0 0x20000000>;
  2674. + };
  2675. +
  2676. + dcxo19_2M: dcxo19_2M_clk {
  2677. + #clock-cells = <0>;
  2678. + compatible = "fixed-clock";
  2679. + clock-frequency = <19200000>;
  2680. + clock-output-names = "dcxo19_2M";
  2681. + };
  2682. +
  2683. + dcxo24M: dcxo24M_clk {
  2684. + #clock-cells = <0>;
  2685. + compatible = "fixed-clock";
  2686. + clock-frequency = <24000000>;
  2687. + clock-output-names = "dcxo24M";
  2688. + };
  2689. +
  2690. + dcxo26M: dcxo26M_clk {
  2691. + #clock-cells = <0>;
  2692. + compatible = "fixed-clock";
  2693. + clock-frequency = <26000000>;
  2694. + clock-output-names = "dcxo26M";
  2695. + };
  2696. +
  2697. + sys24M: sys24M_clk {
  2698. + #clock-cells = <0>;
  2699. + compatible = "fixed-clock";
  2700. + clock-frequency = <24000000>;
  2701. + clock-output-names = "sys24M";
  2702. + };
  2703. +
  2704. + rc_16m: rc16m_clk {
  2705. + #clock-cells = <0>;
  2706. + compatible = "fixed-clock";
  2707. + clock-frequency = <16000000>;
  2708. + clock-accuracy = <300000000>;
  2709. + clock-output-names = "rc-16m";
  2710. + };
  2711. +
  2712. + ext_32k: ext32k_clk {
  2713. + #clock-cells = <0>;
  2714. + compatible = "fixed-clock";
  2715. + clock-frequency = <32768>;
  2716. + clock-output-names = "ext-32k";
  2717. + };
  2718. +
  2719. + gic: interrupt-controller@3400000 {
  2720. + compatible = "arm,gic-v3";
  2721. + reg = <0x0 0x03400000 0x0 0x10000>, /* GIC Dist */
  2722. + <0x0 0x03460000 0x0 0xFF004>; /* GIC Re */
  2723. + #interrupt-cells = <3>;
  2724. + #address-cells = <0>;
  2725. + interrupt-controller;
  2726. + interrupt-parent = <&gic>;
  2727. +
  2728. + ppi-partitions {
  2729. + ppi_partition0: interrupt-partition-0 {
  2730. + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
  2731. + };
  2732. +
  2733. + ppi_partition1: interrupt-partition-1 {
  2734. + affinity = <&cpu6 &cpu7>;
  2735. + };
  2736. + };
  2737. + };
  2738. +
  2739. + wakeupgen: interrupt-controller@0 {
  2740. + compatible = "allwinner,sunxi-wakeupgen";
  2741. + interrupt-controller;
  2742. + #interrupt-cells = <3>;
  2743. + #address-cells = <0>;
  2744. + interrupt-parent = <&gic>;
  2745. + };
  2746. +
  2747. + nmi_intc: intc-nmi@7010320 {
  2748. + compatible = "allwinner,sun8i-nmi";
  2749. + interrupt-parent = <&gic>;
  2750. + #interrupt-cells = <2>;
  2751. + #address-cells = <0>;
  2752. + interrupt-controller;
  2753. + reg = <0x0 0x07010320 0x0 0xc>;
  2754. + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
  2755. + };
  2756. +
  2757. + mmu_aw: iommu@3900000 {
  2758. + compatible = "allwinner,iommu-v20";
  2759. + reg = <0x0 0x03900000 0x0 0x20000>;
  2760. + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
  2761. + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
  2762. + interrupt-names = "iommu-irq1","iommu-irq2";
  2763. + clocks = <&ccu CLK_IOMMU0_SYS_H>,
  2764. + <&ccu CLK_IOMMU0_SYS_P>,
  2765. + <&ccu CLK_IOMMU0_SYS_MBUS>,
  2766. + <&ccu CLK_IOMMU1_SYS_H>,
  2767. + <&ccu CLK_IOMMU1_SYS_P>,
  2768. + <&ccu CLK_IOMMU1_SYS_MBUS>
  2769. + ;
  2770. + clock-names = "iommu0-sys-hclk",
  2771. + "iommu0-sys-pclk",
  2772. + "iommu0-sys-mclk",
  2773. + "iommu1-sys-hclk",
  2774. + "iommu1-sys-pclk",
  2775. + "iommu1-sys-mclk"
  2776. + ;
  2777. + resets = <&ccu RST_BUS_IOMMU0_SY>, <&ccu RST_BUS_IOMMU1_SY>;
  2778. + /* clock-frequency = <24000000>; */
  2779. + #iommu-cells = <2>;
  2780. + version=<0x16>;
  2781. + tlb_prefetch = <0x3007f>;
  2782. + tlb_invalid_mode = <0x1>;
  2783. + ptw_invalid_mode = <0x1>;
  2784. + masters = "USB", "CSI", "ISP", "VE_ENC", "dummy04", "dummy05",
  2785. + "VE_DEC0", "VE_DEC1", "DE0","DI","G2D","EINK", "DEBUG_MODE";
  2786. +
  2787. + usb_iommu {
  2788. + iommu-master;
  2789. + id=<0>;
  2790. + };
  2791. +
  2792. + csi_iommu {
  2793. + iommu-master;
  2794. + id=<1>;
  2795. + power-domains = <&pck600 PD_VI>;
  2796. + };
  2797. +
  2798. + isp_iommu {
  2799. + iommu-master;
  2800. + id=<2>;
  2801. + power-domains = <&pck600 PD_VI>;
  2802. + };
  2803. +
  2804. + ve_enc_iommu {
  2805. + iommu-master;
  2806. + id=<3>;
  2807. + power-domains = <&pck600 PD_VE_ENC>;
  2808. + };
  2809. +
  2810. + dummy04 {
  2811. + iommu-master;
  2812. + id=<4>;
  2813. + skip;
  2814. + };
  2815. + dummy05 {
  2816. + iommu-master;
  2817. + id=<5>;
  2818. + skip;
  2819. + };
  2820. +
  2821. + ve_dec0_iommu {
  2822. + iommu-master;
  2823. + id=<6>;
  2824. + power-domains = <&pck600 PD_VE_DEC>;
  2825. + };
  2826. +
  2827. + ve_dec1_iommu {
  2828. + iommu-master;
  2829. + id=<7>;
  2830. + power-domains = <&pck600 PD_VE_DEC>;
  2831. + };
  2832. +
  2833. + de0_iommu {
  2834. + iommu-master;
  2835. + id=<8>;
  2836. + power-domains = <&pck600 PD_DE_SYS>;
  2837. + };
  2838. +
  2839. + di_iommu {
  2840. + iommu-master;
  2841. + id=<9>;
  2842. + power-domains = <&pck600 PD_DE_SYS>;
  2843. + };
  2844. +
  2845. + g2d_iommu {
  2846. + iommu-master;
  2847. + id=<10>;
  2848. + power-domains = <&pck600 PD_DE_SYS>;
  2849. + };
  2850. +
  2851. + eink_iommu {
  2852. + iommu-master;
  2853. + id=<11>;
  2854. + power-domains = <&pck600 PD_DE_SYS>;
  2855. + };
  2856. + };
  2857. +
  2858. + dsufreq: dsufreq@0 {
  2859. + compatible = "allwinner,dsufreq";
  2860. + reg = <0x0 0x08860000 0x0 0x1000>;
  2861. + clocks = <&cpupll_ccu CLK_PLL_CPU_DSU>;
  2862. + operating-points-v2 = <&dsu_opp_table>;
  2863. + };
  2864. +
  2865. +
  2866. + thermal_zones: thermal-zones {
  2867. + cpul_thermal_zone: cpul_thermal_zone {
  2868. + polling-delay-passive = <100>;
  2869. + polling-delay = <1000>;
  2870. + thermal-sensors = <&ths 3>;
  2871. + sustainable-power = <756>;
  2872. +
  2873. + cpul_trips: trips {
  2874. + cpul_threshold: trip-point@0 {
  2875. + temperature = <70000>;
  2876. + type = "passive";
  2877. + hysteresis = <2000>;
  2878. + };
  2879. + cpul_target: trip-point@1 {
  2880. + temperature = <90000>;
  2881. + type = "passive";
  2882. + hysteresis = <2000>;
  2883. + };
  2884. + cpul_crit: cpu_crit@0 {
  2885. + temperature = <110000>;
  2886. + type = "critical";
  2887. + hysteresis = <0>;
  2888. + };
  2889. + };
  2890. +
  2891. + cooling-maps {
  2892. + map0 {
  2893. + trip = <&cpul_target>;
  2894. + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  2895. + contribution = <1024>;
  2896. + };
  2897. + };
  2898. + };
  2899. +
  2900. + cpub_thermal_zone: cpub_thermal_zone {
  2901. + polling-delay-passive = <100>;
  2902. + polling-delay = <1000>;
  2903. + thermal-sensors = <&ths 0>;
  2904. + sustainable-power = <914>;
  2905. +
  2906. + cpub_trips: trips {
  2907. + cpub_threshold: trip-point@0 {
  2908. + temperature = <70000>;
  2909. + type = "passive";
  2910. + hysteresis = <2000>;
  2911. + };
  2912. + cpub_target: trip-point@1 {
  2913. + temperature = <90000>;
  2914. + type = "passive";
  2915. + hysteresis = <2000>;
  2916. + };
  2917. + cpub_crit: cpu_crit@0 {
  2918. + temperature = <110000>;
  2919. + type = "critical";
  2920. + hysteresis = <0>;
  2921. + };
  2922. + };
  2923. +
  2924. + cooling-maps {
  2925. + map0 {
  2926. + trip = <&cpub_target>;
  2927. + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  2928. + contribution = <1024>;
  2929. + };
  2930. + };
  2931. + };
  2932. +
  2933. + cpul_idle_zone: cpul_idle_zone {
  2934. + polling-delay-passive = <100>;
  2935. + polling-delay = <1000>;
  2936. + thermal-sensors = <&ths 5>;
  2937. +
  2938. + cpul_idle_trips: trips {
  2939. + cpul_thres: trip-point@0 {
  2940. + temperature = <90000>;
  2941. + type = "passive";
  2942. + hysteresis = <2000>;
  2943. + };
  2944. + cpul_overshot: trip-point@1{
  2945. + temperature = <100000>;
  2946. + type = "passive";
  2947. + hysteresis = <2000>;
  2948. + };
  2949. + };
  2950. +
  2951. + cooling-maps {
  2952. + map0 {
  2953. + trip = <&cpul_overshot>;
  2954. + cooling-device = <&cpu2_idle 0 50>,
  2955. + <&cpu3_idle 0 50>,
  2956. + <&cpu4_idle 0 50>,
  2957. + <&cpu5_idle 0 50>;
  2958. + contribution = <1024>;
  2959. + };
  2960. + };
  2961. + };
  2962. +
  2963. + cpub_idle_zone: cpub_idle_zone {
  2964. + polling-delay-passive = <100>;
  2965. + polling-delay = <1000>;
  2966. + thermal-sensors = <&ths 6>;
  2967. +
  2968. + cpub_idle_trips: trips {
  2969. + cpub_thres: trip-point@0 {
  2970. + temperature = <90000>;
  2971. + type = "passive";
  2972. + hysteresis = <2000>;
  2973. + };
  2974. + cpub_overshot: trip-point@1{
  2975. + temperature = <100000>;
  2976. + type = "passive";
  2977. + hysteresis = <2000>;
  2978. + };
  2979. + };
  2980. +
  2981. + cooling-maps {
  2982. + map0 {
  2983. + trip = <&cpub_overshot>;
  2984. + cooling-device = <&cpu6_idle 0 100>,
  2985. + <&cpu7_idle 0 100>;
  2986. + contribution = <1024>;
  2987. + };
  2988. + };
  2989. + };
  2990. +
  2991. + gpu_thermal_zone: gpu_thermal_zone {
  2992. + polling-delay-passive = <100>;
  2993. + polling-delay = <1000>;
  2994. + thermal-sensors = <&ths 4>;
  2995. + sustainable-power = <2400>;
  2996. +
  2997. + gpu_trips: trips {
  2998. + gpu_threshold: trip-point@0 {
  2999. + temperature = <60000>;
  3000. + type = "passive";
  3001. + hysteresis = <0>;
  3002. + };
  3003. + gpu_target: trip-point@1 {
  3004. + temperature = <90000>;
  3005. + type = "passive";
  3006. + hysteresis = <0>;
  3007. + };
  3008. + gpu_crit: gpu_crit@0 {
  3009. + temperature = <110000>;
  3010. + type = "critical";
  3011. + hysteresis = <0>;
  3012. + };
  3013. + };
  3014. +
  3015. + cooling-maps {
  3016. + map0 {
  3017. + trip = <&gpu_threshold>;
  3018. + cooling-device = <&gpu
  3019. + 0
  3020. + 0>;
  3021. + contribution = <1024>;
  3022. + };
  3023. + map1 {
  3024. + trip = <&gpu_target>;
  3025. + cooling-device = <&gpu
  3026. + 0
  3027. + 3>;
  3028. + contribution = <1024>;
  3029. + };
  3030. + map2 {
  3031. + trip = <&gpu_crit>;
  3032. + cooling-device = <&gpu
  3033. + 3
  3034. + 3>;
  3035. + contribution = <1024>;
  3036. + };
  3037. +
  3038. + };
  3039. + };
  3040. +
  3041. + npu_thermal_zone: npu_thermal_zone {
  3042. + polling-delay-passive = <100>;
  3043. + polling-delay = <1000>;
  3044. + thermal-sensors = <&ths 2>;
  3045. +
  3046. + npu_trips: trips {
  3047. + npu_crit: npu_crit@0 {
  3048. + temperature = <110000>;
  3049. + type = "critical";
  3050. + hysteresis = <0>;
  3051. + };
  3052. + };
  3053. + };
  3054. +
  3055. + ddr_thermal_zone: ddr_thermal_zone {
  3056. + polling-delay-passive = <0>;
  3057. + polling-delay = <0>;
  3058. + thermal-sensors = <&ths 1>;
  3059. +
  3060. + ddr_trips: trips {
  3061. + ddr_crit: ddr_crit@0 {
  3062. + temperature = <110000>;
  3063. + type = "critical";
  3064. + hysteresis = <0>;
  3065. + };
  3066. + };
  3067. + };
  3068. +
  3069. + skin_zone {
  3070. + polling-delay-passive = <0>;
  3071. + polling-delay = <0>;
  3072. + thermal-sensors = <&ths 7>;
  3073. +
  3074. + skin_trips: trips {
  3075. + skin_crit: skin_crit@0 {
  3076. + temperature = <50000>;
  3077. + type = "critical";
  3078. + hysteresis = <0>;
  3079. + };
  3080. + };
  3081. + };
  3082. + };
  3083. +
  3084. + pck600: power-controller@7060000 {
  3085. + compatible = "allwinner,sun60i-a733-pck-600";
  3086. + reg = <0x0 0x07060000 0x0 0xB000>;
  3087. + clocks = <&r_ccu CLK_R_PPU>;
  3088. + #power-domain-cells = <1>;
  3089. + };
  3090. +
  3091. + dram: dram {
  3092. + compatible = "allwinner,dram";
  3093. + clocks = <&ccu CLK_PLL_DDR>;
  3094. + clock-names = "pll_ddr";
  3095. + };
  3096. +
  3097. + ddr_clk: clk_ddr {
  3098. + compatible = "allwinner,sun60iw2_clock_ddr";
  3099. + reg = <0x0 0x02002000 0x0 0x1000>;
  3100. + clocks = <&ccu CLK_PLL_DDR>;
  3101. + clock-names = "pll_ddr";
  3102. + #clock-cells = <0>;
  3103. + };
  3104. +
  3105. + dram_opp_table: opp_table {
  3106. + compatible = "operating-points-v2";
  3107. + opp@150000000 {
  3108. + opp-hz = /bits/ 64 <150000000>;
  3109. + clock-latency-ns = <150000>;
  3110. + opp-microvolt = <900000>;
  3111. + };
  3112. + };
  3113. +
  3114. + sunxi_dmcfreq: dmcfreq@3120000 {
  3115. + compatible = "allwinner,sun60iw2-dmc", "syscon";
  3116. + reg = <0x0 0x0a020000 0x0 0x2000>,
  3117. + <0x0 0x02020000 0x0 0x4000>,
  3118. + <0x0 0x0a100000 0x0 0x11000>;
  3119. + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
  3120. + clocks = <&ddr_clk>, <&ccu CLK_NSI>;
  3121. + clock-names = "dram", "bus";
  3122. + operating-points-v2 = <&dram_opp_table>;
  3123. + upthreshold = <50>;
  3124. + downdifferential = <20>;
  3125. + holdtime = <25>;
  3126. + vddcore-supply = <&reg_vdd_sys>;
  3127. + normalvoltage = <900000>;
  3128. + boostvoltage = <900000>;
  3129. + };
  3130. +
  3131. + soc: soc@3000000 {
  3132. + compatible = "simple-bus";
  3133. + #address-cells = <2>;
  3134. + #size-cells = <2>;
  3135. + ranges;
  3136. +
  3137. + ve: ve@1c0e000 {
  3138. + compatible = "allwinner,sunxi-cedar-ve";
  3139. + reg = <0x0 0x01c0e000 0x0 0x3000>,
  3140. + <0x0 0x03000000 0x0 0x10>;
  3141. + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  3142. + clocks = <&ccu CLK_PLL_VE0>,
  3143. + <&ccu CLK_VE_AHB_GATE>,
  3144. + <&ccu CLK_DEC_MBUS_GATE>,
  3145. + <&ccu CLK_VE_DEC_MBUS>,
  3146. + <&ccu CLK_BUS_VE_DEC>,
  3147. + <&ccu CLK_VE_DEC>;
  3148. + clock-names = "pll_ve",
  3149. + "ahb_gate",
  3150. + "mbus_gate",
  3151. + "mbus_ve",
  3152. + "bus_ve",
  3153. + "ve";
  3154. + resets = <&ccu RST_BUS_VE_DEC>;
  3155. + reset-names = "reset_ve";
  3156. + operating-points-v2 = <&ve_opp_table>;
  3157. + iommus = <&mmu_aw 6 1>;
  3158. + nsi = <&nsi0 7>;
  3159. + power-domains = <&pck600 PD_VE_DEC>;
  3160. + };
  3161. +
  3162. + ve1: ve1@1c0e000 {
  3163. + compatible = "allwinner,sunxi-cedar-ve1";
  3164. + iommus = <&mmu_aw 7 1>;
  3165. + nsi = <&nsi0 8>;
  3166. + };
  3167. +
  3168. + ve2: ve2@1c10000 {
  3169. + compatible = "allwinner,sunxi-cedar-ve2";
  3170. + reg = <0x0 0x01c10000 0x0 0x1000>,
  3171. + <0x0 0x03000000 0x0 0x10>;
  3172. + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  3173. + clocks = <&ccu CLK_PLL_VE1>,
  3174. + <&ccu CLK_VE_ENC_AHB_GATE>,
  3175. + <&ccu CLK_MBUS_VE_GATE>,
  3176. + <&ccu CLK_MBUS_VE>,
  3177. + <&ccu CLK_BUS_VE_ENC>,
  3178. + <&ccu CLK_VE_ENC0>;
  3179. + clock-names = "pll_ve",
  3180. + "ahb_gate",
  3181. + "mbus_gate",
  3182. + "mbus_ve",
  3183. + "bus_ve",
  3184. + "ve";
  3185. + resets = <&ccu RST_BUS_VE_ENC0>;
  3186. + reset-names = "reset_ve";
  3187. + operating-points-v2 = <&ve_opp_table>;
  3188. + iommus = <&mmu_aw 3 1>;
  3189. + nsi = <&nsi0 9>;
  3190. + power-domains = <&pck600 PD_VE_ENC>;
  3191. + ve_top_reg_offset = <0x800>;
  3192. + };
  3193. +
  3194. + rtc_ccu: rtc_ccu@7090000 {
  3195. + compatible = "allwinner,sun60iw2-rtc-ccu";
  3196. + reg = <0x0 0x07090000 0x0 0x400>;
  3197. + #clock-cells = <1>;
  3198. + #reset-cells = <1>;
  3199. + };
  3200. +
  3201. + cpupll_ccu: cpupll_ccu@8870000 {
  3202. + compatible = "allwinner,sun60iw2-cpupll";
  3203. + reg = <0x0 0x08870000 0x0 0x3034>;
  3204. + clocks = <&rtc_ccu CLK_DCXO>;
  3205. + clock-names = "dcxo";
  3206. + #clock-cells = <1>;
  3207. + #reset-cells = <1>;
  3208. + };
  3209. +
  3210. + ccu: ccu@2002000 {
  3211. + compatible = "allwinner,sun60iw2-ccu";
  3212. + reg = <0x0 0x02002000 0x0 0x2000>;
  3213. + clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rc_16m>;
  3214. + clock-names = "hosc", "losc", "iosc";
  3215. + #clock-cells = <1>;
  3216. + #reset-cells = <1>;
  3217. + /*
  3218. + * for example
  3219. + * sdm_info: sdm_info {
  3220. + * pll-video0 {
  3221. + * sdm-enable = <1>; // required
  3222. + * sdm-factor = <4>; // required
  3223. + * freq-mod = <TR_N>; // optional: default TR_N
  3224. + * sdm-freq = <FREQ_32>; // optional: default FREQ_31_5
  3225. + * };
  3226. + * };
  3227. + */
  3228. + };
  3229. +
  3230. + r_ccu: r_ccu@7010000 {
  3231. + compatible = "allwinner,sun60iw2-r-ccu";
  3232. + reg = <0x0 0x07010000 0x0 0x340>;
  3233. + #clock-cells = <1>;
  3234. + #reset-cells = <1>;
  3235. + };
  3236. +
  3237. + dump_reg:dump_reg@44000 {
  3238. + compatible = "allwinner,sunxi-dump-reg";
  3239. + reg = <0x0 0x00044000 0x0 0x0004>;
  3240. + };
  3241. +
  3242. + soc_timer0: timer@3009000{
  3243. + compatible = "allwinner,sun50i-timer";
  3244. + device_type = "soc_timer";
  3245. + reg = <0x0 0x03009000 0x0 0x400>;
  3246. + interrupt-parent = <&gic>;
  3247. + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  3248. + clock-names = "parent", "bus", "timer0-mod", "timer1-mod";
  3249. + clocks = <&sys24M>, <&ccu CLK_BUS_TIMER>, <&ccu CLK_TIMER0>, <&ccu CLK_TIMER1>;
  3250. + resets = <&ccu RST_BUS_TIMER0>;
  3251. + };
  3252. +
  3253. + // rtc: rtc@7090000 {
  3254. + // compatible = "allwinner,sun60i-a733-rtc";
  3255. + // reg = <0x0 0x07090000 0x0 0x400>;
  3256. + // interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  3257. + // clocks = <&r_ccu CLK_RTC>,
  3258. + // <&dcxo19_2M>,
  3259. + // <&dcxo24M>,
  3260. + // <&dcxo26M>,
  3261. + // <&r_ccu CLK_R_AHB>,
  3262. + // <&ext_32k>;
  3263. + // clock-names = "bus", "osc19M", "osc24M", "osc26M", "ahb", "ext-osc32k";
  3264. + // // resets = <&r_ccu RST_BUS_RTC>;
  3265. + // #clock-cells = <1>;
  3266. + // };
  3267. +
  3268. + rtc: rtc@7090000 {
  3269. + compatible = "allwinner,rtc-v201";
  3270. + device_type = "rtc";
  3271. + wakeup-source;
  3272. + reg = <0x0 0x07090000 0x0 0x320>;
  3273. + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  3274. + clocks = <&r_ccu CLK_RTC>, <&rtc_ccu CLK_RTC_1K>, <&rtc_ccu CLK_RTC_SPI>;
  3275. + clock-names = "r-ahb-rtc", "rtc-1k", "rtc-spi";
  3276. + resets = <&r_ccu RST_BUS_RTC>;
  3277. + gpr_cur_pos = <6>;
  3278. + gpr_bootcount_pos = <7>;
  3279. + };
  3280. +
  3281. + pio: pinctrl@2000000 {
  3282. + //#address-cells = <1>;
  3283. + //#size-cells = <0>;
  3284. + compatible = "allwinner,sun60iw2-pinctrl";
  3285. + reg = <0x0 0x02000000 0x0 0x600>;
  3286. + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
  3287. + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
  3288. + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
  3289. + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
  3290. + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  3291. + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
  3292. + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  3293. + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  3294. + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  3295. + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  3296. + clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>;
  3297. + clock-names = "apb", "hosc", "losc";
  3298. + gpio-controller;
  3299. + #gpio-cells = <3>;
  3300. + interrupt-controller;
  3301. + #interrupt-cells = <3>;
  3302. +
  3303. + sdc0_pins_f: sdc0@5 {
  3304. + pins = "PF2";
  3305. + function = "sdc0";
  3306. + drive-strength = <30>;
  3307. + bias-pull-up;
  3308. + power-source = <3300>;
  3309. + };
  3310. +
  3311. + sdc0_pins_g: sdc0@6 {
  3312. + pins = "PF2";
  3313. + function = "sdc0";
  3314. + drive-strength = <30>;
  3315. + bias-pull-up;
  3316. + power-source = <1800>;
  3317. + };
  3318. +
  3319. + sdc0_pins_a: sdc0@0 {
  3320. + pins = "PF0", "PF1",
  3321. + "PF3", "PF4", "PF5";
  3322. + function = "sdc0";
  3323. + drive-strength = <10>;
  3324. + bias-pull-up;
  3325. + power-source = <3300>;
  3326. + };
  3327. +
  3328. + sdc0_pins_b: sdc0@1 {
  3329. + pins = "PF0", "PF1",
  3330. + "PF3", "PF4", "PF5";
  3331. + function = "sdc0";
  3332. + drive-strength = <10>;
  3333. + bias-pull-up;
  3334. + power-source = <1800>;
  3335. + };
  3336. +
  3337. + sdc0_pins_c: sdc0@2 {
  3338. + pins = "PF0", "PF1", "PF2",
  3339. + "PF3", "PF4", "PF5";
  3340. + function = "gpio_in";
  3341. + power-source = <3300>;
  3342. + };
  3343. +
  3344. + /* TODO: add jtag pin */
  3345. + sdc0_pins_d: sdc0@3 {
  3346. + pins = "PF2", "PF4";
  3347. + function = "uart0";
  3348. + drive-strength = <10>;
  3349. + bias-pull-up;
  3350. + power-source = <3300>;
  3351. + };
  3352. +
  3353. + sdc0_pins_e: sdc0@4 {
  3354. + pins = "PF0", "PF1", "PF3",
  3355. + "PF5";
  3356. + function = "jtag";
  3357. + drive-strength = <10>;
  3358. + bias-pull-up;
  3359. + power-source = <3300>;
  3360. + };
  3361. +
  3362. + sdc1_pins_a: sdc1@0 {
  3363. + pins = "PG1", "PG2",
  3364. + "PG3", "PG4", "PG5";
  3365. + function = "sdc1";
  3366. + drive-strength = <10>;
  3367. + bias-pull-up;
  3368. + };
  3369. +
  3370. + sdc1_pins_b: sdc1@1 {
  3371. + pins = "PG0", "PG1", "PG2",
  3372. + "PG3", "PG4", "PG5";
  3373. + function = "gpio_in";
  3374. + };
  3375. +
  3376. + sdc1_pins_c: sdc1@2 {
  3377. + pins = "PG0";
  3378. + function = "sdc1";
  3379. + drive-strength = <20>;
  3380. + bias-pull-up;
  3381. + };
  3382. +
  3383. + sdc2_pins_a: sdc2@0 {
  3384. + pins = "PC6",
  3385. + "PC8", "PC9", "PC10", "PC11",
  3386. + "PC13", "PC14", "PC15", "PC16";
  3387. + function = "sdc2";
  3388. + drive-strength = <20>;
  3389. + bias-pull-up;
  3390. + };
  3391. +
  3392. + sdc2_pins_b: sdc2@1 {
  3393. + pins = "PC0", "PC1", "PC5", "PC6",
  3394. + "PC8", "PC9", "PC10", "PC11",
  3395. + "PC13", "PC14", "PC15", "PC16";
  3396. + function = "gpio_in";
  3397. + };
  3398. +
  3399. + sdc2_pins_c: sdc2@2 {
  3400. + pins = "PC0";
  3401. + function = "sdc2";
  3402. + drive-strength = <40>;
  3403. + bias-pull-down;
  3404. + };
  3405. +
  3406. + sdc2_pins_d: sdc2@3 {
  3407. + pins = "PC5", "PC1";
  3408. + function = "sdc2";
  3409. + drive-strength = <40>;
  3410. + bias-pull-up;
  3411. + };
  3412. +
  3413. + sdc3_pins_a: sdc3@0 {
  3414. + pins = "PC6",
  3415. + "PC8", "PC9", "PC10", "PC11",
  3416. + "PC13", "PC14", "PC15", "PC16";
  3417. + function = "sdc3";
  3418. + drive-strength = <20>;
  3419. + bias-pull-up;
  3420. + };
  3421. +
  3422. + sdc3_pins_b: sdc3@1 {
  3423. + pins = "PC0", "PC1", "PC5", "PC6",
  3424. + "PC8", "PC9", "PC10", "PC11",
  3425. + "PC13", "PC14", "PC15", "PC16";
  3426. + function = "gpio_in";
  3427. + };
  3428. +
  3429. + sdc3_pins_c: sdc3@2 {
  3430. + pins = "PC0";
  3431. + function = "sdc3";
  3432. + drive-strength = <40>;
  3433. + bias-pull-down;
  3434. + };
  3435. +
  3436. + sdc3_pins_d: sdc3@3 {
  3437. + pins = "PC5", "PC1";
  3438. + function = "sdc3";
  3439. + drive-strength = <40>;
  3440. + bias-pull-up;
  3441. + };
  3442. +
  3443. + csi_mclk0_pins_a: csi_mclk0@0 {
  3444. + pins = "PE0";
  3445. + function = "mcsi0";
  3446. + drive-strength = <20>;
  3447. + };
  3448. +
  3449. + csi_mclk0_pins_b: csi_mclk0@1 {
  3450. + pins = "PE0";
  3451. + function = "gpio_in";
  3452. + };
  3453. +
  3454. + csi_mclk1_pins_a: csi_mclk1@0 {
  3455. + pins = "PE5";
  3456. + function = "mcsi1";
  3457. + drive-strength = <20>;
  3458. + };
  3459. +
  3460. + csi_mclk1_pins_b: csi_mclk1@1 {
  3461. + pins = "PE5";
  3462. + function = "gpio_in";
  3463. + };
  3464. +
  3465. + csi_mclk2_pins_a: csi_mclk2@0 {
  3466. + pins = "PE9";
  3467. + function = "mcsi2";
  3468. + drive-strength = <20>;
  3469. + };
  3470. +
  3471. + csi_mclk2_pins_b: csi_mclk2@1 {
  3472. + pins = "PE9";
  3473. + function = "gpio_in";
  3474. + };
  3475. +
  3476. + ncsi0_8bit_pins_a: ncsi0_8bit@0 {
  3477. + pins = "PE0", "PE1", "PE2",
  3478. + "PE3", "PE4", "PE6", "PE7",
  3479. + "PE8", "PE9", "PE10";
  3480. + function = "ncsi0";
  3481. + drive-strength = <20>;
  3482. + };
  3483. +
  3484. + ncsi0_8bit_pins_b: ncsi0_8bit@1 {
  3485. + pins = "PE0", "PE1", "PE2",
  3486. + "PE3", "PE4", "PE6", "PE7",
  3487. + "PE8", "PE9", "PE10";
  3488. + function = "gpio_in";
  3489. + };
  3490. +
  3491. + ncsi1_8bit_pins_a: ncsi1_8bit@0 {
  3492. + pins = "PK0", "PK1", "PK2",
  3493. + "PK19", "PK18", "PK17", "PK16",
  3494. + "PK15", "PK14", "PK13", "PK12";
  3495. + function = "ncsi1";
  3496. + drive-strength = <20>;
  3497. + };
  3498. +
  3499. + ncsi1_8bit_pins_b: ncsi1_8bit@1 {
  3500. + pins = "PK0", "PK1", "PK2",
  3501. + "PK19", "PK18", "PK17", "PK16",
  3502. + "PK15", "PK14", "PK13", "PK12";
  3503. + function = "gpio_in";
  3504. + };
  3505. +
  3506. + ncsi1_16bit_pins_a: ncsi1_16bit@0 {
  3507. + pins = "PK0", "PK1", "PK2",
  3508. + "PK19", "PK18", "PK17", "PK16",
  3509. + "PK15", "PK14", "PK13", "PK12",
  3510. + "PK11", "PK10", "PK9", "PK8",
  3511. + "PK7", "PK6", "PK5", "PK4";
  3512. + function = "ncsi1";
  3513. + drive-strength = <20>;
  3514. + };
  3515. +
  3516. + ncsi1_16bit_pins_b: ncsi1_16bit@1 {
  3517. + pins = "PK0", "PK1", "PK2",
  3518. + "PK19", "PK18", "PK17", "PK16",
  3519. + "PK15", "PK14", "PK13", "PK12",
  3520. + "PK11", "PK10", "PK9", "PK8",
  3521. + "PK7", "PK6", "PK5", "PK4";
  3522. + function = "gpio_in";
  3523. + };
  3524. +
  3525. + mipia_pins_a: mipia@0 {
  3526. + pins = "PK0", "PK1", "PK2", "PK3", "PK4",
  3527. + "PK5", "PK6", "PK7", "PK8", "PK9";
  3528. + function = "mcsia";
  3529. + drive-strength = <10>;
  3530. +
  3531. + };
  3532. +
  3533. + mipia_pins_b: mipia@1 {
  3534. + pins = "PK0", "PK1", "PK2", "PK3", "PK4",
  3535. + "PK5", "PK6", "PK7", "PK8", "PK9";
  3536. + function = "gpio_in";
  3537. + };
  3538. +
  3539. + mipib_pins_a: mipib@0 {
  3540. + pins = "PK10", "PK11", "PK12", "PK13", "PK14",
  3541. + "PK15", "PK16", "PK17", "PK18", "PK19";
  3542. + function = "mcsib";
  3543. + drive-strength = <10>;
  3544. + };
  3545. +
  3546. + mipib_pins_b: mipib@1 {
  3547. + pins = "PK10", "PK11", "PK12", "PK13", "PK14",
  3548. + "PK15", "PK16", "PK17", "PK18", "PK19";
  3549. + function = "gpio_in";
  3550. +
  3551. + };
  3552. +
  3553. + mipic_pins_a: mipic@0 {
  3554. + pins = "PK20", "PK21", "PK22",
  3555. + "PK23", "PK24", "PK25";
  3556. + function = "mcsic";
  3557. + drive-strength = <10>;
  3558. +
  3559. + };
  3560. +
  3561. + mipic_pins_b: mipic@1 {
  3562. + pins = "PK20", "PK21", "PK22",
  3563. + "PK23", "PK24", "PK25";
  3564. + function = "gpio_in";
  3565. + };
  3566. +
  3567. + dsi0_4lane_pins_a: dsi0_4lane@0 {
  3568. + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
  3569. + function = "dsi0";
  3570. + drive-strength = <30>;
  3571. + bias-disable;
  3572. + };
  3573. +
  3574. + dsi0_4lane_pins_b: dsi0_4lane@1 {
  3575. + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
  3576. + function = "io_disabled";
  3577. + bias-disable;
  3578. + };
  3579. +
  3580. + dsi1_4lane_pins_a: dsi1_4lane@0 {
  3581. + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19";
  3582. + function = "dsi1";
  3583. + drive-strength = <30>;
  3584. + bias-disable;
  3585. + };
  3586. +
  3587. + dsi1_4lane_pins_b: dsi1_4lane@1 {
  3588. + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19";
  3589. + function = "io_disabled";
  3590. + bias-disable;
  3591. + };
  3592. +
  3593. + lvds0_pins_a: lvds0@0 {
  3594. + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
  3595. + function = "lvds0";
  3596. + drive-strength = <30>;
  3597. + };
  3598. +
  3599. + lvds0_pins_b: lvds0@1 {
  3600. + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9";
  3601. + function = "gpio_in";
  3602. + };
  3603. +
  3604. + lvds1_pins_a: lvds1@0 {
  3605. + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19";
  3606. + function = "lvds1";
  3607. + drive-strength = <30>;
  3608. + };
  3609. +
  3610. + lvds1_pins_b: lvds1@1 {
  3611. + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19";
  3612. + function = "gpio_in";
  3613. + };
  3614. +
  3615. + lvds2_pins_a: lvds2@0 {
  3616. + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9";
  3617. + function = "lvds2";
  3618. + drive-strength = <30>;
  3619. + };
  3620. +
  3621. + lvds2_pins_b: lvds2@1 {
  3622. + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9";
  3623. + function = "gpio_in";
  3624. + };
  3625. +
  3626. + lvds3_pins_a: lvds3@0 {
  3627. + pins = "PJ10", "PJ11", "PJ12", "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19";
  3628. + function = "lvds3";
  3629. + drive-strength = <30>;
  3630. + };
  3631. +
  3632. + lvds3_pins_b: lvds3@1 {
  3633. + pins = "PJ10", "PJ11", "PJ12", "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19";
  3634. + function = "gpio_in";
  3635. + };
  3636. +
  3637. + rgb0_24pins_a: rgb0@0 {
  3638. + pins = "PG0", "PG1", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PG2", "PG3", "PD6", "PD7", "PD8", "PD9", \
  3639. + "PD10", "PD11", "PG4", "PG5", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
  3640. + "PD20", "PD21";
  3641. + function = "lcd0";
  3642. + drive-strength = <10>;
  3643. + };
  3644. +
  3645. + rgb0_24pins_b: rgb0@1 {
  3646. + pins = "PG0", "PG1", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PG2", "PG3", "PD6", "PD7", "PD8", "PD9", \
  3647. + "PD10", "PD11", "PG4", "PG5", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
  3648. + "PD20", "PD21";
  3649. + function = "gpio_in";
  3650. + };
  3651. +
  3652. + rgb1_24pins_a: rgb1@0 {
  3653. + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", "PJ10", "PJ11", "PJ12", \
  3654. + "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19", "PJ20", "PJ21", "PJ22", "PJ23", "PJ24", \
  3655. + "PJ25", "PJ26", "PJ27";
  3656. + function = "lcd1";
  3657. + drive-strength = <10>;
  3658. + };
  3659. +
  3660. + rgb1_24pins_b: rgb1@1 {
  3661. + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", "PJ10", "PJ11", "PJ12", \
  3662. + "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19", "PJ20", "PJ21", "PJ22", "PJ23", "PJ24", \
  3663. + "PJ25", "PJ26", "PJ27";
  3664. + function = "gpio_in";
  3665. + };
  3666. + };
  3667. +
  3668. + r_pio: pinctrl@7025000 {
  3669. + #address-cells = <1>;
  3670. + compatible = "allwinner,sun60iw2-r-pinctrl";
  3671. + reg = <0x0 0x07025000 0x0 0x410>;
  3672. + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* GPIOL */
  3673. + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  3674. + clocks = <&r_ccu CLK_R_APBS0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>;
  3675. + clock-names = "apb", "hosc", "losc";
  3676. + gpio-controller;
  3677. + #gpio-cells = <3>;
  3678. + interrupt-controller;
  3679. + #interrupt-cells = <3>;
  3680. +
  3681. + r_i2c0_pins: s_twi0@0 {
  3682. + pins = "PL0", "PL1";
  3683. + function = "s_twi0";
  3684. + drive-strength = <10>;
  3685. + bias-pull-up;
  3686. + };
  3687. + };
  3688. +
  3689. + wdt: watchdog@2050000 {
  3690. + compatible = "allwinner,wdt-v103";
  3691. + reg = <0x0 0x02050000 0x0 0x20>;
  3692. + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
  3693. + };
  3694. +
  3695. + dma: dma-controller@4601000 {
  3696. + compatible = "allwinner,dma-v106";
  3697. + reg = <0x0 0x04601000 0x0 0x2000>;
  3698. + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  3699. + clocks = <&ccu CLK_DMA0>, <&ccu CLK_MBUS_DMA0>;
  3700. + clock-names = "bus", "mbus";
  3701. + dma-channels = <16>;
  3702. + dma-requests = <64>;
  3703. + resets = <&ccu RST_BUS_DMA0>;
  3704. + #dma-cells = <1>;
  3705. + };
  3706. +
  3707. + sid: sid@3006000 {
  3708. + compatible = "allwinner,sunxi-sid";
  3709. + reg = <0x0 0x03006000 0x0 0x1000>;
  3710. + #address-cells = <1>;
  3711. + #size-cells = <1>;
  3712. + non-secure-maxoffset = <0x7C>;
  3713. + non-secure-maxlen = <0x20>;
  3714. +
  3715. + secure_status {
  3716. + reg = <0x0 0>;
  3717. + offset = <0xa0>;
  3718. + size = <0x4>;
  3719. + };
  3720. + chipid {
  3721. + reg = <0x0 0>;
  3722. + offset = <0x200>;
  3723. + size = <0x10>;
  3724. + };
  3725. + rotpk {
  3726. + reg = <0x0 0>;
  3727. + offset = <0x140>;
  3728. + size = <0x20>;
  3729. + };
  3730. + ufs_cal_word_l {
  3731. + offset = <0x260>;
  3732. + mask = <0xfffffff>;
  3733. + shift = <0>;
  3734. + };
  3735. + ufs_cal_word_h {
  3736. + offset = <0x264>;
  3737. + mask = <0xfffffff>;
  3738. + shift = <0>;
  3739. + };
  3740. + dvfs_ori {
  3741. + offset = <0x24C>;
  3742. + mask = <0xff>;
  3743. + shift = <8>;
  3744. + };
  3745. + dvfs_bak {
  3746. + offset = <0x24C>;
  3747. + mask = <0xff>;
  3748. + shift = <16>;
  3749. + };
  3750. + };
  3751. +
  3752. + sram_ctrl: sram_ctrl@3000000 {
  3753. + compatible = "allwinner,sram_ctrl";
  3754. + reg = <0x0 0x03000000 0x0 0x184>;
  3755. + soc_ver {
  3756. + offset = <0x24>;
  3757. + mask = <0x7>;
  3758. + shift = <0>;
  3759. + };
  3760. + };
  3761. +
  3762. + ths: ths@2522000 {
  3763. + compatible = "allwinner,sun60iw2p1-ths";
  3764. + reg = <0x0 0x02522000 0x0 0x500>;
  3765. + clocks = <&ccu CLK_THS0>,<&ccu CLK_GPADC0_24M>;
  3766. + clock-names = "bus","gpadc";
  3767. + resets = <&ccu RST_BUS_THS0>;
  3768. + #thermal-sensor-cells = <1>;
  3769. + };
  3770. +
  3771. + nsi0: nsi-controller@2020000 {
  3772. + compatible = "allwinner,sunxi-nsi-v2";
  3773. + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
  3774. + reg = <0x0 0x02020000 0x0 0x10000>,
  3775. + <0x0 0x0A030000 0x0 0x20000>;
  3776. + clocks = <&ccu CLK_PLL_DDR>, <&ccu CLK_MBUS> , <&ccu CLK_NSI>,
  3777. + <&ccu CLK_PLL_PERI0_600M>, <&ccu CLK_GIC>, <&ccu CLK_NSI_CFG>,
  3778. + <&ccu CLK_PLL_PERI0_600M>, <&ccu CLK_DRAM0>;
  3779. + clock-names = "pll", "bus", "nsi", "nsi-p","gic", "nsi-cfg", "bus-p", "cpu_direct";
  3780. + resets = <&ccu RST_BUS_NSI>, <&ccu RST_BUS_NSI_CFG>;
  3781. + reset-names = "bus_nsi", "bus_nsi_cfg";
  3782. + clock-frequency = <600000000>,<600000000>;
  3783. + #nsi-cells = <1>;
  3784. + clk_path_type = <1>;
  3785. + topology_type = <2>;
  3786. + channel_type = <2>;
  3787. + master_clks = <6 2>,<10 4>,<18 2>,<19 2>,<20 2>,<32 2>,<33 2>;
  3788. + ia_pmu_data_unit = <16>;
  3789. + ra_pmu_data_unit = <64>;
  3790. + ta_pmu_data_unit = <64>;
  3791. + cpu_pmu_data_unit = <64>;
  3792. + sub_node_id_mapping;
  3793. +
  3794. + cpu0{
  3795. + id = <19>;
  3796. + cpu_direct_reg = <0x0A030000 0x2000>;
  3797. + cpu_direct_mux = <0x8000200 0x0 0>;
  3798. + };
  3799. + cpu1{
  3800. + id = <20>;
  3801. + cpu_direct_reg = <0x0A040000 0x2000>;
  3802. + cpu_direct_mux = <0x8000200 0x0 0>;
  3803. + };
  3804. +
  3805. + npu{
  3806. + id = <18>;
  3807. + power-domains = <&pck600 PD_NPU>;
  3808. + };
  3809. +
  3810. + usb_pcie{
  3811. + id=<13>;
  3812. + power-domains = <&pck600 PD_PCIE>;
  3813. + };
  3814. +
  3815. + // gpu{
  3816. + // id = <6>;
  3817. + // power-domains = <&pck600 PD_GPU_TOP>;
  3818. + // };
  3819. +
  3820. + iommu0{
  3821. + id = <14>;
  3822. + mode = <0>;
  3823. + pri = <3>;
  3824. + select = <1>;
  3825. + };
  3826. +
  3827. + iommu1{
  3828. + id = <15>;
  3829. + mode = <0>;
  3830. + pri = <3>;
  3831. + select = <1>;
  3832. + };
  3833. +
  3834. + de {
  3835. + id = <2>;
  3836. + mode = <0>;
  3837. + pri = <2>;
  3838. + select = <1>;
  3839. + power-domains = <&pck600 PD_DE_SYS>;
  3840. + };
  3841. +
  3842. + eink {
  3843. + id = <3>;
  3844. + mode = <0>;
  3845. + pri = <1>;
  3846. + select = <1>;
  3847. + power-domains = <&pck600 PD_DE_SYS>;
  3848. + };
  3849. +
  3850. + di {
  3851. + id = <4>;
  3852. + mode = <0>;
  3853. + pri = <1>;
  3854. + select = <1>;
  3855. + power-domains = <&pck600 PD_DE_SYS>;
  3856. + };
  3857. +
  3858. + g2d {
  3859. + id = <5>;
  3860. + mode = <0>;
  3861. + pri = <1>;
  3862. + select = <1>;
  3863. + power-domains = <&pck600 PD_DE_SYS>;
  3864. + };
  3865. +
  3866. + ve0 {
  3867. + id = <7>;
  3868. + mode = <0>;
  3869. + pri = <1>;
  3870. + select = <1>;
  3871. + power-domains = <&pck600 PD_VE_DEC>;
  3872. + };
  3873. +
  3874. + ve1 {
  3875. + id = <8>;
  3876. + mode = <0>;
  3877. + pri = <1>;
  3878. + select = <1>;
  3879. + power-domains = <&pck600 PD_VE_DEC>;
  3880. + };
  3881. +
  3882. + ve2 {
  3883. + id = <9>;
  3884. + mode = <0>;
  3885. + pri = <1>;
  3886. + select = <1>;
  3887. + power-domains = <&pck600 PD_VE_ENC>;
  3888. + };
  3889. +
  3890. +
  3891. + isp {
  3892. + id = <16>;
  3893. + mode = <0>;
  3894. + pri = <2>;
  3895. + select = <1>;
  3896. + power-domains = <&pck600 PD_VI>;
  3897. + };
  3898. +
  3899. + csi {
  3900. + id = <17>;
  3901. + mode = <0>;
  3902. + pri = <2>;
  3903. + select = <1>;
  3904. + power-domains = <&pck600 PD_VI>;
  3905. + };
  3906. + };
  3907. +
  3908. + uart0: serial@2500000 {
  3909. + compatible = "snps,dw-apb-uart";
  3910. + reg = <0x0 0x02500000 0x0 0x400>;
  3911. + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  3912. + reg-shift = <2>;
  3913. + reg-io-width = <4>;
  3914. + clocks = <&ccu CLK_UART0>;
  3915. + resets = <&ccu RST_BUS_UART0>;
  3916. + status = "disabled";
  3917. + };
  3918. +
  3919. + uart1: serial@2501000 {
  3920. + compatible = "snps,dw-apb-uart";
  3921. + reg = <0x0 0x02501000 0x0 0x400>;
  3922. + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  3923. + reg-shift = <2>;
  3924. + reg-io-width = <4>;
  3925. + clocks = <&ccu CLK_UART1>;
  3926. + resets = <&ccu RST_BUS_UART1>;
  3927. + status = "disabled";
  3928. + };
  3929. +
  3930. + uart2: serial@2502000 {
  3931. + compatible = "snps,dw-apb-uart";
  3932. + reg = <0x0 0x02502000 0x0 0x400>;
  3933. + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  3934. + reg-shift = <2>;
  3935. + reg-io-width = <4>;
  3936. + clocks = <&ccu CLK_UART2>;
  3937. + resets = <&ccu RST_BUS_UART2>;
  3938. + status = "disabled";
  3939. + };
  3940. +
  3941. + uart3: serial@2503000 {
  3942. + compatible = "snps,dw-apb-uart";
  3943. + reg = <0x0 0x02503000 0x0 0x400>;
  3944. + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  3945. + reg-shift = <2>;
  3946. + reg-io-width = <4>;
  3947. + clocks = <&ccu CLK_UART3>;
  3948. + resets = <&ccu RST_BUS_UART3>;
  3949. + status = "disabled";
  3950. + };
  3951. +
  3952. + uart4: serial@2504000 {
  3953. + compatible = "snps,dw-apb-uart";
  3954. + reg = <0x0 0x02504000 0x0 0x400>;
  3955. + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  3956. + reg-shift = <2>;
  3957. + reg-io-width = <4>;
  3958. + clocks = <&ccu CLK_UART4>;
  3959. + resets = <&ccu RST_BUS_UART4>;
  3960. + status = "disabled";
  3961. + };
  3962. +
  3963. + uart5: serial@2505000 {
  3964. + compatible = "snps,dw-apb-uart";
  3965. + reg = <0x0 0x02505000 0x0 0x400>;
  3966. + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  3967. + reg-shift = <2>;
  3968. + reg-io-width = <4>;
  3969. + clocks = <&ccu CLK_UART5>;
  3970. + resets = <&ccu RST_BUS_UART5>;
  3971. + status = "disabled";
  3972. + };
  3973. +
  3974. + uart6: serial@2506000 {
  3975. + compatible = "snps,dw-apb-uart";
  3976. + reg = <0x0 0x02506000 0x0 0x400>;
  3977. + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  3978. + reg-shift = <2>;
  3979. + reg-io-width = <4>;
  3980. + clocks = <&ccu CLK_UART6>;
  3981. + resets = <&ccu RST_BUS_UART6>;
  3982. + status = "disabled";
  3983. + };
  3984. +
  3985. + uart7: serial@7080000 {
  3986. + compatible = "snps,dw-apb-uart";
  3987. + reg = <0x0 0x07080000 0x0 0x400>;
  3988. + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  3989. + reg-shift = <2>;
  3990. + reg-io-width = <4>;
  3991. + clocks = <&r_ccu CLK_R_UART0>;
  3992. + resets = <&r_ccu RST_BUS_R_UART0>;
  3993. + status = "disabled";
  3994. + };
  3995. +
  3996. + uart8: serial@7081000 {
  3997. + compatible = "snps,dw-apb-uart";
  3998. + reg = <0x0 0x07081000 0x0 0x400>;
  3999. + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
  4000. + reg-shift = <2>;
  4001. + reg-io-width = <4>;
  4002. + clocks = <&r_ccu CLK_R_UART0>;
  4003. + resets = <&r_ccu RST_BUS_R_UART1>;
  4004. + status = "disabled";
  4005. + };
  4006. +
  4007. + i2c0: i2c@2510000 {
  4008. + compatible = "allwinner,sun55i-a523-i2c",
  4009. + "allwinner,sun8i-v536-i2c",
  4010. + "allwinner,sun6i-a31-i2c";
  4011. + reg = <0x0 0x02510000 0x0 0x400>;
  4012. + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  4013. + clocks = <&ccu CLK_TWI0>;
  4014. + resets = <&ccu RST_BUS_TWI0>;
  4015. + dmas = <&dma 37>, <&dma 37>;
  4016. + dma-names = "tx", "rx";
  4017. + status = "disabled";
  4018. + #address-cells = <1>;
  4019. + #size-cells = <0>;
  4020. + };
  4021. +
  4022. + i2c1: i2c@2511000 {
  4023. + compatible = "allwinner,sun55i-a523-i2c",
  4024. + "allwinner,sun8i-v536-i2c",
  4025. + "allwinner,sun6i-a31-i2c";
  4026. + reg = <0x0 0x02511000 0x0 0x400>;
  4027. + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  4028. + clocks = <&ccu CLK_TWI1>;
  4029. + resets = <&ccu RST_BUS_TWI1>;
  4030. + dmas = <&dma 38>, <&dma 38>;
  4031. + dma-names = "tx", "rx";
  4032. + status = "disabled";
  4033. + #address-cells = <1>;
  4034. + #size-cells = <0>;
  4035. + };
  4036. +
  4037. + i2c2: i2c@2512000 {
  4038. + compatible = "allwinner,sun55i-a523-i2c",
  4039. + "allwinner,sun8i-v536-i2c",
  4040. + "allwinner,sun6i-a31-i2c";
  4041. + reg = <0x0 0x02512000 0x0 0x400>;
  4042. + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  4043. + clocks = <&ccu CLK_TWI2>;
  4044. + resets = <&ccu RST_BUS_TWI2>;
  4045. + dmas = <&dma 39>, <&dma 39>;
  4046. + dma-names = "tx", "rx";
  4047. + status = "disabled";
  4048. + #address-cells = <1>;
  4049. + #size-cells = <0>;
  4050. + };
  4051. +
  4052. + i2c3: i2c@2513000 {
  4053. + compatible = "allwinner,sun55i-a523-i2c",
  4054. + "allwinner,sun8i-v536-i2c",
  4055. + "allwinner,sun6i-a31-i2c";
  4056. + reg = <0x0 0x02513000 0x0 0x400>;
  4057. + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  4058. + clocks = <&ccu CLK_TWI3>;
  4059. + resets = <&ccu RST_BUS_TWI3>;
  4060. + dmas = <&dma 40>, <&dma 40>;
  4061. + dma-names = "tx", "rx";
  4062. + status = "disabled";
  4063. + #address-cells = <1>;
  4064. + #size-cells = <0>;
  4065. + };
  4066. +
  4067. + i2c4: i2c@2514000 {
  4068. + compatible = "allwinner,sun55i-a523-i2c",
  4069. + "allwinner,sun8i-v536-i2c",
  4070. + "allwinner,sun6i-a31-i2c";
  4071. + reg = <0x0 0x02514000 0x0 0x400>;
  4072. + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  4073. + clocks = <&ccu CLK_TWI4>;
  4074. + resets = <&ccu RST_BUS_TWI4>;
  4075. + dmas = <&dma 41>, <&dma 41>;
  4076. + dma-names = "tx", "rx";
  4077. + status = "disabled";
  4078. + #address-cells = <1>;
  4079. + #size-cells = <0>;
  4080. + };
  4081. +
  4082. + i2c5: i2c@2515000 {
  4083. + compatible = "allwinner,sun55i-a523-i2c",
  4084. + "allwinner,sun8i-v536-i2c",
  4085. + "allwinner,sun6i-a31-i2c";
  4086. + reg = <0x0 0x02515000 0x0 0x400>;
  4087. + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  4088. + clocks = <&ccu CLK_TWI5>;
  4089. + resets = <&ccu RST_BUS_TWI5>;
  4090. + dmas = <&dma 42>, <&dma 42>;
  4091. + dma-names = "tx", "rx";
  4092. + status = "disabled";
  4093. + #address-cells = <1>;
  4094. + #size-cells = <0>;
  4095. + };
  4096. +
  4097. + i2c6: i2c@2516000 {
  4098. + compatible = "allwinner,sun55i-a523-i2c",
  4099. + "allwinner,sun8i-v536-i2c",
  4100. + "allwinner,sun6i-a31-i2c";
  4101. + reg = <0x0 0x02516000 0x0 0x400>;
  4102. + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  4103. + clocks = <&ccu CLK_TWI6>;
  4104. + resets = <&ccu RST_BUS_TWI6>;
  4105. + dmas = <&dma 43>, <&dma 43>;
  4106. + dma-names = "tx", "rx";
  4107. + status = "disabled";
  4108. + #address-cells = <1>;
  4109. + #size-cells = <0>;
  4110. + };
  4111. +
  4112. + i2c7: i2c@2517000 {
  4113. + compatible = "allwinner,sun55i-a523-i2c",
  4114. + "allwinner,sun8i-v536-i2c",
  4115. + "allwinner,sun6i-a31-i2c";
  4116. + reg = <0x0 0x02517000 0x0 0x400>;
  4117. + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  4118. + clocks = <&ccu CLK_TWI7>;
  4119. + resets = <&ccu RST_BUS_TWI7>;
  4120. + dmas = <&dma 44>, <&dma 44>;
  4121. + dma-names = "tx", "rx";
  4122. + status = "disabled";
  4123. + #address-cells = <1>;
  4124. + #size-cells = <0>;
  4125. + };
  4126. +
  4127. + i2c8: i2c@2518000 {
  4128. + compatible = "allwinner,sun55i-a523-i2c",
  4129. + "allwinner,sun8i-v536-i2c",
  4130. + "allwinner,sun6i-a31-i2c";
  4131. + reg = <0x0 0x02518000 0x0 0x400>;
  4132. + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  4133. + clocks = <&ccu CLK_TWI8>;
  4134. + resets = <&ccu RST_BUS_TWI8>;
  4135. + dmas = <&dma 45>, <&dma 45>;
  4136. + dma-names = "tx", "rx";
  4137. + status = "disabled";
  4138. + #address-cells = <1>;
  4139. + #size-cells = <0>;
  4140. + };
  4141. +
  4142. + i2c9: i2c@2519000 {
  4143. + compatible = "allwinner,sun55i-a523-i2c",
  4144. + "allwinner,sun8i-v536-i2c",
  4145. + "allwinner,sun6i-a31-i2c";
  4146. + reg = <0x0 0x02519000 0x0 0x400>;
  4147. + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  4148. + clocks = <&ccu CLK_TWI9>;
  4149. + resets = <&ccu RST_BUS_TWI9>;
  4150. + dmas = <&dma 58>, <&dma 58>;
  4151. + dma-names = "tx", "rx";
  4152. + status = "disabled";
  4153. + #address-cells = <1>;
  4154. + #size-cells = <0>;
  4155. + };
  4156. +
  4157. + i2c10: i2c@251a000 {
  4158. + compatible = "allwinner,sun55i-a523-i2c",
  4159. + "allwinner,sun8i-v536-i2c",
  4160. + "allwinner,sun6i-a31-i2c";
  4161. + reg = <0x0 0x0251a000 0x0 0x400>;
  4162. + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  4163. + clocks = <&ccu CLK_TWI10>;
  4164. + resets = <&ccu RST_BUS_TWI10>;
  4165. + dmas = <&dma 59>, <&dma 59>;
  4166. + dma-names = "tx", "rx";
  4167. + status = "disabled";
  4168. + #address-cells = <1>;
  4169. + #size-cells = <0>;
  4170. + };
  4171. +
  4172. + i2c11: i2c@251b000 {
  4173. + compatible = "allwinner,sun55i-a523-i2c",
  4174. + "allwinner,sun8i-v536-i2c",
  4175. + "allwinner,sun6i-a31-i2c";
  4176. + reg = <0x0 0x0251b000 0x0 0x400>;
  4177. + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  4178. + clocks = <&ccu CLK_TWI11>;
  4179. + resets = <&ccu RST_BUS_TWI11>;
  4180. + dmas = <&dma 60>, <&dma 60>;
  4181. + dma-names = "tx", "rx";
  4182. + status = "disabled";
  4183. + #address-cells = <1>;
  4184. + #size-cells = <0>;
  4185. + };
  4186. +
  4187. + i2c12: i2c@251c000 {
  4188. + compatible = "allwinner,sun55i-a523-i2c",
  4189. + "allwinner,sun8i-v536-i2c",
  4190. + "allwinner,sun6i-a31-i2c";
  4191. + reg = <0x0 0x0251c000 0x0 0x400>;
  4192. + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  4193. + clocks = <&ccu CLK_TWI12>;
  4194. + resets = <&ccu RST_BUS_TWI12>;
  4195. + dmas = <&dma 61>, <&dma 61>;
  4196. + dma-names = "tx", "rx";
  4197. + status = "disabled";
  4198. + #address-cells = <1>;
  4199. + #size-cells = <0>;
  4200. + };
  4201. +
  4202. + r_i2c0: i2c@7083000 {
  4203. + compatible = "allwinner,sun55i-a523-i2c",
  4204. + "allwinner,sun8i-v536-i2c",
  4205. + "allwinner,sun6i-a31-i2c";
  4206. + reg = <0x0 0x07083000 0x0 0x400>;
  4207. + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
  4208. + clocks = <&r_ccu CLK_R_TWI0>;
  4209. + resets = <&r_ccu RST_BUS_R_TWI0>;
  4210. + dmas = <&dma 47>, <&dma 47>;
  4211. + dma-names = "tx", "rx";
  4212. + pinctrl-names = "default";
  4213. + pinctrl-0 = <&r_i2c0_pins>;
  4214. + status = "disabled";
  4215. + #address-cells = <1>;
  4216. + #size-cells = <0>;
  4217. + };
  4218. +
  4219. + r_i2c1: i2c@7084000 {
  4220. + compatible = "allwinner,sun55i-a523-i2c",
  4221. + "allwinner,sun8i-v536-i2c",
  4222. + "allwinner,sun6i-a31-i2c";
  4223. + reg = <0x0 0x07084000 0x0 0x400>;
  4224. + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
  4225. + clocks = <&r_ccu CLK_R_TWI1>;
  4226. + resets = <&r_ccu RST_BUS_R_TWI1>;
  4227. + dmas = <&dma 48>, <&dma 48>;
  4228. + dma-names = "tx", "rx";
  4229. + status = "disabled";
  4230. + #address-cells = <1>;
  4231. + #size-cells = <0>;
  4232. + };
  4233. +
  4234. + r_i2c2: i2c@7085000 {
  4235. + compatible = "allwinner,sun55i-a523-i2c",
  4236. + "allwinner,sun8i-v536-i2c",
  4237. + "allwinner,sun6i-a31-i2c";
  4238. + reg = <0x0 0x07085000 0x0 0x400>;
  4239. + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  4240. + clocks = <&r_ccu CLK_R_TWI2>;
  4241. + resets = <&r_ccu RST_BUS_R_TWI2>;
  4242. + dmas = <&dma 49>, <&dma 49>;
  4243. + dma-names = "tx", "rx";
  4244. + status = "disabled";
  4245. + #address-cells = <1>;
  4246. + #size-cells = <0>;
  4247. + };
  4248. +
  4249. + pwm0: pwm@2527000 {
  4250. + #pwm-cells = <3>;
  4251. + compatible = "allwinner,sunxi-pwm-v203";
  4252. + reg = <0x0 0x02527000 0x0 0x400>;
  4253. + clocks = <&ccu CLK_PWM0>;
  4254. + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  4255. + resets = <&ccu RST_BUS_PWM0>;
  4256. + pwm-number = <10>;
  4257. + sunxi-pwms = <&pwm0_0>, <&pwm0_1>, <&pwm0_2>, <&pwm0_3>, <&pwm0_4>,
  4258. + <&pwm0_5>, <&pwm0_6>, <&pwm0_7>, <&pwm0_8>, <&pwm0_9>;
  4259. + status = "okay";
  4260. + };
  4261. +
  4262. + pwm0_0: pwm0@2527010 {
  4263. + compatible = "allwinner,sunxi-pwm0";
  4264. + pinctrl-names = "active", "sleep";
  4265. + reg = <0x0 0x02527010 0x0 0x4>;
  4266. + reg_base = <0x02527000>;
  4267. + status = "disabled";
  4268. + };
  4269. +
  4270. + pwm0_1: pwm0@2527011 {
  4271. + compatible = "allwinner,sunxi-pwm1";
  4272. + pinctrl-names = "active", "sleep";
  4273. + reg = <0x0 0x02527011 0x0 0x4>;
  4274. + reg_base = <0x02527000>;
  4275. + status = "disabled";
  4276. + };
  4277. +
  4278. + pwm0_2: pwm0@2527012 {
  4279. + compatible = "allwinner,sunxi-pwm2";
  4280. + pinctrl-names = "active", "sleep";
  4281. + reg = <0x0 0x02527012 0x0 0x4>;
  4282. + reg_base = <0x02527000>;
  4283. + status = "disabled";
  4284. + };
  4285. +
  4286. + pwm0_3: pwm0@2527013 {
  4287. + compatible = "allwinner,sunxi-pwm3";
  4288. + pinctrl-names = "active", "sleep";
  4289. + reg = <0x0 0x02527013 0x0 0x4>;
  4290. + reg_base = <0x02527000>;
  4291. + status = "disabled";
  4292. + };
  4293. +
  4294. + pwm0_4: pwm0@2527014 {
  4295. + compatible = "allwinner,sunxi-pwm4";
  4296. + pinctrl-names = "active", "sleep";
  4297. + reg = <0x0 0x02527014 0x0 0x4>;
  4298. + reg_base = <0x02527000>;
  4299. + status = "disabled";
  4300. + };
  4301. +
  4302. + pwm0_5: pwm0@2527015 {
  4303. + compatible = "allwinner,sunxi-pwm5";
  4304. + pinctrl-names = "active", "sleep";
  4305. + reg = <0x0 0x02527015 0x0 0x4>;
  4306. + reg_base = <0x02527000>;
  4307. + status = "disabled";
  4308. + };
  4309. +
  4310. + pwm0_6: pwm0@2527016 {
  4311. + compatible = "allwinner,sunxi-pwm6";
  4312. + pinctrl-names = "active", "sleep";
  4313. + reg = <0x0 0x02527016 0x0 0x4>;
  4314. + reg_base = <0x02527000>;
  4315. + status = "disabled";
  4316. + };
  4317. +
  4318. + pwm0_7: pwm0@2527017 {
  4319. + compatible = "allwinner,sunxi-pwm7";
  4320. + pinctrl-names = "active", "sleep";
  4321. + reg = <0x0 0x02527017 0x0 0x4>;
  4322. + reg_base = <0x02527000>;
  4323. + status = "disabled";
  4324. + };
  4325. +
  4326. + pwm0_8: pwm0@2527018 {
  4327. + compatible = "allwinner,sunxi-pwm8";
  4328. + pinctrl-names = "active", "sleep";
  4329. + reg = <0x0 0x02527018 0x0 0x4>;
  4330. + reg_base = <0x02527000>;
  4331. + status = "disabled";
  4332. + };
  4333. +
  4334. + pwm0_9: pwm0@2527019 {
  4335. + compatible = "allwinner,sunxi-pwm9";
  4336. + pinctrl-names = "active", "sleep";
  4337. + reg = <0x0 0x02527019 0x0 0x4>;
  4338. + reg_base = <0x02527000>;
  4339. + status = "disabled";
  4340. + };
  4341. +
  4342. + pwm1: pwm@2528000 {
  4343. + #pwm-cells = <3>;
  4344. + compatible = "allwinner,sunxi-pwm-v203";
  4345. + reg = <0x0 0x02528000 0x0 0x400>;
  4346. + clocks = <&ccu CLK_PWM1>;
  4347. + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  4348. + resets = <&ccu RST_BUS_PWM1>;
  4349. + pwm-number = <10>;
  4350. + sunxi-pwms = <&pwm1_0>, <&pwm1_1>, <&pwm1_2>, <&pwm1_3>,
  4351. + <&pwm1_4>, <&pwm1_5>, <&pwm1_6>, <&pwm1_7>, <&pwm1_8>, <&pwm1_9>;
  4352. + status = "okay";
  4353. + };
  4354. +
  4355. + pwm1_0: pwm1@2528010 {
  4356. + compatible = "allwinner,sunxi-pwm10";
  4357. + pinctrl-names = "active", "sleep";
  4358. + reg = <0x0 0x02528010 0x0 0x4>;
  4359. + reg_base = <0x02528000>;
  4360. + status = "disabled";
  4361. + };
  4362. +
  4363. + pwm1_1: pwm1@2528011 {
  4364. + compatible = "allwinner,sunxi-pwm11";
  4365. + pinctrl-names = "active", "sleep";
  4366. + reg = <0x0 0x02528011 0x0 0x4>;
  4367. + reg_base = <0x02528000>;
  4368. + status = "disabled";
  4369. + };
  4370. +
  4371. + pwm1_2: pwm1@2528012 {
  4372. + compatible = "allwinner,sunxi-pwm12";
  4373. + pinctrl-names = "active", "sleep";
  4374. + reg = <0x0 0x02528012 0x0 0x4>;
  4375. + reg_base = <0x02528000>;
  4376. + status = "disabled";
  4377. + };
  4378. +
  4379. + pwm1_3: pwm1@2528013 {
  4380. + compatible = "allwinner,sunxi-pwm13";
  4381. + pinctrl-names = "active", "sleep";
  4382. + reg = <0x0 0x02528013 0x0 0x4>;
  4383. + reg_base = <0x02528000>;
  4384. + status = "disabled";
  4385. + };
  4386. +
  4387. + pwm1_4: pwm1@2528014 {
  4388. + compatible = "allwinner,sunxi-pwm14";
  4389. + pinctrl-names = "active", "sleep";
  4390. + reg = <0x0 0x02528014 0x0 0x4>;
  4391. + reg_base = <0x02528000>;
  4392. + status = "disabled";
  4393. + };
  4394. +
  4395. + pwm1_5: pwm1@2528015 {
  4396. + compatible = "allwinner,sunxi-pwm15";
  4397. + pinctrl-names = "active", "sleep";
  4398. + reg = <0x0 0x02528015 0x0 0x4>;
  4399. + reg_base = <0x02528000>;
  4400. + status = "disabled";
  4401. + };
  4402. +
  4403. + pwm1_6: pwm1@2528016 {
  4404. + compatible = "allwinner,sunxi-pwm16";
  4405. + pinctrl-names = "active", "sleep";
  4406. + reg = <0x0 0x02528016 0x0 0x4>;
  4407. + reg_base = <0x02528000>;
  4408. + status = "disabled";
  4409. + };
  4410. +
  4411. + pwm1_7: pwm1@2528017 {
  4412. + compatible = "allwinner,sunxi-pwm17";
  4413. + pinctrl-names = "active", "sleep";
  4414. + reg = <0x0 0x02528017 0x0 0x4>;
  4415. + reg_base = <0x02528000>;
  4416. + status = "disabled";
  4417. + };
  4418. +
  4419. + pwm1_8: pwm1@2528018 {
  4420. + compatible = "allwinner,sunxi-pwm18";
  4421. + pinctrl-names = "active", "sleep";
  4422. + reg = <0x0 0x02528018 0x0 0x4>;
  4423. + reg_base = <0x02528000>;
  4424. + status = "disabled";
  4425. + };
  4426. +
  4427. + pwm1_9: pwm1@2528019 {
  4428. + compatible = "allwinner,sunxi-pwm19";
  4429. + pinctrl-names = "active", "sleep";
  4430. + reg = <0x0 0x02528019 0x0 0x4>;
  4431. + reg_base = <0x02528000>;
  4432. + status = "disabled";
  4433. + };
  4434. +
  4435. + s_pwm0: pwm@7023000 {
  4436. + #pwm-cells = <3>;
  4437. + compatible = "allwinner,sunxi-pwm-v204";
  4438. + reg = <0x0 0x07023000 0x0 0x400>;
  4439. + clocks = <&r_ccu CLK_R_PWM>,<&r_ccu CLK_R_BUS_PWM>;
  4440. + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
  4441. + clock-names = "clk_pwm","clk_bus_pwm";
  4442. + resets = <&r_ccu RST_BUS_R_PWM>;
  4443. + pwm-number = <10>;
  4444. + sunxi-pwms = <&s_pwm0_0>, <&s_pwm0_1>, <&s_pwm0_2>, <&s_pwm0_3>,
  4445. + <&s_pwm0_4>, <&s_pwm0_5>, <&s_pwm0_6>, <&s_pwm0_7>, <&s_pwm0_8>, <&s_pwm0_9>;
  4446. + status = "okay";
  4447. + };
  4448. +
  4449. + s_pwm0_0: s_pwm0@7023010 {
  4450. + compatible = "allwinner,sunxi-pwm20";
  4451. + pinctrl-names = "active", "sleep";
  4452. + reg = <0x0 0x07023010 0x0 0x4>;
  4453. + reg_base = <0x07023000>;
  4454. + status = "disabled";
  4455. + };
  4456. +
  4457. + s_pwm0_1: s_pwm0@7023011 {
  4458. + compatible = "allwinner,sunxi-pwm21";
  4459. + pinctrl-names = "active", "sleep";
  4460. + reg = <0x0 0x07023011 0x0 0x4>;
  4461. + reg_base = <0x07023000>;
  4462. + status = "disabled";
  4463. + };
  4464. +
  4465. + s_pwm0_2: s_pwm0@7023012 {
  4466. + compatible = "allwinner,sunxi-pwm22";
  4467. + pinctrl-names = "active", "sleep";
  4468. + reg = <0x0 0x07023012 0x0 0x4>;
  4469. + reg_base = <0x07023000>;
  4470. + status = "disabled";
  4471. + };
  4472. +
  4473. + s_pwm0_3: s_pwm0@7023013 {
  4474. + compatible = "allwinner,sunxi-pwm23";
  4475. + pinctrl-names = "active", "sleep";
  4476. + reg = <0x0 0x07023013 0x0 0x4>;
  4477. + reg_base = <0x07023000>;
  4478. + status = "disabled";
  4479. + };
  4480. +
  4481. + s_pwm0_4: s_pwm0@7023014 {
  4482. + compatible = "allwinner,sunxi-pwm24";
  4483. + pinctrl-names = "active", "sleep";
  4484. + reg = <0x0 0x07023014 0x0 0x4>;
  4485. + reg_base = <0x07023000>;
  4486. + status = "disabled";
  4487. + };
  4488. +
  4489. + s_pwm0_5: s_pwm0@7023015 {
  4490. + compatible = "allwinner,sunxi-pwm25";
  4491. + pinctrl-names = "active", "sleep";
  4492. + reg = <0x0 0x07023015 0x0 0x4>;
  4493. + reg_base = <0x07023000>;
  4494. + status = "disabled";
  4495. + };
  4496. +
  4497. + s_pwm0_6: s_pwm0@7023016 {
  4498. + compatible = "allwinner,sunxi-pwm26";
  4499. + pinctrl-names = "active", "sleep";
  4500. + reg = <0x0 0x07023016 0x0 0x4>;
  4501. + reg_base = <0x07023000>;
  4502. + status = "disabled";
  4503. + };
  4504. +
  4505. + s_pwm0_7: s_pwm0@7023017 {
  4506. + compatible = "allwinner,sunxi-pwm27";
  4507. + pinctrl-names = "active", "sleep";
  4508. + reg = <0x0 0x07023017 0x0 0x4>;
  4509. + reg_base = <0x07023000>;
  4510. + status = "disabled";
  4511. + };
  4512. +
  4513. + s_pwm0_8: s_pwm0@7023018 {
  4514. + compatible = "allwinner,sunxi-pwm28";
  4515. + pinctrl-names = "active", "sleep";
  4516. + reg = <0x0 0x07023018 0x0 0x4>;
  4517. + reg_base = <0x07023000>;
  4518. + status = "disabled";
  4519. + };
  4520. +
  4521. + s_pwm0_9: s_pwm0@7023019 {
  4522. + compatible = "allwinner,sunxi-pwm29";
  4523. + pinctrl-names = "active", "sleep";
  4524. + reg = <0x0 0x07023019 0x0 0x4>;
  4525. + reg_base = <0x07023000>;
  4526. + status = "disabled";
  4527. + };
  4528. +
  4529. + lradc: lradc@2524000 {
  4530. + compatible = "allwinner,keyboard_1350mv";
  4531. + reg = <0x0 0x02524000 0x0 0x100>;
  4532. + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  4533. + clocks = <&ccu CLK_LRADC>;
  4534. + resets = <&ccu RST_BUS_LRADC>;
  4535. + status = "disabled";
  4536. + };
  4537. +
  4538. + gpadc0: gpadc@2521000 {
  4539. + compatible = "allwinner,sunxi-gpadc-v101";
  4540. + reg = <0x0 0x02521000 0x0 0x400>;
  4541. + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  4542. + clocks = <&ccu CLK_GPADC0>, <&ccu CLK_GPADC0_24M>;
  4543. + clock-names = "bus", "hosc";
  4544. + resets = <&ccu RST_BUS_GPADC0>;
  4545. + status = "disabled";
  4546. + };
  4547. +
  4548. + irrx: irrx@2526000 {
  4549. + compatible = "allwinner,irrx";
  4550. + reg = <0x0 0x02526000 0x0 0x400>;
  4551. + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  4552. + clocks = <&ccu CLK_IRRX_GATE>, <&sys24M>, <&ccu CLK_IRRX>;
  4553. + clock-names = "bus", "pclk", "mclk";
  4554. + resets = <&ccu RST_BUS_IRRX>;
  4555. + status = "disabled";
  4556. + };
  4557. +
  4558. + s_irrx: irrx@7040000 {
  4559. + compatible = "allwinner,irrx";
  4560. + reg = <0x0 0x07040000 0x0 0x400>;
  4561. + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  4562. + clocks = <&r_ccu CLK_R_BUS_IRRX>, <&ccu CLK_PLL_REF>, <&r_ccu CLK_R_IRRX>;
  4563. + clock-names = "bus", "pclk", "mclk";
  4564. + resets = <&r_ccu RST_BUS_R_IRRX>;
  4565. + status = "disabled";
  4566. + };
  4567. +
  4568. + irtx: irtx@2525000 {
  4569. + compatible = "allwinner,irtx";
  4570. + reg = <0x0 0x02525000 0x0 0x400>;
  4571. + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  4572. + clocks = <&ccu CLK_IRTX_GATE>, <&sys24M>, <&ccu CLK_IRTX>;
  4573. + clock-names = "bus", "pclk", "mclk";
  4574. + resets = <&ccu RST_BUS_IRTX>;
  4575. + status = "disabled";
  4576. + };
  4577. +
  4578. + ledc: ledc@2520000 {
  4579. + #address-cells = <1>;
  4580. + #size-cells = <0>;
  4581. + compatible = "allwinner,sunxi-leds";
  4582. + reg = <0x0 0x02520000 0x0 0x400>;
  4583. + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  4584. + clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>;
  4585. + clock-names = "clk_ledc", "clk_cpuapb";
  4586. + resets = <&ccu RST_BUS_LEDC>;
  4587. + reset-names = "ledc_reset";
  4588. + dmas = <&dma 46>;
  4589. + dma-names = "tx";
  4590. + status = "disabled";
  4591. + };
  4592. +
  4593. + npu: npu@3600000 {
  4594. + compatible = "vivante,gc";
  4595. + reg = <0x0 0x03600000 0x0 0x1000>;
  4596. + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  4597. + clocks = <&ccu CLK_BUS_NPU>,
  4598. + <&ccu CLK_NPU>,
  4599. + <&ccu CLK_MBUS_NPU_GATE>,
  4600. + <&ccu CLK_NPU_AHB_GATE>;
  4601. + clock-names = "bus", "core", "mbus", "reg";
  4602. + resets = <&ccu RST_BUS_NPU_CORE>,
  4603. + <&ccu RST_BUS_NPU_AXI>,
  4604. + <&ccu RST_BUS_NPU_AHB>;
  4605. + reset-names = "core", "axi", "ahb";
  4606. + power-domains = <&pck600 PD_NPU>;
  4607. + status = "disabled";
  4608. + };
  4609. +
  4610. + // npu: npu@3600000 {
  4611. + // compatible = "allwinner,npu";
  4612. + // reg = <0x0 0x03600000 0x0 0x1000>;
  4613. + // device_type = "npu";
  4614. + // dev_name = "npu";
  4615. + // interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  4616. + // interrupt-names = "npu";
  4617. + // clocks = <&ccu CLK_NPU>, <&ccu CLK_PLL_NPU>, <&ccu CLK_BUS_NPU>, <&ccu CLK_MBUS_NPU_GATE>, <&ccu CLK_NPU_AHB_GATE>;
  4618. + // clock-names = "clk_npu", "clk_parent", "clk_bus", "clk_mbus_gate", "clk_ahb_gate";
  4619. + // operating-points-v2 = <&npu_opp_table>;
  4620. + // resets = <&ccu RST_BUS_NPU_CORE>, <&ccu RST_BUS_NPU_AXI>, <&ccu RST_BUS_NPU_AHB>;
  4621. + // reset-names = "npu_rst", "npu_axi_rst", "npu_ahb_rst";
  4622. + // power-domains = <&pck600 PD_NPU>;
  4623. + // npu-vf = <1008>;
  4624. + // status = "disabled";
  4625. + // };
  4626. +
  4627. + hwspinlock: hwspinlock@3005000 {
  4628. + compatible = "allwinner,sunxi-hwspinlock";
  4629. + reg = <0x0 0x3005000 0x0 0x1000>;
  4630. + #hwlock-cells = <1>;
  4631. + clocks = <&ccu CLK_SPINLOCK>;
  4632. + clock-names = "clk_hwspinlock_bus";
  4633. + resets = <&ccu RST_BUS_SPINLOCK>;
  4634. + reset-names = "rst";
  4635. + num-locks = <32>;
  4636. + status = "disabled";
  4637. + };
  4638. +
  4639. + /*
  4640. + * channel0~3 : arm -> cpus
  4641. + */
  4642. + msgbox: msgbox@3004000 {
  4643. + compatible = "allwinner,sun60iw2-msgbox";
  4644. + #mbox-cells = <1>;
  4645. + reg = <0x0 0x03004000 0x0 0x1000>,
  4646. + <0x0 0x07094000 0x0 0x1000>;
  4647. + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  4648. + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
  4649. + clocks = <&ccu CLK_MSGBOX0>;
  4650. + clock-names = "msgbox";
  4651. + resets = <&ccu RST_BUS_MSGBOX0>;
  4652. + reset-names = "rst";
  4653. + local_id = <0>;
  4654. + status = "disabled";
  4655. + };
  4656. +
  4657. + a55_rproc: a55_rproc@0 {
  4658. + compatible = "allwinner,arm64-rproc";
  4659. + status = "disabled";
  4660. + };
  4661. +
  4662. + cryptoengine: ce@4603000 {
  4663. + compatible = "allwinner,sunxi-ce";
  4664. + device_name = "ce";
  4665. + reg = <0x0 0x04603000 0x0 0xa0>, /* non-secure space */
  4666. + <0x0 0x04603800 0x0 0xa0>; /* secure space */
  4667. + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>, /*non-secure*/
  4668. + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; /* secure*/
  4669. + clock-frequency = <400000000>; /* 400MHz */
  4670. + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>,
  4671. + <&ccu CLK_PLL_PERI0_400M>, <&ccu CLK_CE_SYS>;
  4672. + clock-names = "bus_ce", "ce_clk", "mbus_ce", "clk_src", "ce_sys_clk";
  4673. + resets = <&ccu RST_BUS_CE>;
  4674. + status = "disabled";
  4675. + };
  4676. +
  4677. + usbc0: usbc0@10 {
  4678. + device_type = "usbc0";
  4679. + compatible = "allwinner,sunxi-otg-manager";
  4680. + reg = <0x0 0x10 0x0 0x1000>;
  4681. + usb_port_type = <2>;
  4682. + usb_detect_type = <1>;
  4683. + usb_detect_mode = <0>;
  4684. + usb_id_gpio;
  4685. + usb_det_vbus_gpio;
  4686. + usb_regulator_io = "nocare";
  4687. + usb_wakeup_suspend = <0>;
  4688. + usb_luns = <3>;
  4689. + usb_serial_unique = <0>;
  4690. + usb_serial_number = "20080411";
  4691. + rndis_wceis = <1>;
  4692. + status = "disabled";
  4693. + };
  4694. +
  4695. + udc:udc-controller@4100000 {
  4696. + compatible = "allwinner,sunxi-udc";
  4697. + reg = <0x0 0x04100000 0x0 0x1000>, /* udc base */
  4698. + <0x0 0x00000000 0x0 0x100>; /* sram base */
  4699. + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  4700. + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_DEVICE>, <&ccu CLK_RES_DCAP_24M>,
  4701. + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>;
  4702. + clock-names = "hosc", "bus_otg", "res_dcap", "usb_sys_ahb", "msi_lite";
  4703. + resets = <&ccu RST_USB_0_DEVICE>, <&ccu RST_USB_0_PHY_RSTN>;
  4704. + reset-names = "otg", "phy";
  4705. + aw,dma_addr_extend;
  4706. + aw,dma_wordaddr_bypass = <0x1>;
  4707. + status = "disabled";
  4708. + };
  4709. +
  4710. + ehci0:ehci0-controller@4101000 {
  4711. + compatible = "allwinner,sunxi-ehci0";
  4712. + reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/
  4713. + <0x0 0x00000000 0x0 0x100>, /*sram base*/
  4714. + <0x0 0x04100000 0x0 0x1000>; /*otg base*/
  4715. + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  4716. + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_EHCI>, <&ccu CLK_RES_DCAP_24M>,
  4717. + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>;
  4718. + clock-names = "hosc", "bus_hci", "res_dcap", "usb_sys_ahb", "msi_lite";
  4719. + resets = <&ccu RST_USB_0_EHCI>, <&ccu RST_USB_0_PHY_RSTN>;
  4720. + reset-names = "hci", "phy";
  4721. + hci_ctrl_no = <0>;
  4722. + status = "disabled";
  4723. + };
  4724. +
  4725. + ohci0:ohci0-controller@4101400 {
  4726. + compatible = "allwinner,sunxi-ohci0";
  4727. + reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/
  4728. + <0x0 0x00000000 0x0 0x100>, /*sram base*/
  4729. + <0x0 0x04100000 0x0 0x1000>; /*otg base*/
  4730. + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  4731. + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_OHCI>, <&ccu CLK_USB>, <&ccu CLK_RES_DCAP_24M>,
  4732. + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>;
  4733. + clock-names = "hosc", "bus_hci", "ohci", "res_dcap", "usb_sys_ahb", "msi_lite";
  4734. + resets = <&ccu RST_USB_0_OHCI>, <&ccu RST_USB_0_PHY_RSTN>;
  4735. + reset-names = "hci", "phy";
  4736. + hci_ctrl_no = <0>;
  4737. + status = "disabled";
  4738. + };
  4739. +
  4740. + usbc1: usbc1@11 {
  4741. + device_type = "usbc1";
  4742. + reg = <0x0 0x11 0x0 0x1000>;
  4743. + usb_regulator_io = "nocare";
  4744. + usb_wakeup_suspend = <0>;
  4745. + status = "disabled";
  4746. + };
  4747. +
  4748. + ehci1: ehci1-controller@4200000 {
  4749. + compatible = "allwinner,sunxi-ehci1";
  4750. + reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/
  4751. + <0x0 0x00000000 0x0 0x100>, /*sram base*/
  4752. + <0x0 0x04100000 0x0 0x1000>; /*otg base*/
  4753. + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  4754. + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB1_EHCI>, <&ccu CLK_RES_DCAP_24M>,
  4755. + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>;
  4756. + clock-names = "hosc", "bus_hci", "res_dcap", "usb_sys_ahb", "msi_lite";
  4757. + resets = <&ccu RST_USB_1_EHCI>, <&ccu RST_USB_1_PHY_RSTN>;
  4758. + reset-names = "hci", "phy";
  4759. + hci_ctrl_no = <1>;
  4760. + status = "disabled";
  4761. + };
  4762. +
  4763. + ohci1: ohci1-controller@4200400 {
  4764. + compatible = "allwinner,sunxi-ohci1";
  4765. + reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/
  4766. + <0x0 0x00000000 0x0 0x100>, /*sram base*/
  4767. + <0x0 0x04100000 0x0 0x1000>; /*otg base*/
  4768. + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
  4769. + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB1_OHCI>, <&ccu CLK_USB1>, <&ccu CLK_RES_DCAP_24M>,
  4770. + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>;
  4771. + clock-names = "hosc", "bus_hci", "ohci", "res_dcap", "usb_sys_ahb", "msi_lite";
  4772. + resets = <&ccu RST_USB_1_OHCI>, <&ccu RST_USB_1_PHY_RSTN>;
  4773. + reset-names = "hci", "phy";
  4774. + hci_ctrl_no = <1>;
  4775. + status = "disabled";
  4776. + };
  4777. +
  4778. + usbc2:usbc2@12 {
  4779. + device_type = "usbc2";
  4780. + compatible = "allwinner,sunxi-plat-dwc3";
  4781. + reg = <0x0 0x12 0x0 0x1000>;
  4782. + #address-cells = <2>;
  4783. + #size-cells = <2>;
  4784. + ranges;
  4785. + aw,inv-sync-hdr-quirk;
  4786. + status = "disabled";
  4787. +
  4788. + dwc3: usb@6a00000 {
  4789. + compatible = "snps,dwc3";
  4790. + reg = <0x0 0x06a00000 0x0 0x100000>;
  4791. +
  4792. + clocks = <&ccu CLK_USB2_MF>, <&ccu CLK_USB2_U2_REF>, <&ccu CLK_USB2_SUSPEND>;
  4793. + clock-names = "bus_clk", "ref_clk", "suspend";
  4794. +
  4795. + assigned-clocks = <&ccu CLK_USB2_SUSPEND>;
  4796. + assigned-clock-rates = <24000000>;
  4797. +
  4798. + resets = <&ccu RST_USB_2>;
  4799. + reset-names = "hci";
  4800. +
  4801. + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  4802. +
  4803. + phys = <&u2phy>, <&combo0_usb>;
  4804. + phy-names = "usb2-phy", "usb3-phy";
  4805. + phy_type = "utmi";
  4806. +
  4807. + dr_mode = "otg"; // dr_mode option: host, peripheral, otg
  4808. + power-domains = <&pck600 PD_USB2>;
  4809. + maximum-speed = "super-speed-plus";
  4810. + snps,dis_enblslpm_quirk;
  4811. + snps,dis-u1-entry-quirk;
  4812. + snps,dis-u2-entry-quirk;
  4813. + snps,dis_u3_susphy_quirk;
  4814. + snps,dis_u2_susphy_quirk;
  4815. + status = "disabled";
  4816. + };
  4817. + };
  4818. +
  4819. + u2phy: phy@6b00000 {
  4820. + compatible = "allwinner,sunxi-plat-phy";
  4821. + reg = <0x0 0x06b00000 0x0 0x800>, /* Application Registers */
  4822. + <0x0 0x03000000 0x0 0x300>; /* SYSCFG Registers */
  4823. + reg-names = "u2_base", "res_base";
  4824. + clocks = <&ccu CLK_RES_DCAP_24M>;
  4825. + clock-names = "res_dcap";
  4826. + aw,rext_mode = <2>;
  4827. + aw,phy_tune_param = <0x143338D6>;
  4828. + #phy-cells = <0>;
  4829. + status = "disabled";
  4830. + };
  4831. +
  4832. + vind0: vind@5800800 {
  4833. + compatible = "allwinner,sunxi-vin-media", "simple-bus";
  4834. + #address-cells = <2>;
  4835. + #size-cells = <2>;
  4836. + ranges;
  4837. + device_id = <0>;
  4838. + csi_top = <600000000>;
  4839. + csi_isp = <540000000>;
  4840. + reg = <0x0 0x05800800 0x0 0x200>,
  4841. + <0x0 0x05800000 0x0 0x800>,
  4842. + <0x0 0x05810000 0x0 0x100>;
  4843. + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
  4844. + clocks = <&ccu CLK_CSI>, <&ccu CLK_PLL_VIDEO0_4X>,
  4845. + <&ccu CLK_CSI_MASTER0>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>,
  4846. + <&ccu CLK_CSI_MASTER1>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>,
  4847. + <&ccu CLK_CSI_MASTER2>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>,
  4848. + <&ccu CLK_ISP>, <&ccu CLK_PLL_VIDEO0_4X>,
  4849. + <&ccu CLK_BUS_CSI>, <&ccu CLK_CSI_MBUS>, <&ccu CLK_ISP_MBUS>;
  4850. + clock-names = "csi_top", "csi_top_src",
  4851. + "csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll",
  4852. + "csi_mclk1", "csi_mclk1_24m", "csi_mclk1_pll",
  4853. + "csi_mclk2", "csi_mclk2_24m", "csi_mclk2_pll",
  4854. + "csi_isp", "csi_isp_src",
  4855. + "csi_bus", "csi_mbus", "csi_isp_mbus";
  4856. + resets = <&ccu RST_BUS_CSI>, <>;
  4857. + reset-names = "csi_ret", "isp_ret";
  4858. + pinctrl-names = "mclk0-default", "mclk0-sleep", "mclk1-default", "mclk1-sleep",
  4859. + "mclk2-default", "mclk2-sleep";
  4860. + pinctrl-0 = <&csi_mclk0_pins_a>;
  4861. + pinctrl-1 = <&csi_mclk0_pins_b>;
  4862. + pinctrl-2 = <&csi_mclk1_pins_a>;
  4863. + pinctrl-3 = <&csi_mclk1_pins_b>;
  4864. + pinctrl-4 = <&csi_mclk2_pins_a>;
  4865. + pinctrl-5 = <&csi_mclk2_pins_b>;
  4866. + power-domains = <&pck600 PD_VI>;
  4867. + status = "disabled";
  4868. +
  4869. + csi0: csi@5820000 {
  4870. + compatible = "allwinner,sunxi-csi";
  4871. + reg = <0x0 0x05820000 0x0 0x1000>;
  4872. + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  4873. + device_id = <0>;
  4874. + pinctrl-names = "default","sleep";
  4875. + pinctrl-0 = <&ncsi0_8bit_pins_a>;
  4876. + pinctrl-1 = <&ncsi0_8bit_pins_b>;
  4877. + status = "disabled";
  4878. + };
  4879. + csi1: csi@5821000 {
  4880. + compatible = "allwinner,sunxi-csi";
  4881. + reg = <0x0 0x05821000 0x0 0x1000>;
  4882. + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
  4883. + pinctrl-names = "default","sleep";
  4884. + pinctrl-0 = <&ncsi1_8bit_pins_a>;
  4885. + pinctrl-1 = <&ncsi1_8bit_pins_b>;
  4886. + device_id = <1>;
  4887. + status = "disabled";
  4888. + };
  4889. + csi2: csi@5822000 {
  4890. + compatible = "allwinner,sunxi-csi";
  4891. + reg = <0x0 0x05822000 0x0 0x1000>;
  4892. + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  4893. + pinctrl-names = "default","sleep";
  4894. + device_id = <2>;
  4895. + status = "disabled";
  4896. + };
  4897. + mipi0: mipi@5810100 {
  4898. + compatible = "allwinner,sunxi-mipi";
  4899. + reg = <0x0 0x05810100 0x0 0x100>,
  4900. + <0x0 0x05811000 0x0 0x400>;
  4901. + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  4902. + pinctrl-names = "mipi0-default","mipi0-sleep";
  4903. + pinctrl-0 = <&mipia_pins_a>;
  4904. + pinctrl-1 = <&mipia_pins_b>;
  4905. + device_id = <0>;
  4906. + status = "disabled";
  4907. + };
  4908. + mipi1: mipi@5810200 {
  4909. + compatible = "allwinner,sunxi-mipi";
  4910. + reg = <0x0 0x05810200 0x0 0x100>,
  4911. + <0x0 0x05811400 0x0 0x400>;
  4912. + pinctrl-names = "mipi1-default","mipi1-sleep";
  4913. + pinctrl-0 = <&mipib_pins_a>;
  4914. + pinctrl-1 = <&mipib_pins_b>;
  4915. + device_id = <1>;
  4916. + status = "disabled";
  4917. + };
  4918. + mipi2: mipi@5810300 {
  4919. + compatible = "allwinner,sunxi-mipi";
  4920. + reg = <0x0 0x05810300 0x0 0x100>,
  4921. + <0x0 0x05811800 0x0 0x400>;
  4922. + pinctrl-names = "mipi2-default","mipi2-sleep";
  4923. + pinctrl-0 = <&mipic_pins_a>;
  4924. + pinctrl-1 = <&mipic_pins_b>;
  4925. + device_id = <2>;
  4926. + status = "disabled";
  4927. + };
  4928. + tdm0: tdm@5908000 {
  4929. + compatible = "allwinner,sunxi-tdm";
  4930. + reg = <0x0 0x05908000 0x0 0x400>;
  4931. + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
  4932. + work_mode = <0x0>;
  4933. + device_id = <0>;
  4934. + iommus = <&mmu_aw 2 0>;
  4935. + status = "disabled";
  4936. + };
  4937. + isp00:isp@5900000 {
  4938. + compatible = "allwinner,sunxi-isp";
  4939. + reg = <0x0 0x05900000 0x0 0x1300>;
  4940. + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
  4941. + work_mode = <0x0>;
  4942. + device_id = <0>;
  4943. + iommus = <&mmu_aw 2 0>;
  4944. + status = "disabled";
  4945. + };
  4946. + isp01:isp@58ffffc {
  4947. + compatible = "allwinner,sunxi-isp";
  4948. + reg = <0x0 0x058ffffc 0x0 0x1304>;
  4949. + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  4950. + work_mode = <0xff>;
  4951. + device_id = <1>;
  4952. + iommus = <&mmu_aw 2 0>;
  4953. + status = "disabled";
  4954. + };
  4955. + isp02:isp@58ffff8 {
  4956. + compatible = "allwinner,sunxi-isp";
  4957. + reg = <0x0 0x058ffff8 0x0 0x1308>;
  4958. + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
  4959. + work_mode = <0xff>;
  4960. + device_id = <2>;
  4961. + iommus = <&mmu_aw 2 0>;
  4962. + status = "disabled";
  4963. + };
  4964. + isp03:isp@58ffff4 {
  4965. + compatible = "allwinner,sunxi-isp";
  4966. + reg = <0x0 0x058ffff4 0x0 0x130c>;
  4967. + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  4968. + work_mode = <0xff>;
  4969. + device_id = <3>;
  4970. + iommus = <&mmu_aw 2 0>;
  4971. + status = "disabled";
  4972. + };
  4973. + isp10:isp@4 {
  4974. + compatible = "allwinner,sunxi-isp";
  4975. + device_id = <4>;
  4976. + iommus = <&mmu_aw 2 0>;
  4977. + status = "disabled";
  4978. + };
  4979. + isp20:isp@5 {
  4980. + compatible = "allwinner,sunxi-isp";
  4981. + device_id = <5>;
  4982. + iommus = <&mmu_aw 2 0>;
  4983. + status = "disabled";
  4984. + };
  4985. + isp30:isp@6 {
  4986. + compatible = "allwinner,sunxi-isp";
  4987. + device_id = <6>;
  4988. + iommus = <&mmu_aw 2 0>;
  4989. + status = "disabled";
  4990. + };
  4991. + scaler00:scaler@5910000 {
  4992. + compatible = "allwinner,sunxi-scaler";
  4993. + reg = <0x0 0x05910000 0x0 0x400>;
  4994. + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
  4995. + work_mode = <0x0>;
  4996. + device_id = <0>;
  4997. + iommus = <&mmu_aw 1 0>;
  4998. + status = "disabled";
  4999. + };
  5000. + scaler01:scaler@590fffc {
  5001. + compatible = "allwinner,sunxi-scaler";
  5002. + reg = <0x0 0x0590fffc 0x0 0x404>;
  5003. + work_mode = <0xff>;
  5004. + device_id = <1>;
  5005. + iommus = <&mmu_aw 1 0>;
  5006. + status = "disabled";
  5007. + };
  5008. + scaler02:scaler@590fff8 {
  5009. + compatible = "allwinner,sunxi-scaler";
  5010. + reg = <0x0 0x0590fff8 0x0 0x408>;
  5011. + work_mode = <0xff>;
  5012. + device_id = <2>;
  5013. + iommus = <&mmu_aw 1 0>;
  5014. + status = "disabled";
  5015. + };
  5016. + scaler03:scaler@590fff4 {
  5017. + compatible = "allwinner,sunxi-scaler";
  5018. + reg = <0x0 0x0590fff4 0x0 0x40c>;
  5019. + work_mode = <0xff>;
  5020. + device_id = <3>;
  5021. + iommus = <&mmu_aw 1 0>;
  5022. + status = "disabled";
  5023. + };
  5024. + scaler10:scaler@5910400 {
  5025. + compatible = "allwinner,sunxi-scaler";
  5026. + reg = <0x0 0x05910400 0x0 0x400>;
  5027. + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  5028. + work_mode = <0x0>;
  5029. + device_id = <4>;
  5030. + iommus = <&mmu_aw 1 0>;
  5031. + status = "disabled";
  5032. + };
  5033. + scaler11:scaler@59103fc {
  5034. + compatible = "allwinner,sunxi-scaler";
  5035. + reg = <0x0 0x059103fc 0x0 0x404>;
  5036. + work_mode = <0xff>;
  5037. + device_id = <5>;
  5038. + iommus = <&mmu_aw 1 0>;
  5039. + status = "disabled";
  5040. + };
  5041. + scaler12:scaler@59103f8 {
  5042. + compatible = "allwinner,sunxi-scaler";
  5043. + reg = <0x0 0x059103f8 0x0 0x408>;
  5044. + work_mode = <0xff>;
  5045. + device_id = <6>;
  5046. + iommus = <&mmu_aw 1 0>;
  5047. + status = "disabled";
  5048. + };
  5049. + scaler13:scaler@59103f4 {
  5050. + compatible = "allwinner,sunxi-scaler";
  5051. + reg = <0x0 0x059103f4 0x0 0x40c>;
  5052. + work_mode = <0xff>;
  5053. + device_id = <7>;
  5054. + iommus = <&mmu_aw 1 0>;
  5055. + status = "disabled";
  5056. + };
  5057. + scaler20:scaler@5910800 {
  5058. + compatible = "allwinner,sunxi-scaler";
  5059. + reg = <0x0 0x05910800 0x0 0x400>;
  5060. + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  5061. + work_mode = <0x0>;
  5062. + device_id = <8>;
  5063. + iommus = <&mmu_aw 1 0>;
  5064. + status = "disabled";
  5065. + };
  5066. + scaler21:scaler@59107fc {
  5067. + compatible = "allwinner,sunxi-scaler";
  5068. + reg = <0x0 0x059107fc 0x0 0x404>;
  5069. + work_mode = <0xff>;
  5070. + device_id = <9>;
  5071. + iommus = <&mmu_aw 1 0>;
  5072. + status = "disabled";
  5073. + };
  5074. + scaler22:scaler@59107f8 {
  5075. + compatible = "allwinner,sunxi-scaler";
  5076. + reg = <0x0 0x059107f8 0x0 0x408>;
  5077. + work_mode = <0xff>;
  5078. + device_id = <10>;
  5079. + iommus = <&mmu_aw 1 0>;
  5080. + status = "disabled";
  5081. + };
  5082. + scaler23:scaler@59107f4 {
  5083. + compatible = "allwinner,sunxi-scaler";
  5084. + reg = <0x0 0x059107f4 0x0 0x40c>;
  5085. + work_mode = <0xff>;
  5086. + device_id = <11>;
  5087. + iommus = <&mmu_aw 1 0>;
  5088. + status = "disabled";
  5089. + };
  5090. + scaler30:scaler@5910c00 {
  5091. + compatible = "allwinner,sunxi-scaler";
  5092. + reg = <0x0 0x05910c00 0x0 0x400>;
  5093. + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
  5094. + work_mode = <0x0>;
  5095. + device_id = <12>;
  5096. + iommus = <&mmu_aw 1 0>;
  5097. + status = "disabled";
  5098. + };
  5099. + scaler31:scaler@5910bfc {
  5100. + compatible = "allwinner,sunxi-scaler";
  5101. + reg = <0x0 0x05910bfc 0x0 0x404>;
  5102. + work_mode = <0xff>;
  5103. + device_id = <13>;
  5104. + iommus = <&mmu_aw 1 0>;
  5105. + status = "disabled";
  5106. + };
  5107. + scaler32:scaler@5910bf8 {
  5108. + compatible = "allwinner,sunxi-scaler";
  5109. + reg = <0x0 0x05910bf8 0x0 0x408>;
  5110. + work_mode = <0xff>;
  5111. + device_id = <14>;
  5112. + iommus = <&mmu_aw 1 0>;
  5113. + status = "disabled";
  5114. + };
  5115. + scaler33:scaler@5910bf4 {
  5116. + compatible = "allwinner,sunxi-scaler";
  5117. + reg = <0x0 0x05910bf4 0x0 0x40c>;
  5118. + work_mode = <0xff>;
  5119. + device_id = <15>;
  5120. + iommus = <&mmu_aw 1 0>;
  5121. + status = "disabled";
  5122. + };
  5123. + scaler40:scaler@16 {
  5124. + compatible = "allwinner,sunxi-scaler";
  5125. + device_id = <16>;
  5126. + iommus = <&mmu_aw 1 0>;
  5127. + status = "disabled";
  5128. + };
  5129. + scaler50:scaler@17 {
  5130. + compatible = "allwinner,sunxi-scaler";
  5131. + device_id = <17>;
  5132. + iommus = <&mmu_aw 1 0>;
  5133. + status = "disabled";
  5134. + };
  5135. + actuator0: actuator@2108180 {
  5136. + compatible = "allwinner,sunxi-actuator";
  5137. + device_type = "actuator0";
  5138. + reg = <0x0 0x02108180 0x0 0x10>;
  5139. + actuator0_name = "ad5820_act";
  5140. + actuator0_slave = <0x18>;
  5141. + actuator0_af_pwdn = <>;
  5142. + actuator0_afvdd = "afvcc-csi";
  5143. + actuator0_afvdd_vol = <2800000>;
  5144. + status = "disabled";
  5145. + };
  5146. + flash0: flash@2108190 {
  5147. + device_type = "flash0";
  5148. + compatible = "allwinner,sunxi-flash";
  5149. + reg = <0x0 0x02108190 0x0 0x10>;
  5150. + flash0_type = <2>;
  5151. + flash0_en = <>;
  5152. + flash0_mode = <>;
  5153. + flash0_flvdd = "";
  5154. + flash0_flvdd_vol = <>;
  5155. + device_id = <0>;
  5156. + status = "disabled";
  5157. + };
  5158. + sensor0: sensor@5812000 {
  5159. + reg = <0x0 0x05812000 0x0 0x10>;
  5160. + device_type = "sensor0";
  5161. + compatible = "allwinner,sunxi-sensor";
  5162. + sensor0_mname = "ov5640";
  5163. + sensor0_twi_cci_id = <2>;
  5164. + sensor0_twi_addr = <0x78>;
  5165. + sensor0_mclk_id = <0>;
  5166. + sensor0_pos = "rear";
  5167. + sensor0_isp_used = <0>;
  5168. + sensor0_fmt = <0>;
  5169. + sensor0_stby_mode = <0>;
  5170. + sensor0_vflip = <0>;
  5171. + sensor0_hflip = <0>;
  5172. + sensor0_iovdd-supply = <>;
  5173. + sensor0_iovdd_vol = <>;
  5174. + sensor0_avdd-supply = <>;
  5175. + sensor0_avdd_vol = <>;
  5176. + sensor0_dvdd-supply = <>;
  5177. + sensor0_dvdd_vol = <>;
  5178. + sensor0_power_en = <>;
  5179. + sensor0_reset = <>;
  5180. + sensor0_pwdn = <>;
  5181. + sensor0_sm_vs = <>;
  5182. + flash_handle = <&flash0>;
  5183. + act_handle = <&actuator0>;
  5184. + device_id = <0>;
  5185. + status = "disabled";
  5186. + };
  5187. + sensor1: sensor@5812010 {
  5188. + reg = <0x0 0x05812010 0x0 0x10>;
  5189. + device_type = "sensor1";
  5190. + compatible = "allwinner,sunxi-sensor";
  5191. + sensor1_mname = "ov5647";
  5192. + sensor1_twi_cci_id = <3>;
  5193. + sensor1_twi_addr = <0x6c>;
  5194. + sensor1_mclk_id = <1>;
  5195. + sensor1_pos = "front";
  5196. + sensor1_isp_used = <0>;
  5197. + sensor1_fmt = <0>;
  5198. + sensor1_stby_mode = <0>;
  5199. + sensor1_vflip = <0>;
  5200. + sensor1_hflip = <0>;
  5201. + sensor1_iovdd-supply = <>;
  5202. + sensor1_iovdd_vol = <>;
  5203. + sensor1_avdd-supply = <>;
  5204. + sensor1_avdd_vol = <>;
  5205. + sensor1_dvdd-supply = <>;
  5206. + sensor1_dvdd_vol = <>;
  5207. + sensor1_power_en = <>;
  5208. + sensor1_reset = <>;
  5209. + sensor1_pwdn = <>;
  5210. + sensor1_sm_vs = <>;
  5211. + flash_handle = <>;
  5212. + act_handle = <>;
  5213. + device_id = <1>;
  5214. + status = "disabled";
  5215. + };
  5216. + sensor2: sensor@5812020 {
  5217. + reg = <0x0 0x05812020 0x0 0x10>;
  5218. + device_type = "sensor2";
  5219. + compatible = "allwinner,sunxi-sensor";
  5220. + sensor2_mname = "imx386_mipi";
  5221. + sensor2_twi_cci_id = <3>;
  5222. + sensor2_twi_addr = <0x6c>;
  5223. + sensor2_mclk_id = <1>;
  5224. + sensor2_pos = "rear";
  5225. + sensor2_isp_used = <0>;
  5226. + sensor2_fmt = <0>;
  5227. + sensor2_stby_mode = <0>;
  5228. + sensor2_vflip = <0>;
  5229. + sensor2_hflip = <0>;
  5230. + sensor2_iovdd-supply = <>;
  5231. + sensor2_iovdd_vol = <>;
  5232. + sensor2_avdd-supply = <>;
  5233. + sensor2_avdd_vol = <>;
  5234. + sensor2_dvdd-supply = <>;
  5235. + sensor2_dvdd_vol = <>;
  5236. + sensor2_power_en = <>;
  5237. + sensor2_reset = <>;
  5238. + sensor2_pwdn = <>;
  5239. + sensor2_sm_vs = <>;
  5240. + flash_handle = <>;
  5241. + act_handle = <>;
  5242. + device_id = <2>;
  5243. + status = "disabled";
  5244. + };
  5245. + sensor_list0:sensor_list@5812040 {
  5246. + reg = <0x0 0x05812040 0x0 0x10>;
  5247. + device_type = "sensor_list0";
  5248. + compatible = "allwinner,sunxi-sensor-list";
  5249. + csi_sel = <0>;
  5250. + sensor00_mname = "ov5675_mipi_b";
  5251. + sensor00_twi_addr = <0x60>;
  5252. + sensor00_type = <1>;
  5253. + sensor00_hflip = <1>;
  5254. + sensor00_vflip = <0>;
  5255. + sensor00_act_used = <1>;
  5256. + sensor00_act_name = "dw9714_act";
  5257. + sensor00_act_twi_addr = <0x18>;
  5258. + sensor01_mname = "gc05a2_mipi_b";
  5259. + sensor01_twi_addr = <0x62>;
  5260. + sensor01_type = <1>;
  5261. + sensor01_hflip = <0>;
  5262. + sensor01_vflip = <0>;
  5263. + sensor01_act_used = <1>;
  5264. + sensor01_act_name = "dw9714_act";
  5265. + sensor01_act_twi_addr = <0x18>;
  5266. + sensor02_mname = "gc5035_mipi_b";
  5267. + sensor02_twi_addr = <0x64>;
  5268. + sensor02_type = <1>;
  5269. + sensor02_hflip = <0>;
  5270. + sensor02_vflip = <0>;
  5271. + sensor02_act_used = <1>;
  5272. + sensor02_act_name = "dw9714_act";
  5273. + sensor02_act_twi_addr = <0x18>;
  5274. + device_id = <0>;
  5275. + status = "disabled";
  5276. + };
  5277. + sensor_list1:sensor_list@5812050 {
  5278. + reg = <0x0 0x05812050 0x0 0x10>;
  5279. + device_type = "sensor_list1";
  5280. + compatible = "allwinner,sunxi-sensor-list";
  5281. + csi_sel = <0>;
  5282. + sensor10_mname = "ov02a10_mipi_f";
  5283. + sensor10_twi_addr = <0x70>;
  5284. + sensor10_type = <1>;
  5285. + sensor10_hflip = <1>;
  5286. + sensor10_vflip = <0>;
  5287. + sensor10_act_used = <0>;
  5288. + sensor10_act_name = "";
  5289. + sensor10_act_twi_addr = <>;
  5290. + sensor11_mname = "gc02m1_mipi_f";
  5291. + sensor11_twi_addr = <0x72>;
  5292. + sensor11_type = <1>;
  5293. + sensor11_hflip = <1>;
  5294. + sensor11_vflip = <0>;
  5295. + sensor11_act_used = <0>;
  5296. + sensor11_act_name = "";
  5297. + sensor11_act_twi_addr = <>;
  5298. + sensor12_mname = "gc02m2_mipi_f";
  5299. + sensor12_twi_addr = <0x74>;
  5300. + sensor12_type = <1>;
  5301. + sensor12_hflip = <0>;
  5302. + sensor12_vflip = <0>;
  5303. + sensor12_act_used = <0>;
  5304. + sensor12_act_name = "";
  5305. + sensor12_act_twi_addr = <>;
  5306. + device_id = <1>;
  5307. + status = "disabled";
  5308. + };
  5309. + vinc00:vinc@5830000 {
  5310. + device_type = "vinc0";
  5311. + compatible = "allwinner,sunxi-vin-core";
  5312. + reg = <0x0 0x05830000 0x0 0x1000>;
  5313. + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  5314. + vinc0_csi_sel = <1>;
  5315. + vinc0_mipi_sel = <0xff>;
  5316. + vinc0_isp_sel = <0>;
  5317. + vinc0_isp_tx_ch = <0>;
  5318. + vinc0_tdm_rx_sel = <0>;
  5319. + vinc0_rear_sensor_sel = <0>;
  5320. + vinc0_front_sensor_sel = <0>;
  5321. + vinc0_sensor_list = <0>;
  5322. + device_id = <0>;
  5323. + work_mode = <0x0>;
  5324. + iommus = <&mmu_aw 1 0>;
  5325. + status = "disabled";
  5326. + };
  5327. + vinc01:vinc@582fffc {
  5328. + device_type = "vinc1";
  5329. + compatible = "allwinner,sunxi-vin-core";
  5330. + reg = <0x0 0x0582fffc 0x0 0x1004>;
  5331. + vinc1_csi_sel = <1>;
  5332. + vinc1_mipi_sel = <0xff>;
  5333. + vinc1_isp_sel = <1>;
  5334. + vinc1_isp_tx_ch = <0>;
  5335. + vinc1_tdm_rx_sel = <1>;
  5336. + vinc1_rear_sensor_sel = <0>;
  5337. + vinc1_front_sensor_sel = <0>;
  5338. + vinc1_sensor_list = <0>;
  5339. + device_id = <1>;
  5340. + work_mode = <0xff>;
  5341. + iommus = <&mmu_aw 1 0>;
  5342. + status = "disabled";
  5343. + };
  5344. +
  5345. + vinc02:vinc@582fff8 {
  5346. + device_type = "vinc2";
  5347. + compatible = "allwinner,sunxi-vin-core";
  5348. + reg = <0x0 0x0582fff8 0x0 0x1008>;
  5349. + vinc2_csi_sel = <2>;
  5350. + vinc2_mipi_sel = <0xff>;
  5351. + vinc2_isp_sel = <2>;
  5352. + vinc2_isp_tx_ch = <2>;
  5353. + vinc2_tdm_rx_sel = <2>;
  5354. + vinc2_rear_sensor_sel = <0>;
  5355. + vinc2_front_sensor_sel = <0>;
  5356. + vinc2_sensor_list = <0>;
  5357. + device_id = <2>;
  5358. + work_mode = <0xff>;
  5359. + iommus = <&mmu_aw 1 0>;
  5360. + status = "disabled";
  5361. + };
  5362. + vinc03:vinc@582fff4 {
  5363. + device_type = "vinc3";
  5364. + compatible = "allwinner,sunxi-vin-core";
  5365. + reg = <0x0 0x0582fff4 0x0 0x100c>;
  5366. + vinc3_csi_sel = <0>;
  5367. + vinc3_mipi_sel = <0xff>;
  5368. + vinc3_isp_sel = <0>;
  5369. + vinc3_isp_tx_ch = <0>;
  5370. + vinc3_tdm_rx_sel = <0>;
  5371. + vinc3_rear_sensor_sel = <1>;
  5372. + vinc3_front_sensor_sel = <1>;
  5373. + vinc3_sensor_list = <0>;
  5374. + device_id = <3>;
  5375. + work_mode = <0xff>;
  5376. + iommus = <&mmu_aw 1 0>;
  5377. + status = "disabled";
  5378. + };
  5379. + vinc10:vinc@5831000 {
  5380. + device_type = "vinc4";
  5381. + compatible = "allwinner,sunxi-vin-core";
  5382. + reg = <0x0 0x05831000 0x0 0x1000>;
  5383. + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  5384. + vinc4_csi_sel = <1>;
  5385. + vinc4_mipi_sel = <0xff>;
  5386. + vinc4_isp_sel = <0>;
  5387. + vinc4_isp_tx_ch = <0>;
  5388. + vinc4_tdm_rx_sel = <0>;
  5389. + vinc4_rear_sensor_sel = <0>;
  5390. + vinc4_front_sensor_sel = <0>;
  5391. + vinc4_sensor_list = <0>;
  5392. + device_id = <4>;
  5393. + work_mode = <0x0>;
  5394. + iommus = <&mmu_aw 1 0>;
  5395. + status = "disabled";
  5396. + };
  5397. + vinc11:vinc@5830ffc {
  5398. + device_type = "vinc5";
  5399. + compatible = "allwinner,sunxi-vin-core";
  5400. + reg = <0x0 0x05830ffc 0x0 0x1004>;
  5401. + vinc5_csi_sel = <2>;
  5402. + vinc5_mipi_sel = <0xff>;
  5403. + vinc5_isp_sel = <1>;
  5404. + vinc5_isp_tx_ch = <1>;
  5405. + vinc5_tdm_rx_sel = <1>;
  5406. + vinc5_rear_sensor_sel = <0>;
  5407. + vinc5_front_sensor_sel = <0>;
  5408. + vinc5_sensor_list = <0>;
  5409. + device_id = <5>;
  5410. + work_mode = <0xff>;
  5411. + iommus = <&mmu_aw 1 0>;
  5412. + status = "disabled";
  5413. + };
  5414. + vinc12:vinc@5830ff8 {
  5415. + device_type = "vinc6";
  5416. + compatible = "allwinner,sunxi-vin-core";
  5417. + reg = <0x0 0x05830ff8 0x0 0x1008>;
  5418. + vinc6_csi_sel = <2>;
  5419. + vinc6_mipi_sel = <0xff>;
  5420. + vinc6_isp_sel = <0>;
  5421. + vinc6_isp_tx_ch = <0>;
  5422. + vinc6_tdm_rx_sel = <0>;
  5423. + vinc6_rear_sensor_sel = <0>;
  5424. + vinc6_front_sensor_sel = <0>;
  5425. + vinc6_sensor_list = <0>;
  5426. + device_id = <6>;
  5427. + work_mode = <0xff>;
  5428. + iommus = <&mmu_aw 1 0>;
  5429. + status = "disabled";
  5430. + };
  5431. + vinc13:vinc@5830ff4 {
  5432. + device_type = "vinc7";
  5433. + compatible = "allwinner,sunxi-vin-core";
  5434. + reg = <0x0 0x05830ff4 0x0 0x100c>;
  5435. + vinc7_csi_sel = <2>;
  5436. + vinc7_mipi_sel = <0xff>;
  5437. + vinc7_isp_sel = <0>;
  5438. + vinc7_isp_tx_ch = <0>;
  5439. + vinc7_tdm_rx_sel = <0>;
  5440. + vinc7_rear_sensor_sel = <0>;
  5441. + vinc7_front_sensor_sel = <0>;
  5442. + vinc7_sensor_list = <0>;
  5443. + device_id = <7>;
  5444. + work_mode = <0xff>;
  5445. + iommus = <&mmu_aw 1 0>;
  5446. + status = "disabled";
  5447. + };
  5448. + vinc20:vinc@5832000 {
  5449. + device_type = "vinc8";
  5450. + compatible = "allwinner,sunxi-vin-core";
  5451. + reg = <0x0 0x05832000 0x0 0x1000>;
  5452. + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  5453. + vinc8_csi_sel = <2>;
  5454. + vinc8_mipi_sel = <0xff>;
  5455. + vinc8_isp_sel = <4>;
  5456. + vinc8_isp_tx_ch = <3>;
  5457. + vinc8_tdm_rx_sel = <3>;
  5458. + vinc8_rear_sensor_sel = <0>;
  5459. + vinc8_front_sensor_sel = <0>;
  5460. + vinc8_sensor_list = <0>;
  5461. + device_id = <8>;
  5462. + work_mode = <0x0>;
  5463. + iommus = <&mmu_aw 1 0>;
  5464. + status = "disabled";
  5465. + };
  5466. + vinc21:vinc@5831ffc {
  5467. + device_type = "vinc9";
  5468. + compatible = "allwinner,sunxi-vin-core";
  5469. + reg = <0x0 0x05831ffc 0x0 0x1004>;
  5470. + vinc9_csi_sel = <2>;
  5471. + vinc9_mipi_sel = <0xff>;
  5472. + vinc9_isp_sel = <0>;
  5473. + vinc9_isp_tx_ch = <0>;
  5474. + vinc9_tdm_rx_sel = <0>;
  5475. + vinc9_rear_sensor_sel = <0>;
  5476. + vinc9_front_sensor_sel = <0>;
  5477. + vinc9_sensor_list = <0>;
  5478. + device_id = <9>;
  5479. + work_mode = <0xff>;
  5480. + iommus = <&mmu_aw 1 0>;
  5481. + status = "disabled";
  5482. + };
  5483. + vinc22:vinc@5831ff8 {
  5484. + device_type = "vinc10";
  5485. + compatible = "allwinner,sunxi-vin-core";
  5486. + reg = <0x0 0x05831ff8 0x0 0x1008>;
  5487. + vinc10_csi_sel = <2>;
  5488. + vinc10_mipi_sel = <0xff>;
  5489. + vinc10_isp_sel = <0>;
  5490. + vinc10_isp_tx_ch = <0>;
  5491. + vinc10_tdm_rx_sel = <0>;
  5492. + vinc10_rear_sensor_sel = <0>;
  5493. + vinc10_front_sensor_sel = <0>;
  5494. + vinc10_sensor_list = <0>;
  5495. + device_id = <10>;
  5496. + work_mode = <0xff>;
  5497. + iommus = <&mmu_aw 1 0>;
  5498. + status = "disabled";
  5499. + };
  5500. + vinc23:vinc@5831ff4 {
  5501. + device_type = "vinc11";
  5502. + compatible = "allwinner,sunxi-vin-core";
  5503. + reg = <0x0 0x05831ff4 0x0 0x100c>;
  5504. + vinc11_csi_sel = <2>;
  5505. + vinc11_mipi_sel = <0xff>;
  5506. + vinc11_isp_sel = <0>;
  5507. + vinc11_isp_tx_ch = <0>;
  5508. + vinc11_tdm_rx_sel = <0>;
  5509. + vinc11_rear_sensor_sel = <0>;
  5510. + vinc11_front_sensor_sel = <0>;
  5511. + vinc11_sensor_list = <0>;
  5512. + device_id = <11>;
  5513. + work_mode = <0xff>;
  5514. + iommus = <&mmu_aw 1 0>;
  5515. + status = "disabled";
  5516. + };
  5517. + vinc30:vinc@5833000 {
  5518. + device_type = "vinc12";
  5519. + compatible = "allwinner,sunxi-vin-core";
  5520. + reg = <0x0 0x05833000 0x0 0x1000>;
  5521. + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
  5522. + vinc12_csi_sel = <2>;
  5523. + vinc12_mipi_sel = <0xff>;
  5524. + vinc12_isp_sel = <0>;
  5525. + vinc12_isp_tx_ch = <0>;
  5526. + vinc12_tdm_rx_sel = <0>;
  5527. + vinc12_rear_sensor_sel = <0>;
  5528. + vinc12_front_sensor_sel = <0>;
  5529. + vinc12_sensor_list = <0>;
  5530. + device_id = <12>;
  5531. + work_mode = <0x0>;
  5532. + iommus = <&mmu_aw 1 0>;
  5533. + status = "disabled";
  5534. + };
  5535. + vinc31:vinc@5832ffc {
  5536. + device_type = "vinc13";
  5537. + compatible = "allwinner,sunxi-vin-core";
  5538. + reg = <0x0 0x05832ffc 0x0 0x1004>;
  5539. + vinc13_csi_sel = <2>;
  5540. + vinc13_mipi_sel = <0xff>;
  5541. + vinc13_isp_sel = <0>;
  5542. + vinc13_isp_tx_ch = <0>;
  5543. + vinc13_tdm_rx_sel = <0>;
  5544. + vinc13_rear_sensor_sel = <0>;
  5545. + vinc13_front_sensor_sel = <0>;
  5546. + vinc13_sensor_list = <0>;
  5547. + device_id = <13>;
  5548. + work_mode = <0xff>;
  5549. + iommus = <&mmu_aw 1 0>;
  5550. + status = "disabled";
  5551. + };
  5552. + vinc32:vinc@5832ff8 {
  5553. + device_type = "vinc14";
  5554. + compatible = "allwinner,sunxi-vin-core";
  5555. + reg = <0x0 0x05832ff8 0x0 0x1008>;
  5556. + vinc14_csi_sel = <2>;
  5557. + vinc14_mipi_sel = <0xff>;
  5558. + vinc14_isp_sel = <0>;
  5559. + vinc14_isp_tx_ch = <0>;
  5560. + vinc14_tdm_rx_sel = <0>;
  5561. + vinc14_rear_sensor_sel = <0>;
  5562. + vinc14_front_sensor_sel = <0>;
  5563. + vinc14_sensor_list = <0>;
  5564. + device_id = <14>;
  5565. + work_mode = <0xff>;
  5566. + iommus = <&mmu_aw 1 0>;
  5567. + status = "disabled";
  5568. + };
  5569. + vinc33:vinc@5832ff4 {
  5570. + device_type = "vinc15";
  5571. + compatible = "allwinner,sunxi-vin-core";
  5572. + reg = <0x0 0x05832ff4 0x0 0x100c>;
  5573. + vinc15_csi_sel = <2>;
  5574. + vinc15_mipi_sel = <0xff>;
  5575. + vinc15_isp_sel = <0>;
  5576. + vinc15_isp_tx_ch = <0>;
  5577. + vinc15_tdm_rx_sel = <0>;
  5578. + vinc15_rear_sensor_sel = <0>;
  5579. + vinc15_front_sensor_sel = <0>;
  5580. + vinc15_sensor_list = <0>;
  5581. + device_id = <15>;
  5582. + work_mode = <0xff>;
  5583. + iommus = <&mmu_aw 1 0>;
  5584. + status = "disabled";
  5585. + };
  5586. + vinc40:vinc@5834000 {
  5587. + device_type = "vinc16";
  5588. + compatible = "allwinner,sunxi-vin-core";
  5589. + reg = <0x0 0x05834000 0x0 0x1000>;
  5590. + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  5591. + vinc16_csi_sel = <2>;
  5592. + vinc16_mipi_sel = <0xff>;
  5593. + vinc16_isp_sel = <0>;
  5594. + vinc16_isp_tx_ch = <0>;
  5595. + vinc16_tdm_rx_sel = <0>;
  5596. + vinc16_rear_sensor_sel = <0>;
  5597. + vinc16_front_sensor_sel = <0>;
  5598. + vinc16_sensor_list = <0>;
  5599. + device_id = <16>;
  5600. + work_mode = <0x0>;
  5601. + iommus = <&mmu_aw 1 0>;
  5602. + status = "disabled";
  5603. + };
  5604. + vinc50:vinc@5835000 {
  5605. + device_type = "vinc17";
  5606. + compatible = "allwinner,sunxi-vin-core";
  5607. + reg = <0x0 0x05835000 0x0 0x1000>;
  5608. + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  5609. + vinc17_csi_sel = <2>;
  5610. + vinc17_mipi_sel = <0xff>;
  5611. + vinc17_isp_sel = <0>;
  5612. + vinc17_isp_tx_ch = <0>;
  5613. + vinc17_tdm_rx_sel = <0>;
  5614. + vinc17_rear_sensor_sel = <0>;
  5615. + vinc17_front_sensor_sel = <0>;
  5616. + vinc17_sensor_list = <0>;
  5617. + device_id = <17>;
  5618. + work_mode = <0x0>;
  5619. + iommus = <&mmu_aw 1 0>;
  5620. + status = "disabled";
  5621. + };
  5622. + };
  5623. +
  5624. + di:deinterlace@5400000 {
  5625. + #address-cells = <1>;
  5626. + #size-cells = <0>;
  5627. + compatible = "allwinner,sunxi-deinterlace";
  5628. + reg = <0x0 0x05400000 0x0 0x040000>;
  5629. + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  5630. + iommus = <&mmu_aw 9 1>;
  5631. + power-domains = <&pck600 PD_DE_SYS>;
  5632. + status = "okay";
  5633. +
  5634. + clocks = <&ccu CLK_DI>, <&ccu CLK_DI_GATE>;
  5635. + clock-names = "clk_di", "clk_bus_di";
  5636. + clock-frequency = <300000000>;
  5637. +
  5638. + resets = <&ccu RST_BUS_DI>, <&ccu RST_BUS_DE_SY>;
  5639. + reset-names = "rst_bus_di", "rst_bus_desys";
  5640. + };
  5641. +
  5642. + g2d: g2d@5440000 {
  5643. + compatible = "allwinner,sunxi-g2d";
  5644. + reg = <0x0 0x05440000 0x0 0x30000>;
  5645. + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  5646. + clocks = <&ccu CLK_G2D_GATE>, <&ccu CLK_G2D>,
  5647. + <&ccu CLK_MBUS_DESYS_GATE>, <&ccu CLK_DE_AHB_GATE>;
  5648. + clock-names = "bus", "g2d", "mbus_desys", "ahb_de";
  5649. + resets = <&ccu RST_BUS_G2D>, <&ccu RST_BUS_DE_SY>;
  5650. + reset-names = "rst_bus_g2d", "rst_bus_desys";
  5651. + iommus = <&mmu_aw 10 1>;
  5652. + //nsi = <&nsi0 5>;
  5653. + power-domains = <&pck600 PD_DE_SYS>;
  5654. + power-domain-names = "pd_de_sys";
  5655. + assigned-clocks = <&ccu CLK_G2D>;
  5656. + assigned-clock-rates = <300000000>;
  5657. + status = "disabled";
  5658. + };
  5659. +
  5660. + gmac_stmmac_axi_setup: stmmac-axi-config {
  5661. + snps,lpi_en;
  5662. + snps,wr_osr_lmt = <0xf>;
  5663. + snps,rd_osr_lmt = <0xf>;
  5664. + snps,blen = <256 128 64 32 16 8 4>;
  5665. + };
  5666. +
  5667. + gmac_mtl_rx_setup: rx-queues-config {
  5668. + snps,rx-queues-to-use = <1>;
  5669. + queue0 {};
  5670. + };
  5671. +
  5672. + gmac_mtl_tx_setup: tx_queues-config {
  5673. + snps,tx-queues-to-use = <1>;
  5674. + queue0 {};
  5675. + };
  5676. +
  5677. + gmac0: ethernet@4500000 {
  5678. + compatible = "allwinner,sunxi-gmac-210", "snps,dwmac-5.20";
  5679. + reg = <0x0 0x04500000 0x0 0x8000>, <0x0 0x04508000 0x0 0x1000>;
  5680. + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
  5681. + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
  5682. + interrupt-names = "macirq", "eth_lpi", "tx0_irq", "rx0_irq";
  5683. + clocks = <&ccu CLK_GMAC0>, <&ccu CLK_GMAC0_MBUS>, <&ccu CLK_GMAC0_PHY>, <&ccu CLK_GMAC_PTP>;
  5684. + clock-names = "stmmaceth", "pclk", "phy", "ptp_ref";
  5685. + assigned-clocks = <&ccu CLK_GMAC0_PHY>;
  5686. + assigned-clock-rates = <25000000>;
  5687. + resets = <&ccu RST_BUS_GMAC0_AXI>, <&ccu RST_BUS_GMAC0>;
  5688. + reset-names = "stmmaceth", "ahb";
  5689. + phy-mode = "rgmii";
  5690. + phy-handle = <&gmac0_phy0>;
  5691. + status = "disabled";
  5692. +
  5693. + //aw,rgmii-clk-ext;
  5694. + snps,fixed-burst;
  5695. + snps,en-tx-lpi-clockgating;
  5696. + snps,axi-config = <&gmac_stmmac_axi_setup>;
  5697. + snps,mtl-rx-config = <&gmac_mtl_rx_setup>;
  5698. + snps,mtl-tx-config = <&gmac_mtl_tx_setup>;
  5699. +
  5700. + mdio0: mdio0@0 {
  5701. + compatible = "snps,dwmac-mdio";
  5702. + #address-cells = <1>;
  5703. + #size-cells = <0>;
  5704. + gmac0_phy0: ethernet-phy@1 {
  5705. + compatible = "ethernet-phy-ieee802.3-c22";
  5706. + reg = <0x1>;
  5707. + max-speed = <1000>; /* Max speed capability */
  5708. + reset-gpios = <&pio PA 14 GPIO_ACTIVE_LOW>;
  5709. + /* PHY datasheet rst time */
  5710. + reset-assert-us = <10000>;
  5711. + reset-deassert-us = <150000>;
  5712. + };
  5713. + };
  5714. + };
  5715. +
  5716. + gmac1: ethernet@4510000 {
  5717. + compatible = "allwinner,sunxi-gmac-210", "snps,dwmac-5.20";
  5718. + reg = <0x0 0x04510000 0x0 0x8000>, <0x0 0x04518000 0x0 0x1000>;
  5719. + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
  5720. + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
  5721. + interrupt-names = "macirq", "eth_lpi", "tx0_irq", "rx0_irq";
  5722. + clocks = <&ccu CLK_GMAC1>, <&ccu CLK_GMAC1_MBUS>, <&ccu CLK_GMAC1_PHY>, <&ccu CLK_GMAC_PTP>;
  5723. + clock-names = "stmmaceth", "pclk", "phy25m", "ptp_ref";
  5724. + assigned-clocks = <&ccu CLK_GMAC1_PHY>;
  5725. + assigned-clock-rates = <25000000>;
  5726. + resets = <&ccu RST_BUS_GMAC1_AXI>, <&ccu RST_BUS_GMAC1>;
  5727. + reset-names = "stmmaceth", "ahb";
  5728. + phy-mode = "rgmii";
  5729. + phy-handle = <&gmac1_phy0>;
  5730. + status = "disabled";
  5731. +
  5732. + aw,rgmii-clk-ext;
  5733. + snps,fixed-burst;
  5734. + snps,en-tx-lpi-clockgating;
  5735. + snps,axi-config = <&gmac_stmmac_axi_setup>;
  5736. + snps,mtl-rx-config = <&gmac_mtl_rx_setup>;
  5737. + snps,mtl-tx-config = <&gmac_mtl_tx_setup>;
  5738. +
  5739. + mdio1: mdio1@0 {
  5740. + compatible = "snps,dwmac-mdio";
  5741. + #address-cells = <1>;
  5742. + #size-cells = <0>;
  5743. + gmac1_phy0: ethernet-phy@1 {
  5744. + compatible = "ethernet-phy-ieee802.3-c22";
  5745. + reg = <0x1>;
  5746. + max-speed = <1000>; /* Max speed capability */
  5747. + reset-gpios = <&pio PA 14 GPIO_ACTIVE_LOW>;
  5748. + /* PHY datasheet rst time */
  5749. + reset-assert-us = <10000>;
  5750. + reset-deassert-us = <150000>;
  5751. + };
  5752. + };
  5753. + };
  5754. +
  5755. + uio0: uio@4500000 {
  5756. + compatible = "allwinner,sunxi-uio";
  5757. + reg = <0x0 0x04500000 0x0 0x10000>;
  5758. + sunxi,ethernet = <&gmac0>;
  5759. + status = "disabled";
  5760. + };
  5761. +
  5762. + uio1: uio@4510000 {
  5763. + compatible = "allwinner,sunxi-uio";
  5764. + reg = <0x0 0x04510000 0x0 0x10000>;
  5765. + sunxi,ethernet = <&gmac1>;
  5766. + status = "disabled";
  5767. + };
  5768. +
  5769. + rfkill: rfkill {
  5770. + compatible = "allwinner,sunxi-rfkill";
  5771. + status = "disabled";
  5772. + };
  5773. +
  5774. + addr_mgt: addr_mgt {
  5775. + compatible = "allwinner,sunxi-addr_mgt";
  5776. + status = "disabled";
  5777. + };
  5778. +
  5779. + btlpm: btlpm {
  5780. + compatible = "allwinner,sunxi-btlpm";
  5781. + };
  5782. +
  5783. + spi0: spi@2540000 {
  5784. + #address-cells = <1>;
  5785. + #size-cells = <0>;
  5786. + compatible = "allwinner,sunxi-spi-v1.3";
  5787. + device_type = "spi0";
  5788. + reg = <0x0 0x02540000 0x0 0x1000>;
  5789. + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  5790. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>;
  5791. + clock-names = "pll", "mod", "bus";
  5792. + clock-frequency = <100000000>;
  5793. + resets = <&ccu RST_BUS_SPI0>;
  5794. + dmas = <&dma 23>, <&dma 23>;
  5795. + dma-names = "tx", "rx";
  5796. + sunxi,spi-num-cs = <2>;
  5797. + status = "disabled";
  5798. + };
  5799. +
  5800. + spi1: spi@2541000 {
  5801. + #address-cells = <1>;
  5802. + #size-cells = <0>;
  5803. + compatible = "allwinner,sunxi-spi-v1.4";
  5804. + device_type = "spi1";
  5805. + reg = <0x0 0x02541000 0x0 0x1000>;
  5806. + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  5807. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>;
  5808. + clock-names = "pll", "mod", "bus";
  5809. + clock-frequency = <100000000>;
  5810. + resets = <&ccu RST_BUS_SPI1>;
  5811. + dmas = <&dma 24>, <&dma 24>;
  5812. + dma-names = "tx", "rx";
  5813. + sunxi,spi-num-cs = <1>;
  5814. + status = "disabled";
  5815. + };
  5816. +
  5817. + spi2: spi@2542000 {
  5818. + #address-cells = <1>;
  5819. + #size-cells = <0>;
  5820. + compatible = "allwinner,sunxi-spi-v1.3";
  5821. + device_type = "spi2";
  5822. + reg = <0x0 0x02542000 0x0 0x1000>;
  5823. + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  5824. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI2>, <&ccu CLK_BUS_SPI2>;
  5825. + clock-names = "pll", "mod", "bus";
  5826. + clock-frequency = <100000000>;
  5827. + resets = <&ccu RST_BUS_SPI2>;
  5828. + dmas = <&dma 25>, <&dma 25>;
  5829. + dma-names = "tx", "rx";
  5830. + sunxi,spi-num-cs = <1>;
  5831. + status = "disabled";
  5832. + };
  5833. +
  5834. + spi3: spi@2543000 {
  5835. + #address-cells = <1>;
  5836. + #size-cells = <0>;
  5837. + compatible = "allwinner,sunxi-spi-v1.3";
  5838. + device_type = "spi3";
  5839. + reg = <0x0 0x02543000 0x0 0x1000>;
  5840. + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  5841. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI3>, <&ccu CLK_BUS_SPI3>;
  5842. + clock-names = "pll", "mod", "bus";
  5843. + clock-frequency = <100000000>;
  5844. + resets = <&ccu RST_BUS_SPI3>;
  5845. + dmas = <&dma 26>, <&dma 26>;
  5846. + dma-names = "tx", "rx";
  5847. + sunxi,spi-num-cs = <1>;
  5848. + status = "disabled";
  5849. + };
  5850. +
  5851. + spi4: spi@2544000 {
  5852. + #address-cells = <1>;
  5853. + #size-cells = <0>;
  5854. + compatible = "allwinner,sunxi-spi-v1.3";
  5855. + device_type = "spi4";
  5856. + reg = <0x0 0x02544000 0x0 0x1000>;
  5857. + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  5858. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI4>, <&ccu CLK_BUS_SPI4>;
  5859. + clock-names = "pll", "mod", "bus";
  5860. + clock-frequency = <100000000>;
  5861. + resets = <&ccu RST_BUS_SPI4>;
  5862. + dmas = <&dma 54>, <&dma 54>;
  5863. + dma-names = "tx", "rx";
  5864. + sunxi,spi-num-cs = <1>;
  5865. + status = "disabled";
  5866. + };
  5867. +
  5868. + r_spi: spi@7092000 {
  5869. + #address-cells = <1>;
  5870. + #size-cells = <0>;
  5871. + compatible = "allwinner,sunxi-spi-v1.3";
  5872. + device_type = "r_spi";
  5873. + reg = <0x0 0x07092000 0x0 0x1000>;
  5874. + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
  5875. + clocks = <&ccu CLK_PLL_PERI0_300M>, <&r_ccu CLK_R_SPI>, <&r_ccu CLK_R_BUS_SPI>;
  5876. + clock-names = "pll", "mod", "bus";
  5877. + clock-frequency = <100000000>;
  5878. + resets = <&r_ccu RST_BUS_R_SPI>;
  5879. + dmas = <&dma 53>, <&dma 53>;
  5880. + dma-names = "tx", "rx";
  5881. + sunxi,spi-num-cs = <1>;
  5882. + status = "disabled";
  5883. + };
  5884. +
  5885. + serdes: serdes@6c00000 {
  5886. + compatible = "allwinner,cadence-combophy";
  5887. + reg = <0x0 0x06c00000 0x0 0x400>, /* serdes top register part-1 */
  5888. + <0x0 0x06c06000 0x0 0x2000>, /* serdes top register part-2 */
  5889. + <0x0 0x0709016c 0x0 0x4>; /* sys-rtc */
  5890. + clocks = <&ccu CLK_SERDES_PHY_CFG>,
  5891. + <&rtc_ccu CLK_RTC_DCXO_SERDES0>,
  5892. + <&rtc_ccu CLK_RTC_DCXO_SERDES1>;
  5893. + clock-names = "serdes-clk",
  5894. + "dcxo-serdes0-clk",
  5895. + "dcxo-serdes1-clk";
  5896. + resets = <&ccu RST_BUS_SERDES>;
  5897. + reset-names = "serdes-reset";
  5898. + #address-cells = <2>;
  5899. + #size-cells = <2>;
  5900. + ranges;
  5901. + status = "disabled";
  5902. +
  5903. + combophy0: combo-phy0@6c01000 {
  5904. + reg = <0x0 0x06c01000 0x0 0xa00>, /* combophy0 top register */
  5905. + <0x0 0x06c80000 0x0 0x20000>; /* combophy0 phy register*/
  5906. + combo0_dp: combo0-dp-phy {
  5907. + #phy-cells = <0>;
  5908. + status = "okay";
  5909. + };
  5910. + combo0_usb: combo0-usb-phy {
  5911. + #phy-cells = <0>;
  5912. + status = "okay";
  5913. + };
  5914. + };
  5915. +
  5916. + combophy1: combo-phy1@6c02000 {
  5917. + reg = <0x0 0x06c02000 0x0 0xa00>, /* combophy1 top register */
  5918. + <0x0 0x06ca0000 0x0 0x20000>; /* combophy1 phy register*/
  5919. + combo1_usb: combo1-usb-phy {
  5920. + #phy-cells = <0>;
  5921. + status = "okay";
  5922. + };
  5923. + combo1_pcie: combo1-pcie-phy {
  5924. + #phy-cells = <0>;
  5925. + status = "okay";
  5926. + };
  5927. + };
  5928. +
  5929. + aux_hpd: aux-hpd@6c01e00 {
  5930. + reg = <0x0 0x06c01e00 0x0 0x200>; /* aux_hpd top register */
  5931. + aux_hpd_phy: aux-hpd-phy {
  5932. + #phy-cells = <0>;
  5933. + status = "okay";
  5934. + };
  5935. + };
  5936. + };
  5937. +
  5938. + sunxi_drm: sunxi-drm {
  5939. + compatible = "allwinner,sunxi-drm";
  5940. + fb_base = <0>;
  5941. + status = "okay";
  5942. + };
  5943. +
  5944. + de: de@5000000 {
  5945. + compatible = "allwinner,display-engine-v352";
  5946. + iommus = <&mmu_aw 8 1>;
  5947. + nsi = <&nsi0 2>;
  5948. + power-domains = <&pck600 PD_DE_SYS>;
  5949. + reg = <0x0 0x5000000 0x0 0x400000>;
  5950. + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  5951. + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  5952. + clocks = <&ccu CLK_DE0>,
  5953. + <&ccu CLK_BUS_DE0>,
  5954. + <&ccu CLK_DE_AHB_GATE>,
  5955. + <&ccu CLK_MBUS_DESYS_GATE>;
  5956. + clock-names = "clk_de",
  5957. + "clk_bus_de",
  5958. + "ahb_vid_out",
  5959. + "mbus_vo_sys";
  5960. + resets = <&ccu RST_BUS_DE0>,
  5961. + <&ccu RST_BUS_DE_SY>;
  5962. + reset-names = "rst_bus_de",
  5963. + "rst_bus_de_sys";
  5964. + assigned-clocks = <&ccu CLK_DE0>;
  5965. + assigned-clock-parents = <&ccu CLK_PLL_DE_3X>;
  5966. + assigned-clock-rates = <600000000>;
  5967. + status = "okay";
  5968. + ports {
  5969. + #address-cells = <1>;
  5970. + #size-cells = <0>;
  5971. + disp0: port@0 {
  5972. + reg = <0>;
  5973. + #address-cells = <1>;
  5974. + #size-cells = <0>;
  5975. + disp0_out_tcon0: endpoint@0 {
  5976. + reg = <0>;
  5977. + remote-endpoint = <&tcon0_in_disp0>;
  5978. + };
  5979. + disp0_out_tcon1: endpoint@1 {
  5980. + reg = <1>;
  5981. + remote-endpoint = <&tcon1_in_disp0>;
  5982. + };
  5983. + disp0_out_tcon2: endpoint@2 {
  5984. + reg = <2>;
  5985. + remote-endpoint = <&tcon2_in_disp0>;
  5986. + };
  5987. + disp0_out_tcon3: endpoint@4 {
  5988. + reg = <4>;
  5989. + remote-endpoint = <&tcon3_in_disp0>;
  5990. + };
  5991. + disp0_out_tcon4: endpoint@5 {
  5992. + reg = <5>;
  5993. + remote-endpoint = <&tcon4_in_disp0>;
  5994. + };
  5995. + };
  5996. + disp1: port@1 {
  5997. + reg = <1>;
  5998. + #address-cells = <1>;
  5999. + #size-cells = <0>;
  6000. + disp1_out_tcon0: endpoint@0 {
  6001. + reg = <0>;
  6002. + remote-endpoint = <&tcon0_in_disp1>;
  6003. + };
  6004. + disp1_out_tcon1: endpoint@1 {
  6005. + reg = <1>;
  6006. + remote-endpoint = <&tcon1_in_disp1>;
  6007. + };
  6008. + disp1_out_tcon2: endpoint@2 {
  6009. + reg = <2>;
  6010. + remote-endpoint = <&tcon2_in_disp1>;
  6011. + };
  6012. + disp1_out_tcon3: endpoint@4 {
  6013. + reg = <4>;
  6014. + remote-endpoint = <&tcon3_in_disp1>;
  6015. + };
  6016. + disp1_out_tcon4: endpoint@5 {
  6017. + reg = <5>;
  6018. + remote-endpoint = <&tcon4_in_disp1>;
  6019. + };
  6020. + };
  6021. + };
  6022. + };
  6023. +
  6024. + vo0: vo0@5500000 {
  6025. + compatible = "allwinner,tcon-top0";
  6026. + reg = <0x0 0x05500000 0x0 0x1000>;
  6027. + clocks = <&ccu CLK_DPSS_TOP0>,
  6028. + <&ccu CLK_VID_OUT0_AHB_GATE>;
  6029. + clock-names = "clk_bus_dpss_top",
  6030. + "clk_ahb_gate";
  6031. + resets = <&ccu RST_BUS_DPSS_TOP0>,
  6032. + <&ccu RST_BUS_VIDEO_OUT0>;
  6033. + reset-names = "rst_bus_dpss_top",
  6034. + "rst_bus_reg";
  6035. + power-domains = <&pck600 PD_VO>;
  6036. + status = "disabled";
  6037. + };
  6038. +
  6039. + vo1: vo1@5510000 {
  6040. + compatible = "allwinner,tcon-top1";
  6041. + reg = <0x0 0x05510000 0x0 0x1000>;
  6042. + clocks = <&ccu CLK_DPSS_TOP1>,
  6043. + <&ccu CLK_VID_OUT1_AHB_GATE>;
  6044. + clock-names = "clk_bus_dpss_top",
  6045. + "clk_ahb_gate";
  6046. + resets = <&ccu RST_BUS_DPSS_TOP1>,
  6047. + <&ccu RST_BUS_VIDEO_OUT1>;
  6048. + reset-names = "rst_bus_dpss_top",
  6049. + "rst_bus_reg";
  6050. + power-domains = <&pck600 PD_VO1>;
  6051. + status = "disabled";
  6052. + };
  6053. +
  6054. + dlcd0: tcon0@5501000 {
  6055. + compatible = "allwinner,tcon-lcd";
  6056. + reg = <0x0 0x05501000 0x0 0x1000>;
  6057. + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  6058. + clocks = <&ccu CLK_BUS_VO0_TCONLCD0>;
  6059. + clock-names = "clk_bus_tcon";
  6060. + resets = <&ccu RST_BUS_VO0_TCONLCD0>;
  6061. + reset-names = "rst_bus_tcon";
  6062. + top = <&vo0>;
  6063. + status = "disabled";
  6064. + ports {
  6065. + #address-cells = <1>;
  6066. + #size-cells = <0>;
  6067. + tcon0_in: port@0 {
  6068. + #address-cells = <1>;
  6069. + #size-cells = <0>;
  6070. + reg = <0>;
  6071. + tcon0_in_disp0: endpoint@0 {
  6072. + reg = <0>;
  6073. + remote-endpoint = <&disp0_out_tcon0>;
  6074. + };
  6075. + tcon0_in_disp1: endpoint@1 {
  6076. + reg = <1>;
  6077. + remote-endpoint = <&disp1_out_tcon0>;
  6078. + };
  6079. + };
  6080. + tcon0_out: port@1 {
  6081. + #address-cells = <1>;
  6082. + #size-cells = <0>;
  6083. + reg = <1>;
  6084. + tcon0_out_dsi0: endpoint@0 {
  6085. + reg = <0>;
  6086. + remote-endpoint = <&dsi0_in_tcon0>;
  6087. + };
  6088. + tcon0_out_dsi1: endpoint@1 {
  6089. + reg = <1>;
  6090. + remote-endpoint = <&dsi1_in_tcon0>;
  6091. + };
  6092. + tcon0_out_lvds0: endpoint@2 {
  6093. + reg = <2>;
  6094. + remote-endpoint = <&lvds0_in_tcon0>;
  6095. + };
  6096. + tcon0_out_rgb0: endpoint@3 {
  6097. + reg = <3>;
  6098. + remote-endpoint = <&rgb0_in_tcon0>;
  6099. + };
  6100. + };
  6101. + };
  6102. + };
  6103. +
  6104. + dlcd1: tcon1@5502000 {
  6105. + compatible = "allwinner,tcon-lcd";
  6106. + reg = <0x0 0x05502000 0x0 0x1000>;
  6107. + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  6108. + clocks = <&ccu CLK_BUS_VO0_TCONLCD1>;
  6109. + clock-names = "clk_bus_tcon";
  6110. + resets = <&ccu RST_BUS_VO0_TCONLCD1>;
  6111. + reset-names = "rst_bus_tcon";
  6112. + top = <&vo0>;
  6113. + status = "disabled";
  6114. + // TODO find panel used of_graph?
  6115. + ports {
  6116. + #address-cells = <1>;
  6117. + #size-cells = <0>;
  6118. + tcon1_in: port@0 {
  6119. + reg = <0>;
  6120. + #address-cells = <1>;
  6121. + #size-cells = <0>;
  6122. + tcon1_in_disp0: endpoint@0 {
  6123. + reg = <0>;
  6124. + remote-endpoint = <&disp0_out_tcon1>;
  6125. + };
  6126. + tcon1_in_disp1: endpoint@1 {
  6127. + reg = <1>;
  6128. + remote-endpoint = <&disp1_out_tcon1>;
  6129. + };
  6130. + };
  6131. + tcon1_out: port@1 {
  6132. + #address-cells = <1>;
  6133. + #size-cells = <0>;
  6134. + reg = <1>;
  6135. + tcon1_out_dsi1: endpoint@0 {
  6136. + reg = <0>;
  6137. + remote-endpoint = <&dsi1_in_tcon1>;
  6138. + };
  6139. + };
  6140. + };
  6141. + };
  6142. +
  6143. + dlcd2: tcon2@5503000 {
  6144. + compatible = "allwinner,tcon-lcd";
  6145. + reg = <0x0 0x05503000 0x0 0x1000>;
  6146. + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  6147. + clocks = <&ccu CLK_VO0_TCONLCD2>,
  6148. + <&ccu CLK_BUS_VO0_TCONLCD2>;
  6149. + clock-names = "clk_tcon",
  6150. + "clk_bus_tcon";
  6151. + resets = <&ccu RST_BUS_VO0_TCONLCD2>;
  6152. + reset-names = "rst_bus_tcon";
  6153. + assigned-clocks = <&ccu CLK_VO0_TCONLCD2>;
  6154. + assigned-clock-parents = <&ccu CLK_PLL_VIDEO2_4X>;
  6155. + top = <&vo0>;
  6156. + status = "disabled";
  6157. +
  6158. + ports {
  6159. + #address-cells = <1>;
  6160. + #size-cells = <0>;
  6161. + tcon2_in: port@0 {
  6162. + #address-cells = <1>;
  6163. + #size-cells = <0>;
  6164. + reg = <0>;
  6165. + tcon2_in_disp0: endpoint@0 {
  6166. + reg = <0>;
  6167. + remote-endpoint = <&disp0_out_tcon2>;
  6168. + };
  6169. + tcon2_in_disp1: endpoint@1 {
  6170. + reg = <1>;
  6171. + remote-endpoint = <&disp1_out_tcon2>;
  6172. + };
  6173. + };
  6174. + tcon2_out: port@1 {
  6175. + #address-cells = <1>;
  6176. + #size-cells = <0>;
  6177. + reg = <1>;
  6178. + tcon2_out_lvds1: endpoint@0 {
  6179. + reg = <0>;
  6180. + remote-endpoint = <&lvds1_in_tcon2>;
  6181. + };
  6182. + tcon2_out_rgb1: endpoint@1 {
  6183. + reg = <1>;
  6184. + remote-endpoint = <&rgb1_in_tcon2>;
  6185. + };
  6186. + };
  6187. + };
  6188. + };
  6189. +
  6190. + dsi0combophy: phy@5507000 {
  6191. + compatible = "allwinner,sunxi-dsi-combo-phy0,sun60iw2";
  6192. + reg = <0x0 0x05507000 0x0 0x1ff>;
  6193. + clocks = <&ccu CLK_BUS_DSI0>;
  6194. + clock-names = "phy_gating_clk";
  6195. + resets = <&ccu RST_BUS_DSI0>;
  6196. + reset-names = "phy_rst_clk";
  6197. + #clock-cells = <1>;
  6198. + #phy-cells = <0>;
  6199. + status = "disabled";
  6200. + };
  6201. +
  6202. + dsi0: dsi0@5506000 {
  6203. + compatible = "allwinner,dsi0";
  6204. + reg = <0x0 0x05506000 0x0 0xfff>;
  6205. + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  6206. + clocks = <&ccu CLK_DSI0>,
  6207. + <&ccu CLK_BUS_DSI0>,
  6208. + <&dsi0combophy CLK_DSI_HS>,
  6209. + <&dsi0combophy CLK_DSI_LS>;
  6210. + clock-names = "dsi_clk",
  6211. + "dsi_gating_clk",
  6212. + "displl_hs",
  6213. + "displl_ls";
  6214. + resets = <&ccu RST_BUS_DSI0>;
  6215. + reset-names = "dsi_rst_clk";
  6216. + assigned-clocks = <&ccu CLK_DSI0>;
  6217. + assigned-clock-parents = <&ccu CLK_PLL_PERI0_150M>;
  6218. + phys = <&dsi0combophy>;
  6219. + phy-names = "combophy";
  6220. + status = "disabled";
  6221. +
  6222. + ports {
  6223. + #address-cells = <1>;
  6224. + #size-cells = <0>;
  6225. +
  6226. + dsi0_in: port@0 {
  6227. + reg = <0>;
  6228. + #address-cells = <1>;
  6229. + #size-cells = <0>;
  6230. + dsi0_in_tcon0: endpoint@0 {
  6231. + reg = <0>;
  6232. + remote-endpoint = <&tcon0_out_dsi0>;
  6233. + };
  6234. + };
  6235. + };
  6236. + };
  6237. +
  6238. + dsi1combophy: phy@5509000 {
  6239. + compatible = "allwinner,sunxi-dsi-combo-phy1,sun60iw2";
  6240. + reg = <0x0 0x05509000 0x0 0x1ff>;
  6241. + clocks = <&ccu CLK_BUS_DSI1>;
  6242. + clock-names = "phy_gating_clk";
  6243. + resets = <&ccu RST_BUS_DSI1>;
  6244. + reset-names = "phy_rst_clk";
  6245. + #clock-cells = <1>;
  6246. + #phy-cells = <0>;
  6247. + status = "disabled";
  6248. + };
  6249. +
  6250. + dsi1: dsi1@5508000 {
  6251. + compatible = "allwinner,dsi1";
  6252. + reg = <0x0 0x05508000 0x0 0xfff>;
  6253. + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  6254. + clocks = <&ccu CLK_DSI1>,
  6255. + <&ccu CLK_BUS_DSI1>,
  6256. + <&dsi1combophy CLK_DSI_HS>,
  6257. + <&dsi1combophy CLK_DSI_LS>;
  6258. + clock-names = "dsi_clk",
  6259. + "dsi_gating_clk",
  6260. + "displl_hs",
  6261. + "displl_ls";
  6262. + resets = <&ccu RST_BUS_DSI1>;
  6263. + reset-names = "dsi_rst_clk";
  6264. + assigned-clocks = <&ccu CLK_DSI1>;
  6265. + assigned-clock-parents = <&ccu CLK_PLL_PERI0_150M>;
  6266. + phys = <&dsi1combophy>;
  6267. + phy-names = "combophy";
  6268. + status = "disabled";
  6269. + ports {
  6270. + #address-cells = <1>;
  6271. + #size-cells = <0>;
  6272. +
  6273. + dsi1_in: port@0 {
  6274. + reg = <0>;
  6275. + #address-cells = <1>;
  6276. + #size-cells = <0>;
  6277. + dsi1_in_tcon0: endpoint@0 {
  6278. + reg = <0>;
  6279. + remote-endpoint = <&tcon0_out_dsi1>;
  6280. + };
  6281. + dsi1_in_tcon1: endpoint@1 {
  6282. + reg = <1>;
  6283. + remote-endpoint = <&tcon1_out_dsi1>;
  6284. + };
  6285. + };
  6286. + };
  6287. + };
  6288. +
  6289. + rgb0: rgb0@0001000 {
  6290. + compatible = "allwinner,rgb0";
  6291. + status = "disabled";
  6292. + ports {
  6293. + #address-cells = <1>;
  6294. + #size-cells = <0>;
  6295. + rgb0_in: port@0 {
  6296. + #address-cells = <1>;
  6297. + #size-cells = <0>;
  6298. + reg = <0>;
  6299. + rgb0_in_tcon0: endpoint@0 {
  6300. + reg = <0>;
  6301. + remote-endpoint = <&tcon0_out_rgb0>;
  6302. + };
  6303. + };
  6304. + };
  6305. + };
  6306. +
  6307. + lvds0: lvds0@0001000 {
  6308. + compatible = "allwinner,lvds0";
  6309. + clocks = <&dsi0combophy CLK_LVDS_OR_RGB>;
  6310. + clock-names = "lvds_pclk";
  6311. + resets = <&ccu RST_BUS_LVDS0>;
  6312. + reset-names = "rst_bus_lvds";
  6313. + phys = <&dsi0combophy>, <&dsi1combophy>;
  6314. + phy-names = "combophy0", "combophy1";
  6315. + status = "disabled";
  6316. +
  6317. + ports {
  6318. + #address-cells = <1>;
  6319. + #size-cells = <0>;
  6320. + lvds0_in: port@0 {
  6321. + #address-cells = <1>;
  6322. + #size-cells = <0>;
  6323. + reg = <0>;
  6324. + lvds0_in_tcon0: endpoint@0 {
  6325. + reg = <0>;
  6326. + remote-endpoint = <&tcon0_out_lvds0>;
  6327. + };
  6328. + };
  6329. + };
  6330. + };
  6331. +
  6332. + rgb1: rgb1@0001000 {
  6333. + compatible = "allwinner,rgb1";
  6334. + status = "disabled";
  6335. + ports {
  6336. + #address-cells = <1>;
  6337. + #size-cells = <0>;
  6338. + rgb1_in: port@0 {
  6339. + #address-cells = <1>;
  6340. + #size-cells = <0>;
  6341. + reg = <0>;
  6342. + rgb1_in_tcon2: endpoint@0 {
  6343. + reg = <0>;
  6344. + remote-endpoint = <&tcon2_out_rgb1>;
  6345. + };
  6346. + };
  6347. + };
  6348. + };
  6349. +
  6350. + lvds1: lvds1@0001000 {
  6351. + compatible = "allwinner,lvds1";
  6352. + resets = <&ccu RST_BUS_LVDS1>;
  6353. + reset-names = "rst_bus_lvds";
  6354. + status = "disabled";
  6355. +
  6356. + ports {
  6357. + #address-cells = <1>;
  6358. + #size-cells = <0>;
  6359. + lvds1_in: port@0 {
  6360. + #address-cells = <1>;
  6361. + #size-cells = <0>;
  6362. + reg = <0>;
  6363. + lvds1_in_tcon2: endpoint@0 {
  6364. + reg = <0>;
  6365. + remote-endpoint = <&tcon2_out_lvds1>;
  6366. + };
  6367. + };
  6368. + };
  6369. + };
  6370. +
  6371. + tv0: tcon3@5730000 {
  6372. + compatible = "allwinner,tcon-tv";
  6373. + reg = <0x0 0x05730000 0x0 0x1000>;
  6374. + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  6375. + clocks = <&ccu CLK_TCONTV0>;
  6376. + clock-names = "clk_bus_tcon";
  6377. + resets = <&ccu RST_BUS_TCONTV0>;
  6378. + reset-names = "rst_bus_tcon";
  6379. + top = <&vo1>;
  6380. + status = "disabled";
  6381. + ports {
  6382. + #address-cells = <1>;
  6383. + #size-cells = <0>;
  6384. + tcon3_in: port@0 {
  6385. + #address-cells = <1>;
  6386. + #size-cells = <0>;
  6387. + reg = <0>;
  6388. + tcon3_in_disp0: endpoint@0 {
  6389. + reg = <0>;
  6390. + remote-endpoint = <&disp0_out_tcon3>;
  6391. + };
  6392. + tcon3_in_disp1: endpoint@1 {
  6393. + reg = <1>;
  6394. + remote-endpoint = <&disp1_out_tcon3>;
  6395. + };
  6396. + };
  6397. + tcon3_out: port@1 {
  6398. + #address-cells = <1>;
  6399. + #size-cells = <0>;
  6400. + reg = <1>;
  6401. + tcon3_out_hdmi0: endpoint@0 {
  6402. + reg = <0>;
  6403. + remote-endpoint = <&hdmi0_in_tcon3>;
  6404. + };
  6405. + };
  6406. + };
  6407. + };
  6408. +
  6409. + tv1: tcon4@5731000 {
  6410. + compatible = "allwinner,tcon-tv";
  6411. + reg = <0x0 0x05731000 0x0 0x1000>;
  6412. + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  6413. + clocks = <&ccu CLK_EDP_TV>,
  6414. + <&ccu CLK_TCONTV1>;
  6415. + clock-names = "clk_tcon",
  6416. + "clk_bus_tcon";
  6417. + resets = <&ccu RST_BUS_TCONTV1>;
  6418. + reset-names = "rst_bus_tcon";
  6419. + top = <&vo1>;
  6420. + status = "disabled";
  6421. +
  6422. + ports {
  6423. + #address-cells = <1>;
  6424. + #size-cells = <0>;
  6425. + tcon4_in: port@0 {
  6426. + reg = <0>;
  6427. + #address-cells = <1>;
  6428. + #size-cells = <0>;
  6429. + tcon4_in_disp0: endpoint@0 {
  6430. + reg = <0>;
  6431. + remote-endpoint = <&disp0_out_tcon4>;
  6432. + };
  6433. + tcon4_in_disp1: endpoint@1 {
  6434. + reg = <1>;
  6435. + remote-endpoint = <&disp1_out_tcon4>;
  6436. + };
  6437. + };
  6438. + tcon4_out: port@1 {
  6439. + #address-cells = <1>;
  6440. + #size-cells = <0>;
  6441. + reg = <1>;
  6442. + tcon4_out_edp0: endpoint@0 {
  6443. + reg = <0>;
  6444. + remote-endpoint = <&edp0_in_tcon4>;
  6445. + };
  6446. + };
  6447. + };
  6448. + };
  6449. +
  6450. + edp0: edp0@5720000 {
  6451. + #sound-dai-cells = <0>; /* audio driver match method arg */
  6452. + compatible = "allwinner,drm-edp";
  6453. + reg = <0x0 0x05740000 0x0 0x1000>, /* edp base */
  6454. + <0x0 0x05760000 0x0 0x0020>; /* edp pad base */
  6455. + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  6456. + power-domains = <&pck600 PD_VO1>;
  6457. + clocks = <&ccu CLK_EDP_TV>, <&ccu CLK_EDP>;
  6458. + clock-names = "clk_edp", "clk_bus_edp";
  6459. + resets = <&ccu RST_BUS_EDP>;
  6460. + reset-names = "rst_bus_edp";
  6461. + assigned-clocks = <&ccu CLK_EDP_TV>;
  6462. + assigned-clock-parents = <&ccu CLK_PLL_VIDEO1_4X>;
  6463. + phys = <&combo0_dp>, <&aux_hpd_phy>;
  6464. + phy-names = "dp-phy", "aux-phy";
  6465. + sys = <&vo1>;
  6466. + pclk_limit = <200000>; /*KHz*/
  6467. + status = "disabled";
  6468. +
  6469. + ports {
  6470. + #address-cells = <1>;
  6471. + #size-cells = <0>;
  6472. + edp_in: port@0 {
  6473. + #address-cells = <1>;
  6474. + #size-cells = <0>;
  6475. + reg = <0>;
  6476. + edp0_in_tcon4: endpoint@0 {
  6477. + reg = <0>;
  6478. + remote-endpoint = <&tcon4_out_edp0>;
  6479. + };
  6480. + };
  6481. + edp_out: port@1 {
  6482. + #address-cells = <1>;
  6483. + #size-cells = <0>;
  6484. + reg = <1>;
  6485. + };
  6486. + };
  6487. + };
  6488. +
  6489. + hdmi0: hdmi0@5520000 {
  6490. + compatible = "allwinner,sunxi-hdmi";
  6491. + reg = <0x0 0x05520000 0x0 0x100000>;
  6492. + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  6493. + clocks = <&ccu CLK_HDMI_REF>,
  6494. + <&ccu CLK_HDMI>,
  6495. + <&ccu CLK_HDMI_SFR>,
  6496. + <&ccu CLK_HDCP_ESM>,
  6497. + <&rtc_ccu CLK_DCXO>;
  6498. + clock-names = "clk_cec",
  6499. + "clk_hdmi",
  6500. + "clk_hdmi_24M",
  6501. + "clk_hdcp",
  6502. + "clk_dcxo";
  6503. + resets = <&ccu RST_BUS_HDMI_SUB>,
  6504. + <&ccu RST_BUS_HDMI_MAIN>,
  6505. + <&ccu RST_BUS_HDMI_HDCP>;
  6506. + reset-names = "rst_bus_sub",
  6507. + "rst_bus_main",
  6508. + "rst_bus_hdcp";
  6509. + assigned-clocks = <&ccu CLK_HDMI>;
  6510. + assigned-clock-rates = <0>, <0>;
  6511. + power-domains = <&pck600 PD_VO1>;
  6512. +
  6513. + status = "disabled";
  6514. + ports {
  6515. + #address-cells = <1>;
  6516. + #size-cells = <0>;
  6517. + hdmi_in: port@0 {
  6518. + #address-cells = <1>;
  6519. + #size-cells = <0>;
  6520. + reg = <0>;
  6521. + hdmi0_in_tcon3: endpoint@0 {
  6522. + reg = <0>;
  6523. + remote-endpoint = <&tcon3_out_hdmi0>;
  6524. + };
  6525. + };
  6526. + };
  6527. + };
  6528. +
  6529. + ufs: ufs@04520000 {
  6530. + compatible = "allwinner,sunxi-ufs-v0";
  6531. + device_type = "ufs";
  6532. + reg = <0x0 0x4520000 0x0 0x10000>;
  6533. + interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>;
  6534. + clocks = <&sys24M>,
  6535. + <&ccu CLK_PLL_PERI0_200M>,
  6536. + <&ccu CLK_PLL_PERI0_300M>,
  6537. + <&ccu CLK_UFS_AXI>,
  6538. + <&ccu CLK_UFS>,
  6539. + <&ccu CLK_UFS_CFG>,
  6540. + <&ccu CLK_STORE_AHB_GATE>,
  6541. + <&ccu CLK_MBUS_STORE_GATE>,
  6542. + <&ccu CLK_MSI_LITE1>,
  6543. + <&rtc_ccu CLK_RTC_DCXO_WAKEUP>;
  6544. + clock-names = "osc24m","pll_periph","pll_periph_2",
  6545. + "axi_clk_gate","ahb_gate", "cfg_clk_gate",
  6546. + "store_ahb","store_mbus","msi_lite","dcxo_wakeup";
  6547. + resets = <&ccu RST_BUS_UFS_CORE>,
  6548. + <&ccu RST_BUS_UFS_PHY>,
  6549. + <&ccu RST_BUS_UFS_AXI>,
  6550. + <&ccu RST_BUS_UFS_AHB>;
  6551. + reset-names = "controller_rst", "phy_rst", "axi_rst", "ahb_rst";
  6552. + caps-wb-en;
  6553. + /*caps-crypto;*/
  6554. + status = "disabled";
  6555. + };
  6556. +
  6557. + // mmc0: mmc@4020000 {
  6558. + // compatible = "allwinner,sun55i-a523-mmc",
  6559. + // "allwinner,sun20i-d1-mmc";
  6560. + // reg = <0x0 0x04020000 0x0 0x1000>;
  6561. + // clocks = <&ccu CLK_BUS_SMHC0>, <&ccu CLK_SMHC0>,;
  6562. + // clock-names = "ahb", "mmc";
  6563. + // resets = <&ccu RST_BUS_SMHC0>;
  6564. + // reset-names = "ahb";
  6565. + // interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
  6566. + // pinctrl-names = "default";
  6567. + // pinctrl-0 = <&sdc0_pins_a &sdc0_pins_f>;
  6568. + // status = "disabled";
  6569. +
  6570. + // max-frequency = <150000000>;
  6571. + // cap-sd-highspeed;
  6572. + // cap-mmc-highspeed;
  6573. + // cap-sdio-irq;
  6574. + // #address-cells = <1>;
  6575. + // #size-cells = <0>;
  6576. + // };
  6577. +
  6578. + // mmc1: mmc@4021000 {
  6579. + // compatible = "allwinner,sun55i-a523-mmc",
  6580. + // "allwinner,sun20i-d1-mmc";
  6581. + // reg = <0x0 0x04021000 0x0 0x1000>;
  6582. + // clocks = <&ccu CLK_BUS_SMHC1>, <&ccu CLK_SMHC1>;
  6583. + // clock-names = "ahb", "mmc";
  6584. + // resets = <&ccu RST_BUS_SMHC1>;
  6585. + // reset-names = "ahb";
  6586. + // interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  6587. + // pinctrl-names = "default";
  6588. + // pinctrl-0 = <&sdc1_pins_a &sdc1_pins_c>;
  6589. + // status = "disabled";
  6590. +
  6591. + // max-frequency = <150000000>;
  6592. + // cap-sd-highspeed;
  6593. + // cap-mmc-highspeed;
  6594. + // cap-sdio-irq;
  6595. + // #address-cells = <1>;
  6596. + // #size-cells = <0>;
  6597. + // };
  6598. +
  6599. + // mmc2: mmc@4022000 {
  6600. + // compatible = "allwinner,sun55i-a523-mmc",
  6601. + // "allwinner,sun20i-d1-mmc";
  6602. + // reg = <0x0 0x04022000 0x0 0x1000>;
  6603. + // clocks = <&ccu CLK_BUS_SMHC2>, <&ccu CLK_SMHC2>;
  6604. + // clock-names = "ahb", "mmc";
  6605. + // resets = <&ccu RST_BUS_SMHC2>;
  6606. + // reset-names = "ahb";
  6607. + // interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
  6608. + // pinctrl-names = "default";
  6609. + // pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c &sdc2_pins_d>;
  6610. + // status = "disabled";
  6611. +
  6612. + // max-frequency = <150000000>;
  6613. + // cap-sd-highspeed;
  6614. + // cap-mmc-highspeed;
  6615. + // cap-sdio-irq;
  6616. + // #address-cells = <1>;
  6617. + // #size-cells = <0>;
  6618. + // };
  6619. +
  6620. + // mmc3: mmc@4023000 {
  6621. + // compatible = "allwinner,sun55i-a523-mmc",
  6622. + // "allwinner,sun20i-d1-mmc";
  6623. + // reg = <0x0 0x04023000 0x0 0x1000>;
  6624. + // clocks = <&ccu CLK_BUS_SMHC3>, <&ccu CLK_SMHC3>;
  6625. + // clock-names = "ahb", "mmc";
  6626. + // resets = <&ccu RST_BUS_SMHC3>;
  6627. + // reset-names = "ahb";
  6628. + // interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  6629. + // pinctrl-names = "default";
  6630. + // pinctrl-0 = <&sdc3_pins_a &sdc3_pins_c &sdc3_pins_d>;
  6631. + // status = "disabled";
  6632. +
  6633. + // max-frequency = <150000000>;
  6634. + // cap-sd-highspeed;
  6635. + // cap-mmc-highspeed;
  6636. + // cap-sdio-irq;
  6637. + // #address-cells = <1>;
  6638. + // #size-cells = <0>;
  6639. + // };
  6640. +
  6641. + sdc0: sdmmc@4020000 {
  6642. + compatible = "allwinner,sunxi-mmc-v5p3x";
  6643. + device_type = "sdc0";
  6644. + reg = <0x0 0x04020000 0x0 0x1000>;
  6645. + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
  6646. + clocks = <&sys24M>,
  6647. + <&ccu CLK_PLL_PERI1_400M>,
  6648. + <&ccu CLK_PLL_PERI1_300M>,
  6649. + <&ccu CLK_SMHC0>,
  6650. + <&ccu CLK_BUS_SMHC0>,
  6651. + <&ccu CLK_STORE_AHB_GATE>,
  6652. + <&ccu CLK_MBUS_STORE_GATE>,
  6653. + <&ccu CLK_MSI_LITE1>;
  6654. + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite";
  6655. + resets = <&ccu RST_BUS_SMHC0>;
  6656. + reset-names = "rst";
  6657. + pinctrl-names = "default","mmc_1v8","sleep","uart_jtag";
  6658. + pinctrl-0 = <&sdc0_pins_a &sdc0_pins_f>;
  6659. + pinctrl-1 = <&sdc0_pins_b &sdc0_pins_g>;
  6660. + pinctrl-2 = <&sdc0_pins_c>;
  6661. + pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>;
  6662. + max-frequency = <50000000>;
  6663. + bus-width = <4>;
  6664. + req-page-count = <2>;
  6665. + /*non-removable;*/
  6666. + /*broken-cd;*/
  6667. + /*cd-inverted*/
  6668. + /*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/
  6669. + /* vmmc-supply = <&reg_3p3v>;*/
  6670. + /* vqmc-supply = <&reg_3p3v>;*/
  6671. + /* vdmc-supply = <&reg_3p3v>;*/
  6672. + /*vmmc = "vcc-card";*/
  6673. + /*vqmc = "";*/
  6674. + /*vdmc = "";*/
  6675. + cap-sd-highspeed;
  6676. + cap-wait-while-busy;
  6677. + /*sd-uhs-sdr50;*/
  6678. + /*sd-uhs-ddr50;*/
  6679. + /*cap-sdio-irq;*/
  6680. + /*keep-power-in-suspend;*/
  6681. + /*ignore-pm-notify;*/
  6682. + /*sunxi-power-save-mode;*/
  6683. + /*sunxi-dly-400k = <1 0 0 0>; */
  6684. + /*sunxi-dly-26M = <1 0 0 0>;*/
  6685. + /*sunxi-dly-52M = <1 0 0 0>;*/
  6686. + /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
  6687. + /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
  6688. + /*sunxi-dly-104M = <1 0 0 0>;*/
  6689. + /*sunxi-dly-208M = <1 0 0 0>;*/
  6690. + /*sunxi-dly-104M-ddr = <1 0 0 0>;*/
  6691. + /*sunxi-dly-208M-ddr = <1 0 0 0>;*/
  6692. + ctl-spec-caps = <0x428>;
  6693. + status = "okay";
  6694. + };
  6695. +
  6696. + sdc1: sdmmc@4021000 {
  6697. + compatible = "allwinner,sunxi-mmc-v5p3x";
  6698. + device_type = "sdc1";
  6699. + reg = <0x0 0x04021000 0x0 0x1000>;
  6700. + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  6701. + clocks = <&sys24M>,
  6702. + <&ccu CLK_PLL_PERI1_400M>,
  6703. + <&ccu CLK_PLL_PERI1_300M>,
  6704. + <&ccu CLK_SMHC1>,
  6705. + <&ccu CLK_BUS_SMHC1>,
  6706. + <&ccu CLK_STORE_AHB_GATE>,
  6707. + <&ccu CLK_MBUS_STORE_GATE>,
  6708. + <&ccu CLK_MSI_LITE1>;
  6709. + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite";
  6710. + resets = <&ccu RST_BUS_SMHC1>;
  6711. + reset-names = "rst";
  6712. + pinctrl-names = "default","sleep";
  6713. + pinctrl-0 = <&sdc1_pins_a &sdc1_pins_c>;
  6714. + pinctrl-1 = <&sdc1_pins_b>;
  6715. + max-frequency = <50000000>;
  6716. + bus-width = <4>;
  6717. + /*broken-cd;*/
  6718. + /*cd-inverted*/
  6719. + /*cd-gpios = <&pio PG 6 6 1 2 0>;*/
  6720. + /* vmmc-supply = <&reg_3p3v>;*/
  6721. + /* vqmc-supply = <&reg_3p3v>;*/
  6722. + /* vdmc-supply = <&reg_3p3v>;*/
  6723. + /*vmmc = "vcc-card";*/
  6724. + /*vqmc = "";*/
  6725. + /*vdmc = "";*/
  6726. + cap-sd-highspeed;
  6727. + cap-sdio-irq;
  6728. + ignore-pm-notify;
  6729. + /*sd-uhs-sdr50;*/
  6730. + /*sd-uhs-ddr50;*/
  6731. + /*sd-uhs-sdr104;*/
  6732. + /*cap-sdio-irq;*/
  6733. + keep-power-in-suspend;
  6734. + /*ignore-pm-notify;*/
  6735. + /*sunxi-power-save-mode;*/
  6736. + /*sunxi-dly-400k = <0xff 0xff 0xff 0xff 0xff 0xff>; */
  6737. + /*sunxi-dly-26M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6738. + /*sunxi-dly-52M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6739. + /*sunxi-dly-52M-ddr4 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6740. + /*sunxi-dly-52M-ddr8 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6741. + /*sunxi-dly-104M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6742. + /*sunxi-dly-208M = <0xff 0xff 0xff 0xff 0xff 0xff> ;*/
  6743. + /*sunxi-dly-104M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6744. + /*sunxi-dly-208M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/
  6745. + sunxi-dly-208M = <0xff 0x1 0xff 0xff 0xff 0xff>;
  6746. + execute_tuning_in_kernel;
  6747. + ctl-spec-caps = <0x428>;
  6748. + status = "disabled";
  6749. + };
  6750. +
  6751. + sdc2: sdmmc@4022000 {
  6752. + compatible = "allwinner,sunxi-mmc-v4p6x";
  6753. + device_type = "sdc2";
  6754. + reg = <0x0 0x04022000 0x0 0x1000>;
  6755. + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
  6756. + clocks = <&sys24M>,
  6757. + <&ccu CLK_PLL_PERI1_800M>,
  6758. + <&ccu CLK_PLL_PERI1_600M>,
  6759. + <&ccu CLK_SMHC2>,
  6760. + <&ccu CLK_BUS_SMHC2>,
  6761. + <&ccu CLK_STORE_AHB_GATE>,
  6762. + <&ccu CLK_MBUS_STORE_GATE>,
  6763. + <&ccu CLK_MSI_LITE1>;
  6764. + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite";
  6765. + resets = <&ccu RST_BUS_SMHC2>;
  6766. + reset-names = "rst";
  6767. + pinctrl-names = "default","sleep";
  6768. + pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c &sdc2_pins_d>;
  6769. + pinctrl-1 = <&sdc2_pins_b>;
  6770. + bus-width = <8>;
  6771. + req-page-count = <2>;
  6772. + cap-mmc-highspeed;
  6773. + cap-cmd23;
  6774. + mmc-cache-ctrl;
  6775. + non-removable;
  6776. + /*max-frequency = <200000000>;*/
  6777. + max-frequency = <50000000>;
  6778. + cap-erase;
  6779. + mmc-high-capacity-erase-size;
  6780. + no-sdio;
  6781. + no-sd;
  6782. + /*-- speed mode --*/
  6783. + /*sm0: DS26_SDR12*/
  6784. + /*sm1: HSSDR52_SDR25*/
  6785. + /*sm2: HSDDR52_DDR50*/
  6786. + /*sm3: HS200_SDR104*/
  6787. + /*sm4: HS400*/
  6788. + /*-- frequency point --*/
  6789. + /*f0: CLK_400K*/
  6790. + /*f1: CLK_25M*/
  6791. + /*f2: CLK_50M*/
  6792. + /*f3: CLK_100M*/
  6793. + /*f4: CLK_150M*/
  6794. + /*f5: CLK_200M*/
  6795. + ctl-spec-caps = <0x328>;
  6796. + sdc_tm4_sm0_freq0 = <0>;
  6797. + sdc_tm4_sm0_freq1 = <0>;
  6798. + sdc_tm4_sm1_freq0 = <0x00000000>;
  6799. + sdc_tm4_sm1_freq1 = <0>;
  6800. + sdc_tm4_sm2_freq0 = <0x00000000>;
  6801. + sdc_tm4_sm2_freq1 = <0>;
  6802. + sdc_tm4_sm3_freq0 = <0x05000000>;
  6803. + sdc_tm4_sm3_freq1 = <0x00000005>;
  6804. + sdc_tm4_sm4_freq0 = <0x00050000>;
  6805. + sdc_tm4_sm4_freq1 = <0x00000004>;
  6806. + sdc_tm4_sm4_freq0_cmd = <0>;
  6807. + sdc_tm4_sm4_freq1_cmd = <0>;
  6808. +
  6809. + /*vmmc-supply = <&reg_3p3v>;*/
  6810. + /*vqmc-supply = <&reg_3p3v>;*/
  6811. + /*vdmc-supply = <&reg_3p3v>;*/
  6812. + /*vmmc = "vcc-card";*/
  6813. + /*vqmc = "";*/
  6814. + /*vdmc = "";*/
  6815. + /*sunxi-power-save-mode;*/
  6816. + status = "disabled";
  6817. + };
  6818. +
  6819. + sdc3: sdmmc@4023000 {
  6820. + compatible = "allwinner,sunxi-mmc-v5p6x";
  6821. + device_type = "sdc3";
  6822. + reg = <0x0 0x04023000 0x0 0x1000>;
  6823. + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  6824. + clocks = <&sys24M>,
  6825. + <&ccu CLK_PLL_PERI1_800M>,
  6826. + <&ccu CLK_PLL_PERI1_600M>,
  6827. + <&ccu CLK_SMHC3>,
  6828. + <&ccu CLK_BUS_SMHC3>,
  6829. + <&ccu CLK_MBUS_STORE_GATE>,
  6830. + <&ccu CLK_MSI_LITE1>;
  6831. + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_mbus","mmc_msi_lite";
  6832. + resets = <&ccu RST_BUS_SMHC3>;
  6833. + reset-names = "rst";
  6834. + pinctrl-names = "default","sleep";
  6835. + pinctrl-0 = <&sdc3_pins_a &sdc3_pins_c &sdc3_pins_d>;
  6836. + pinctrl-1 = <&sdc3_pins_b>;
  6837. + bus-width = <8>;
  6838. + req-page-count = <2>;
  6839. + cap-mmc-highspeed;
  6840. + cap-cmd23;
  6841. + mmc-cache-ctrl;
  6842. + non-removable;
  6843. + /*max-frequency = <200000000>;*/
  6844. + max-frequency = <50000000>;
  6845. + cap-erase;
  6846. + mmc-high-capacity-erase-size;
  6847. + no-sdio;
  6848. + no-sd;
  6849. + /*-- speed mode --*/
  6850. + /*sm0: DS26_SDR12*/
  6851. + /*sm1: HSSDR52_SDR25*/
  6852. + /*sm2: HSDDR52_DDR50*/
  6853. + /*sm3: HS200_SDR104*/
  6854. + /*sm4: HS400*/
  6855. + /*-- frequency point --*/
  6856. + /*f0: CLK_400K*/
  6857. + /*f1: CLK_25M*/
  6858. + /*f2: CLK_50M*/
  6859. + /*f3: CLK_100M*/
  6860. + /*f4: CLK_150M*/
  6861. + /*f5: CLK_200M*/
  6862. + ctl-spec-caps = <0x328>;
  6863. + sdc_tm4_sm0_freq0 = <0>;
  6864. + sdc_tm4_sm0_freq1 = <0>;
  6865. + sdc_tm4_sm1_freq0 = <0x00000000>;
  6866. + sdc_tm4_sm1_freq1 = <0>;
  6867. + sdc_tm4_sm2_freq0 = <0x00000000>;
  6868. + sdc_tm4_sm2_freq1 = <0>;
  6869. + sdc_tm4_sm3_freq0 = <0x05000000>;
  6870. + sdc_tm4_sm3_freq1 = <0x00000005>;
  6871. + sdc_tm4_sm4_freq0 = <0x00050000>;
  6872. + sdc_tm4_sm4_freq1 = <0x00000004>;
  6873. + sdc_tm4_sm4_freq0_cmd = <0>;
  6874. + sdc_tm4_sm4_freq1_cmd = <0>;
  6875. +
  6876. + /*vmmc-supply = <&reg_3p3v>;*/
  6877. + /*vqmc-supply = <&reg_3p3v>;*/
  6878. + /*vdmc-supply = <&reg_3p3v>;*/
  6879. + /*vmmc = "vcc-card";*/
  6880. + /*vqmc = "";*/
  6881. + /*vdmc = "";*/
  6882. + /*sunxi-power-save-mode;*/
  6883. + status = "disabled";
  6884. + };
  6885. +
  6886. + gpu: gpu@1800000 {
  6887. + compatible = "img,img-bxm-4-64", "img,img-rogue";
  6888. + reg = <0x0 0x01800000 0x0 0x8ffff>;
  6889. + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  6890. + clocks = <&ccu CLK_GPU0>,
  6891. + <&ccu CLK_PLL_GPU0>,
  6892. + <&ccu CLK_BUS_GPU0>;
  6893. + clock-names = "core", "mem", "sys";
  6894. + power-domains = <&pck600 PD_GPU_CORE>,
  6895. + <&pck600 PD_GPU_TOP>;
  6896. + power-domain-names = "a", "b";
  6897. + resets = <&ccu RST_BUS_GPU0>;
  6898. + operating-points-v2 = <&gpu_opp_table>;
  6899. + #cooling-cells = <2>;
  6900. + };
  6901. +
  6902. + // gpu: gpu@1800000 {
  6903. + // device_type = "gpu";
  6904. + // compatible = "img,gpu";
  6905. + // reg = <0x0 0x01800000 0x0 0x8ffff>;
  6906. + // interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
  6907. + // <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  6908. + // interrupt-names = "IRQGPU", "IRQGPUDVFS";
  6909. + // clocks = <&ccu CLK_PLL_GPU0>,
  6910. + // <&ccu CLK_GPU0>,
  6911. + // <&ccu CLK_BUS_GPU0>,
  6912. + // <&ccu CLK_PLL_PERI0_800M>,
  6913. + // <&ccu CLK_PLL_PERI0_600M>,
  6914. + // <&ccu CLK_PLL_PERI0_400M>,
  6915. + // <&ccu CLK_PLL_PERI0_300M>,
  6916. + // <&ccu CLK_PLL_PERI0_200M>;
  6917. + // clock-names = "clk_parent", "clk", "clk_bus",
  6918. + // "clk_800", "clk_600", "clk_400",
  6919. + // "clk_300", "clk_200";
  6920. + // resets = <&ccu RST_BUS_GPU0>;
  6921. + // reset-names = "reset_bus";
  6922. + // // power-domains = <&pck600 PD_GPU_TOP>;
  6923. + // operating-points-v2 = <&gpu_opp_table>;
  6924. + // #cooling-cells = <2>;
  6925. + // };
  6926. +
  6927. + gpu_opp_table: gpu-opp-table {
  6928. + compatible = "allwinner, img-operating-points";
  6929. +
  6930. + /*opp@300000000 {
  6931. + opp-hz = /bits/ 64 <300000000>;
  6932. + opp-microvolt = <800000>;
  6933. + opp-microvolt-vfdefault = <800000>;
  6934. + opp-microvolt-vf0000 = <800000>;
  6935. + opp-microvolt-vf0100 = <800000>;
  6936. + opp-microvolt-vf0200 = <800000>;
  6937. + opp-microvolt-vf0201 = <800000>;
  6938. + opp-microvolt-vf0202 = <800000>;
  6939. + opp-microvolt-vf0302 = <800000>;
  6940. + opp-microvolt-vf0402 = <800000>;
  6941. + opp-microvolt-vf0502 = <800000>;
  6942. + opp-microvolt-vf0602 = <800000>;
  6943. + opp-microvolt-vf0300 = <800000>;
  6944. + opp-microvolt-vf0400 = <800000>;
  6945. + opp-microvolt-vf0500 = <800000>;
  6946. + opp-microvolt-vf0600 = <800000>;
  6947. + opp-microvolt-vf1400 = <800000>;
  6948. + opp-microvolt-vf1500 = <800000>;
  6949. + };*/
  6950. +
  6951. + opp@400000000 {
  6952. + opp-hz = /bits/ 64 <400000000>;
  6953. + opp-microvolt = <800000>;
  6954. + opp-microvolt-vfdefault = <800000>;
  6955. + opp-microvolt-vf0000 = <800000>;
  6956. + opp-microvolt-vf0100 = <800000>;
  6957. + opp-microvolt-vf0101 = <800000>;
  6958. + opp-microvolt-vf0200 = <800000>;
  6959. + opp-microvolt-vf0201 = <800000>;
  6960. + opp-microvolt-vf0202 = <800000>;
  6961. + opp-microvolt-vf0302 = <800000>;
  6962. + opp-microvolt-vf0402 = <800000>;
  6963. + opp-microvolt-vf0502 = <800000>;
  6964. + opp-microvolt-vf0602 = <800000>;
  6965. + opp-microvolt-vf0300 = <800000>;
  6966. + opp-microvolt-vf0400 = <800000>;
  6967. + opp-microvolt-vf0500 = <800000>;
  6968. + opp-microvolt-vf0600 = <800000>;
  6969. + opp-microvolt-vf1400 = <800000>;
  6970. + opp-microvolt-vf1500 = <800000>;
  6971. + };
  6972. +
  6973. + opp@600000000 {
  6974. + opp-hz = /bits/ 64 <600000000>;
  6975. + opp-microvolt = <800000>;
  6976. + opp-microvolt-vfdefault = <800000>;
  6977. + opp-microvolt-vf0000 = <800000>;
  6978. + opp-microvolt-vf0100 = <800000>;
  6979. + opp-microvolt-vf0101 = <800000>;
  6980. + opp-microvolt-vf0200 = <800000>;
  6981. + opp-microvolt-vf0201 = <800000>;
  6982. + opp-microvolt-vf0202 = <800000>;
  6983. + opp-microvolt-vf0302 = <800000>;
  6984. + opp-microvolt-vf0402 = <800000>;
  6985. + opp-microvolt-vf0502 = <800000>;
  6986. + opp-microvolt-vf0602 = <800000>;
  6987. + opp-microvolt-vf0300 = <800000>;
  6988. + opp-microvolt-vf0400 = <800000>;
  6989. + opp-microvolt-vf0500 = <800000>;
  6990. + opp-microvolt-vf0600 = <800000>;
  6991. + opp-microvolt-vf1400 = <800000>;
  6992. + opp-microvolt-vf1500 = <800000>;
  6993. + };
  6994. +
  6995. + opp@800000000 {
  6996. + opp-hz = /bits/ 64 <800000000>;
  6997. + opp-microvolt = <840000>;
  6998. + opp-microvolt-vfdefault = <840000>;
  6999. + opp-microvolt-vf0000 = <840000>;
  7000. + opp-microvolt-vf0100 = <840000>;
  7001. + opp-microvolt-vf0101 = <800000>;
  7002. + opp-microvolt-vf0200 = <840000>;
  7003. + opp-microvolt-vf0201 = <800000>;
  7004. + opp-microvolt-vf0202 = <800000>;
  7005. + opp-microvolt-vf0302 = <800000>;
  7006. + opp-microvolt-vf0402 = <800000>;
  7007. + opp-microvolt-vf0502 = <800000>;
  7008. + opp-microvolt-vf0602 = <800000>;
  7009. + opp-microvolt-vf0300 = <820000>;
  7010. + opp-microvolt-vf0400 = <800000>;
  7011. + opp-microvolt-vf0500 = <800000>;
  7012. + opp-microvolt-vf0600 = <800000>;
  7013. + opp-microvolt-vf1400 = <800000>;
  7014. + opp-microvolt-vf1500 = <800000>;
  7015. + };
  7016. +
  7017. + opp@1008000000 {
  7018. + opp-hz = /bits/ 64 <1008000000>;
  7019. + opp-microvolt = <960000>;
  7020. + opp-microvolt-vfdefault = <960000>;
  7021. + opp-microvolt-vf0000 = <960000>;
  7022. + opp-microvolt-vf0100 = <960000>;
  7023. + opp-microvolt-vf0101 = <920000>;
  7024. + opp-microvolt-vf0200 = <960000>;
  7025. + opp-microvolt-vf0201 = <880000>;
  7026. + opp-microvolt-vf0202 = <920000>;
  7027. + opp-microvolt-vf0302 = <920000>;
  7028. + opp-microvolt-vf0402 = <900000>;
  7029. + opp-microvolt-vf0502 = <880000>;
  7030. + opp-microvolt-vf0602 = <860000>;
  7031. + opp-microvolt-vf0300 = <940000>;
  7032. + opp-microvolt-vf0400 = <900000>;
  7033. + opp-microvolt-vf0500 = <880000>;
  7034. + opp-microvolt-vf0600 = <920000>;
  7035. + opp-microvolt-vf1400 = <880000>;
  7036. + opp-microvolt-vf1500 = <860000>;
  7037. + };
  7038. + };
  7039. +
  7040. + hdmi_codec: hdmi_codec {
  7041. + #sound-dai-cells = <0>;
  7042. + compatible = "allwinner,sunxi-snd-codec-hdmi";
  7043. + status = "disabled";
  7044. + };
  7045. +
  7046. + /* audio dirver module -> I2S/PCM */
  7047. + i2s0_plat:i2s0_plat@2532000 {
  7048. + #sound-dai-cells = <0>;
  7049. + compatible = "allwinner,sunxi-snd-plat-i2s";
  7050. + reg = <0x0 0x02532000 0x0 0xA0>;
  7051. + resets = <&ccu RST_BUS_I2SPCM0>;
  7052. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7053. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7054. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7055. + <&ccu CLK_PLL_PERI0_200M>,
  7056. + <&ccu CLK_BUS_I2SPCM0>,
  7057. + <&ccu CLK_I2SPCM0>;
  7058. + clock-names = "clk_pll_audio0_4x",
  7059. + "clk_pll_audio1_div2",
  7060. + "clk_pll_audio1_div5",
  7061. + "clk_i2s_asrc",
  7062. + "clk_bus_i2s",
  7063. + "clk_i2s";
  7064. + dmas = <&dma 3>, <&dma 3>;
  7065. + dma-names = "tx", "rx";
  7066. + playback-cma = <128>;
  7067. + capture-cma = <128>;
  7068. + tx-fifo-size = <128>;
  7069. + rx-fifo-size = <128>;
  7070. + status = "disabled";
  7071. + };
  7072. +
  7073. + i2s0_mach:i2s0_mach{
  7074. + compatible = "allwinner,sunxi-snd-mach";
  7075. + soundcard-mach,name = "sndi2s0";
  7076. + soundcard-mach,format = "i2s";
  7077. + soundcard-mach,slot-num = <2>;
  7078. + soundcard-mach,slot-width = <32>;
  7079. + status = "disabled";
  7080. + soundcard-mach,cpu {
  7081. + sound-dai = <&i2s0_plat>;
  7082. + };
  7083. + soundcard-mach,codec {
  7084. + };
  7085. + };
  7086. +
  7087. + i2s1_plat:i2s1_plat@2533000 {
  7088. + #sound-dai-cells = <0>;
  7089. + compatible = "allwinner,sunxi-snd-plat-i2s";
  7090. + reg = <0x0 0x02533000 0x0 0xA0>;
  7091. + resets = <&ccu RST_BUS_I2SPCM1>;
  7092. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7093. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7094. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7095. + <&ccu CLK_PLL_PERI0_200M>,
  7096. + <&ccu CLK_BUS_I2SPCM1>,
  7097. + <&ccu CLK_I2SPCM1>;
  7098. + clock-names = "clk_pll_audio0_4x",
  7099. + "clk_pll_audio1_div2",
  7100. + "clk_pll_audio1_div5",
  7101. + "clk_i2s_asrc",
  7102. + "clk_bus_i2s",
  7103. + "clk_i2s";
  7104. + dmas = <&dma 4>, <&dma 4>;
  7105. + dma-names = "tx", "rx";
  7106. + playback-cma = <128>;
  7107. + capture-cma = <128>;
  7108. + tx-fifo-size = <128>;
  7109. + rx-fifo-size = <128>;
  7110. + status = "disabled";
  7111. + };
  7112. +
  7113. + i2s1_mach:i2s1_mach{
  7114. + compatible = "allwinner,sunxi-snd-mach";
  7115. + soundcard-mach,name = "sndi2s1";
  7116. + soundcard-mach,format = "i2s";
  7117. + soundcard-mach,slot-num = <2>;
  7118. + soundcard-mach,slot-width = <32>;
  7119. + status = "disabled";
  7120. + soundcard-mach,cpu {
  7121. + sound-dai = <&i2s1_plat>;
  7122. + };
  7123. + soundcard-mach,codec {
  7124. + };
  7125. + };
  7126. +
  7127. + i2s2_plat:i2s2_plat@2534000 {
  7128. + #sound-dai-cells = <0>;
  7129. + compatible = "allwinner,sunxi-snd-plat-i2s";
  7130. + reg = <0x0 0x02534000 0x0 0xA0>;
  7131. + resets = <&ccu RST_BUS_I2SPCM2>;
  7132. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7133. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7134. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7135. + <&ccu CLK_PLL_PERI0_200M>,
  7136. + <&ccu CLK_BUS_I2SPCM2>,
  7137. + <&ccu CLK_I2SPCM2>;
  7138. + clock-names = "clk_pll_audio0_4x",
  7139. + "clk_pll_audio1_div2",
  7140. + "clk_pll_audio1_div5",
  7141. + "clk_i2s_asrc",
  7142. + "clk_bus_i2s",
  7143. + "clk_i2s";
  7144. + dmas = <&dma 5>, <&dma 5>;
  7145. + dma-names = "tx", "rx";
  7146. + playback-cma = <128>;
  7147. + capture-cma = <128>;
  7148. + tx-fifo-size = <128>;
  7149. + rx-fifo-size = <128>;
  7150. + status = "disabled";
  7151. + };
  7152. +
  7153. + i2s2_mach:i2s2_mach{
  7154. + compatible = "allwinner,sunxi-snd-mach";
  7155. + soundcard-mach,name = "sndi2s2";
  7156. + soundcard-mach,format = "i2s";
  7157. + soundcard-mach,slot-num = <2>;
  7158. + soundcard-mach,slot-width = <32>;
  7159. + status = "disabled";
  7160. + soundcard-mach,cpu {
  7161. + sound-dai = <&i2s2_plat>;
  7162. + };
  7163. + soundcard-mach,codec {
  7164. + };
  7165. + };
  7166. +
  7167. + i2s3_plat:i2s3_plat@2535000 {
  7168. + #sound-dai-cells = <0>;
  7169. + compatible = "allwinner,sunxi-snd-plat-i2s";
  7170. + reg = <0x0 0x02535000 0x0 0xA0>;
  7171. + resets = <&ccu RST_BUS_I2SPCM3>;
  7172. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7173. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7174. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7175. + <&ccu CLK_PLL_PERI0_200M>,
  7176. + <&ccu CLK_BUS_I2SPCM3>,
  7177. + <&ccu CLK_I2SPCM3>;
  7178. + clock-names = "clk_pll_audio0_4x",
  7179. + "clk_pll_audio1_div2",
  7180. + "clk_pll_audio1_div5",
  7181. + "clk_i2s_asrc",
  7182. + "clk_bus_i2s",
  7183. + "clk_i2s";
  7184. + dmas = <&dma 6>, <&dma 6>;
  7185. + dma-names = "tx", "rx";
  7186. + playback-cma = <128>;
  7187. + capture-cma = <128>;
  7188. + tx-fifo-size = <128>;
  7189. + rx-fifo-size = <128>;
  7190. + status = "disabled";
  7191. + };
  7192. +
  7193. + i2s3_mach:i2s3_mach{
  7194. + compatible = "allwinner,sunxi-snd-mach";
  7195. + /* card name. hdmi: "sndhdmi"; edp: "sndedp" */
  7196. + soundcard-mach,name = "sndhdmi";
  7197. + soundcard-mach,format = "i2s";
  7198. + soundcard-mach,slot-num = <2>;
  7199. + soundcard-mach,slot-width = <32>;
  7200. + status = "disabled";
  7201. + soundcard-mach,cpu {
  7202. + sound-dai = <&i2s3_plat>;
  7203. + };
  7204. + soundcard-mach,codec {
  7205. + };
  7206. + };
  7207. +
  7208. + i2s4_plat:i2s4_plat@2536000 {
  7209. + #sound-dai-cells = <0>;
  7210. + compatible = "allwinner,sunxi-snd-plat-i2s";
  7211. + reg = <0x0 0x02536000 0x0 0xA0>;
  7212. + resets = <&ccu RST_BUS_I2SPCM4>;
  7213. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7214. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7215. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7216. + <&ccu CLK_PLL_PERI0_200M>,
  7217. + <&ccu CLK_BUS_I2SPCM4>,
  7218. + <&ccu CLK_I2SPCM4>;
  7219. + clock-names = "clk_pll_audio0_4x",
  7220. + "clk_pll_audio1_div2",
  7221. + "clk_pll_audio1_div5",
  7222. + "clk_i2s_asrc",
  7223. + "clk_bus_i2s",
  7224. + "clk_i2s";
  7225. + dmas = <&dma 7>, <&dma 7>;
  7226. + dma-names = "tx", "rx";
  7227. + playback-cma = <128>;
  7228. + capture-cma = <128>;
  7229. + tx-fifo-size = <128>;
  7230. + rx-fifo-size = <128>;
  7231. + status = "disabled";
  7232. + };
  7233. +
  7234. + i2s4_mach:i2s4_mach{
  7235. + compatible = "allwinner,sunxi-snd-mach";
  7236. + soundcard-mach,name = "sndi2s4";
  7237. + soundcard-mach,format = "i2s";
  7238. + soundcard-mach,slot-num = <2>;
  7239. + soundcard-mach,slot-width = <32>;
  7240. + status = "disabled";
  7241. + soundcard-mach,cpu {
  7242. + sound-dai = <&i2s4_plat>;
  7243. + };
  7244. + soundcard-mach,codec {
  7245. + };
  7246. + };
  7247. +
  7248. + /* audio dirver module -> owa */
  7249. + owa_plat:owa_plat@2537000 {
  7250. + #sound-dai-cells = <0>;
  7251. + compatible = "allwinner,sunxi-snd-plat-owa";
  7252. + reg = <0x0 0x02537000 0x0 0x58>;
  7253. + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  7254. + resets = <&ccu RST_BUS_OWA>;
  7255. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7256. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7257. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7258. + <&ccu CLK_BUS_OWA>,
  7259. + <&ccu CLK_OWA_TX>,
  7260. + <&ccu CLK_OWA_RX>;
  7261. + clock-names = "clk_pll_audio0_4x",
  7262. + "clk_pll_audio1_div2",
  7263. + "clk_pll_audio1_div5",
  7264. + "clk_bus_owa",
  7265. + "clk_owa_tx",
  7266. + "clk_owa_rx";
  7267. + dmas = <&dma 2>, <&dma 2>;
  7268. + dma-names = "tx", "rx";
  7269. + playback-cma = <128>;
  7270. + capture-cma = <128>;
  7271. + tx-fifo-size = <128>;
  7272. + rx-fifo-size = <128>;
  7273. + status = "disabled";
  7274. + };
  7275. +
  7276. + owa_mach:owa_mach {
  7277. + compatible = "allwinner,sunxi-snd-mach";
  7278. + soundcard-mach,name = "sndowa";
  7279. + status = "disabled";
  7280. + soundcard-mach,cpu {
  7281. + sound-dai = <&owa_plat>;
  7282. + };
  7283. + soundcard-mach,codec {
  7284. + };
  7285. + };
  7286. +
  7287. + /* audio dirver module -> dmic */
  7288. + dmic_plat:dmic_plat@2531000 {
  7289. + #sound-dai-cells = <0>;
  7290. + compatible = "allwinner,sunxi-snd-plat-dmic";
  7291. + reg = <0x0 0x02531000 0x0 0x50>;
  7292. + resets = <&ccu RST_BUS_DMIC>;
  7293. + clocks = <&ccu CLK_PLL_AUDIO0_4X>,
  7294. + <&ccu CLK_PLL_AUDIO1_DIV2>,
  7295. + <&ccu CLK_PLL_AUDIO1_DIV5>,
  7296. + <&ccu CLK_BUS_DMIC>,
  7297. + <&ccu CLK_DMIC>;
  7298. + clock-names = "clk_pll_audio0_4x",
  7299. + "clk_pll_audio1_div2",
  7300. + "clk_pll_audio1_div5",
  7301. + "clk_bus_dmic",
  7302. + "clk_dmic";
  7303. + dmas = <&dma 9>;
  7304. + dma-names = "rx";
  7305. + capture-cma = <128>;
  7306. + rx-fifo-size = <128>;
  7307. + status = "disabled";
  7308. + };
  7309. +
  7310. + dmic_mach:dmic_mach{
  7311. + compatible = "allwinner,sunxi-snd-mach";
  7312. + soundcard-mach,name = "snddmic";
  7313. + soundcard-mach,capture-only;
  7314. + status = "disabled";
  7315. + soundcard-mach,cpu {
  7316. + sound-dai = <&dmic_plat>;
  7317. + };
  7318. + soundcard-mach,codec {
  7319. + };
  7320. + };
  7321. +
  7322. + pcie_rc: pcie@6000000 {
  7323. + #address-cells = <3>;
  7324. + #size-cells = <2>;
  7325. + compatible = "allwinner,sunxi-pcie-v300-rc";
  7326. + bus-range = <0x0 0xff>;
  7327. + reg = <0 0x06000000 0 0x480000>;
  7328. + reg-names = "dbi";
  7329. + device_type = "pci";
  7330. + ranges = <0x00000800 0 0x20000000 0x0 0x20000000 0 0x01000000
  7331. + 0x81000000 0 0x21000000 0x0 0x21000000 0 0x01000000
  7332. + 0x82000000 0 0x22000000 0x0 0x22000000 0 0x06000000>;
  7333. + num-lanes = <1>;
  7334. + phys = <&combo1_pcie>;
  7335. + phy-names = "pcie-phy";
  7336. + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  7337. + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  7338. + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  7339. + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  7340. + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  7341. + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
  7342. + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  7343. + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  7344. + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  7345. + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  7346. + interrupt-names = "sii", "msi", "edma-w0", "edma-w1", "edma-w2", "edma-w3",
  7347. + "edma-r0", "edma-r1", "edma-r2", "edma-r3";
  7348. + #interrupt-cells = <1>;
  7349. + interrupt-map-mask = <0 0 0 7>;
  7350. + interrupt-map = <0 0 0 1 &pcie_intc 0>,
  7351. + <0 0 0 2 &pcie_intc 1>,
  7352. + <0 0 0 3 &pcie_intc 2>,
  7353. + <0 0 0 4 &pcie_intc 3>;
  7354. + num-edma = <4>;
  7355. + max-link-speed = <3>;
  7356. + num-ib-windows = <16>;
  7357. + num-ob-windows = <16>;
  7358. + linux,pci-domain = <0>;
  7359. + power-domains = <&pck600 PD_PCIE>;
  7360. + clocks = <&ccu CLK_PCIE0_AUX>, <&ccu CLK_PCIE0_AXI_SLV>, <&ccu CLK_ITS_PCIE0_A>;
  7361. + clock-names = "pclk_aux", "pclk_slv", "its";
  7362. + resets = <&ccu RST_BUS_PCIE0>, <&ccu RST_BUS_PCIE0_PWRUP>, <&ccu RST_BUS_ITS_PCIE0>;
  7363. + reset-names = "pclk_rst", "pwrup_rst", "its";
  7364. + busno = <0>;
  7365. + status = "disabled";
  7366. +
  7367. + pcie_intc: legacy-interrupt-controller {
  7368. + interrupt-controller;
  7369. + #address-cells = <0>;
  7370. + #interrupt-cells = <1>;
  7371. + };
  7372. + };
  7373. + };
  7374. +};
  7375. diff --git a/include/dt-bindings/clock/sun20iw5-aon-ccu.h b/include/dt-bindings/clock/sun20iw5-aon-ccu.h
  7376. new file mode 100644
  7377. index 000000000000..d05d79a63354
  7378. --- /dev/null
  7379. +++ b/include/dt-bindings/clock/sun20iw5-aon-ccu.h
  7380. @@ -0,0 +1,43 @@
  7381. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7382. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7383. +/*
  7384. + * Copyright (C) 2023 [email protected]
  7385. + */
  7386. +
  7387. +#ifndef _DT_BINDINGS_CLK_SUN20IW5_AON_H_
  7388. +#define _DT_BINDINGS_CLK_SUN20IW5_AON_H_
  7389. +
  7390. +#define CLK_PLL_CPU 0
  7391. +#define CLK_PLL_DDR 1
  7392. +#define CLK_PLL_PERI_PARENT 2
  7393. +#define CLK_PLL_PERI_CKO_1536M 3
  7394. +#define CLK_PLL_PERI_CKO_1024M 4
  7395. +#define CLK_PLL_PERI_CKO_768M 5
  7396. +#define CLK_PLL_PERI_CKO_614M 6
  7397. +#define CLK_PLL_PERI_CKO_512M 7
  7398. +#define CLK_PLL_PERI_CKO_384M 8
  7399. +#define CLK_PLL_PERI_CKO_341M 9
  7400. +#define CLK_PLL_PERI_CKO_307M 10
  7401. +#define CLK_PLL_PERI_CKO_236M 11
  7402. +#define CLK_PLL_PERI_CKO_219M 12
  7403. +#define CLK_PLL_PERI_CKO_192M 13
  7404. +#define CLK_PLL_PERI_CKO_118M 14
  7405. +#define CLK_PLL_PERI_CKO_96M 15
  7406. +#define CLK_PLL_PERI_CKO_48M 16
  7407. +#define CLK_PLL_PERI_CKO_24M 17
  7408. +#define CLK_PLL_PERI_CKO_12M 18
  7409. +#define CLK_PLL_VIDEO0_4X 19
  7410. +#define CLK_PLL_CSI_4X 20
  7411. +#define CLK_DCXO 21
  7412. +#define CLK_AHB 22
  7413. +#define CLK_APB0 23
  7414. +#define CLK_RTC_APB 24
  7415. +#define CLK_PWRCTRL 25
  7416. +#define CLK_TCCAL 26
  7417. +#define CLK_APB_SPC 27
  7418. +#define CLK_E907 28
  7419. +#define CLK_A27L2 29
  7420. +
  7421. +#define CLK_MAX_NO (CLK_A27L2 + 1)
  7422. +
  7423. +#endif /* _DT_BINDINGS_CLK_SUN20IW5_AON_H_ */
  7424. diff --git a/include/dt-bindings/clock/sun20iw5-app-ccu.h b/include/dt-bindings/clock/sun20iw5-app-ccu.h
  7425. new file mode 100644
  7426. index 000000000000..040d5e1a4dd9
  7427. --- /dev/null
  7428. +++ b/include/dt-bindings/clock/sun20iw5-app-ccu.h
  7429. @@ -0,0 +1,110 @@
  7430. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7431. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7432. +/*
  7433. + * Copyright (C) 2023 [email protected]
  7434. + */
  7435. +
  7436. +#ifndef _DT_BINDINGS_CLK_SUN20IW5_APP_H_
  7437. +#define _DT_BINDINGS_CLK_SUN20IW5_APP_H_
  7438. +
  7439. +#define CLK_DRAM 0
  7440. +#define CLK_E907_TS 1
  7441. +#define CLK_AL27_MT 2
  7442. +#define CLK_SMHC0 3
  7443. +#define CLK_SS 4
  7444. +#define CLK_SPI 5
  7445. +#define CLK_SPIF 6
  7446. +#define CLK_MCSI 7
  7447. +#define CLK_CSI_MASTER0 8
  7448. +#define CLK_CSI_MASTER1 9
  7449. +#define CLK_SPI2 10
  7450. +#define CLK_TCONLCD 11
  7451. +#define CLK_DE 12
  7452. +#define CLK_G2D 13
  7453. +#define CLK_GPADC0_24M 14
  7454. +#define CLK_VE 15
  7455. +#define CLK_AUDIO_DAC 16
  7456. +#define CLK_AUDIO_ADC 17
  7457. +#define CLK_DMIC 18
  7458. +#define CLK_I2S0 19
  7459. +#define CLK_I2S1 20
  7460. +#define CLK_SMHC1 21
  7461. +#define CLK_PLL_AUDIO_4X 22
  7462. +#define CLK_PLL_AUDIO_1X 23
  7463. +#define CLK_SPI1 24
  7464. +#define CLK_GMAC_FANOUT 25
  7465. +#define CLK_MSGBOX 26
  7466. +#define CLK_WIEGAND_24M 27
  7467. +#define CLK_USB_24M 28
  7468. +#define CLK_USB_12M 29
  7469. +#define CLK_USB_48M 30
  7470. +#define CLK_AVS 31
  7471. +#define CLK_GMAC_25M 32
  7472. +#define CLK_BUS_DPSS_TOP 33
  7473. +#define CLK_BUS_GPIO 34
  7474. +#define CLK_BUS_WKT 35
  7475. +#define CLK_MCSI_AHB 36
  7476. +#define CLK_MBUS_MCSI 37
  7477. +#define CLK_VID_OUT 38
  7478. +#define CLK_MBUS_VID_OUT 39
  7479. +#define CLK_HBUS_GMAC 40
  7480. +#define CLK_USBOHCI 41
  7481. +#define CLK_USBEHCI 42
  7482. +#define CLK_USBOTG 43
  7483. +#define CLK_USB 44
  7484. +#define CLK_UART3 45
  7485. +#define CLK_UART2 46
  7486. +#define CLK_UART1 47
  7487. +#define CLK_UART0 48
  7488. +#define CLK_TWI0 49
  7489. +#define CLK_PWM 50
  7490. +#define CLK_TRNG 51
  7491. +#define CLK_TIMER 52
  7492. +#define CLK_SG_DMA 53
  7493. +#define CLK_DMA 54
  7494. +#define CLK_SYSCRTL 55
  7495. +#define CLK_CE 56
  7496. +#define CLK_HSTIMER 57
  7497. +#define CLK_SPLOCK 58
  7498. +#define CLK_BUS_DRAM 59
  7499. +#define CLK_RV_MSGBOX 60
  7500. +#define CLK_RISCV 61
  7501. +#define CLK_MBUS_G2D 62
  7502. +#define CLK_BUS_G2D 63
  7503. +#define CLK_G2D_HB 64
  7504. +#define CLK_TWI2 65
  7505. +#define CLK_TWI1 66
  7506. +#define CLK_BUS_SPI2 67
  7507. +#define CLK_BUS_GMAC 68
  7508. +#define CLK_BUS_SMHC1 69
  7509. +#define CLK_BUS_SMHC0 70
  7510. +#define CLK_BUS_SPI1 71
  7511. +#define CLK_GBGSYS 72
  7512. +#define CLK_MBUS_GMAC 73
  7513. +#define CLK_MBUS_SMHC1 74
  7514. +#define CLK_MBUS_SMHC0 75
  7515. +#define CLK_MBUS_USB 76
  7516. +#define CLK_MBUS_DMA 77
  7517. +#define CLK_BUS_I2S1 78
  7518. +#define CLK_BUS_I2S0 79
  7519. +#define CLK_BUS_DMIC 80
  7520. +#define CLK_BUS_ADDA 81
  7521. +#define CLK_BUS_SPIF 82
  7522. +#define CLK_BUS_SPI 83
  7523. +#define CLK_BUS_VE_AHB 84
  7524. +#define CLK_MBUS_VE 85
  7525. +#define CLK_BUS_THS 86
  7526. +#define CLK_GPA 87
  7527. +#define CLK_HBUS_MCSI 88
  7528. +#define CLK_SBUS_MCSI 89
  7529. +#define CLK_BUS_MISP 90
  7530. +#define CLK_SD_MONITOR 91
  7531. +#define CLK_AHB_MONITOR 92
  7532. +#define CLK_SBUS_VE 93
  7533. +#define CLK_HBUS_VE 94
  7534. +#define CLK_BUS_TCON 95
  7535. +#define CLK_SGDMA 96
  7536. +#define CLK_BUS_DE 97
  7537. +#define CLK_DE_HB 98
  7538. +
  7539. +#endif /* _DT_BINDINGS_CLK_SUN20IW5_APP_H_ */
  7540. diff --git a/include/dt-bindings/clock/sun50iw10-ccu.h b/include/dt-bindings/clock/sun50iw10-ccu.h
  7541. new file mode 100644
  7542. index 000000000000..b932bd044d00
  7543. --- /dev/null
  7544. +++ b/include/dt-bindings/clock/sun50iw10-ccu.h
  7545. @@ -0,0 +1,159 @@
  7546. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7547. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7548. +/*
  7549. + * Copyright (C) 2020 [email protected]
  7550. + */
  7551. +
  7552. +#ifndef _DT_BINDINGS_CLK_SUN50IW10_H_
  7553. +#define _DT_BINDINGS_CLK_SUN50IW10_H_
  7554. +
  7555. +#define CLK_OSC12M 0
  7556. +#define CLK_PLL_CPUX 1
  7557. +#define CLK_PLL_DDR0 2
  7558. +#define CLK_PLL_PERIPH0 3
  7559. +#define CLK_PLL_PERIPH0_2X 4
  7560. +#define CLK_PLL_PERIPH1 5
  7561. +#define CLK_PLL_PERIPH1_2X 6
  7562. +#define CLK_PLL_GPU 7
  7563. +#define CLK_PLL_VIDEO0 8
  7564. +#define CLK_PLL_VIDEO0_2X 9
  7565. +#define CLK_PLL_VIDEO0_4X 10
  7566. +#define CLK_PLL_VIDEO1 11
  7567. +#define CLK_PLL_VIDEO1_2X 12
  7568. +#define CLK_PLL_VIDEO1_4X 13
  7569. +#define CLK_PLL_VIDEO2 14
  7570. +#define CLK_PLL_VIDEO2_2X 15
  7571. +#define CLK_PLL_VIDEO2_4X 16
  7572. +#define CLK_PLL_VIDEO3 17
  7573. +#define CLK_PLL_VIDEO3_2X 18
  7574. +#define CLK_PLL_VIDEO3_4X 19
  7575. +#define CLK_PLL_VE 20
  7576. +#define CLK_PLL_COM 21
  7577. +#define CLK_PLL_COM_AUDIO 22
  7578. +#define CLK_PLL_AUDIO 23
  7579. +#define CLK_CPUX 24
  7580. +#define CLK_AXI 25
  7581. +#define CLK_CPUX_APB 26
  7582. +#define CLK_PSI_AHB1_AHB2 27
  7583. +#define CLK_AHB3 28
  7584. +#define CLK_APB1 29
  7585. +#define CLK_APB2 30
  7586. +#define CLK_MBUS 31
  7587. +#define CLK_DE0 32
  7588. +#define CLK_DE1 33
  7589. +#define CLK_BUS_DE0 34
  7590. +#define CLK_BUS_DE1 35
  7591. +#define CLK_EINK 36
  7592. +#define CLK_BUS_EINK 37
  7593. +#define CLK_G2D 38
  7594. +#define CLK_BUS_G2D 39
  7595. +#define CLK_EINK_PANEL 40
  7596. +#define CLK_GPU 41
  7597. +#define CLK_BUS_GPU 42
  7598. +#define CLK_CE 43
  7599. +#define CLK_BUS_CE 44
  7600. +#define CLK_VE 45
  7601. +#define CLK_BUS_VE 46
  7602. +#define CLK_BUS_DMA 47
  7603. +#define CLK_BUS_MSGBOX 48
  7604. +#define CLK_BUS_SPINLOCK 49
  7605. +#define CLK_BUS_HSTIMER 50
  7606. +#define CLK_AVS 51
  7607. +#define CLK_BUS_DBG 52
  7608. +#define CLK_BUS_PSI 53
  7609. +#define CLK_BUS_PWM 54
  7610. +#define CLK_BUS_IOMMU 55
  7611. +#define CLK_MBUS_DMA 56
  7612. +#define CLK_MBUS_VE 57
  7613. +#define CLK_MBUS_CE 58
  7614. +#define CLK_MBUS_NAND 59
  7615. +#define CLK_MBUS_CSI 60
  7616. +#define CLK_MBUS_ISP 61
  7617. +#define CLK_MBUS_G2D 62
  7618. +#define CLK_BUS_DRAM 63
  7619. +#define CLK_NAND0 64
  7620. +#define CLK_NAND1 65
  7621. +#define CLK_BUS_NAND 66
  7622. +#define CLK_MMC0 67
  7623. +#define CLK_MMC1 68
  7624. +#define CLK_MMC2 69
  7625. +#define CLK_MMC3 70
  7626. +#define CLK_BUS_MMC0 71
  7627. +#define CLK_BUS_MMC1 72
  7628. +#define CLK_BUS_MMC2 73
  7629. +#define CLK_BUS_MMC3 74
  7630. +#define CLK_BUS_UART0 75
  7631. +#define CLK_BUS_UART1 76
  7632. +#define CLK_BUS_UART2 77
  7633. +#define CLK_BUS_UART3 78
  7634. +#define CLK_BUS_UART4 79
  7635. +#define CLK_BUS_UART5 80
  7636. +#define CLK_BUS_UART6 81
  7637. +#define CLK_BUS_I2C0 82
  7638. +#define CLK_BUS_I2C1 83
  7639. +#define CLK_BUS_I2C2 84
  7640. +#define CLK_BUS_I2C3 85
  7641. +#define CLK_BUS_I2C4 86
  7642. +#define CLK_BUS_I2C5 87
  7643. +#define CLK_SPI0 88
  7644. +#define CLK_SPI1 89
  7645. +#define CLK_SPI2 90
  7646. +#define CLK_BUS_SPI0 91
  7647. +#define CLK_BUS_SPI1 92
  7648. +#define CLK_BUS_SPI2 93
  7649. +#define CLK_EMAC0_25M 94
  7650. +#define CLK_EMAC1_25M 95
  7651. +#define CLK_BUS_EMAC0 96
  7652. +#define CLK_BUS_EMAC1 97
  7653. +#define CLK_IR_RX 98
  7654. +#define CLK_BUS_IR_RX 99
  7655. +#define CLK_IR_TX 100
  7656. +#define CLK_BUS_IR_TX 101
  7657. +#define CLK_BUS_GPADC 102
  7658. +#define CLK_BUS_THS 103
  7659. +#define CLK_I2S0 104
  7660. +#define CLK_I2S1 105
  7661. +#define CLK_I2S2 106
  7662. +#define CLK_I2S3 107
  7663. +#define CLK_BUS_I2S0 108
  7664. +#define CLK_BUS_I2S1 109
  7665. +#define CLK_BUS_I2S2 110
  7666. +#define CLK_BUS_I2S3 111
  7667. +#define CLK_SPDIF 112
  7668. +#define CLK_BUS_SPDIF 113
  7669. +#define CLK_DMIC 114
  7670. +#define CLK_BUS_DMIC 115
  7671. +#define CLK_AUDIO_DAC 116
  7672. +#define CLK_AUDIO_ADC 117
  7673. +#define CLK_AUDIO_4X 118
  7674. +#define CLK_BUS_AUDIO_CODEC 119
  7675. +#define CLK_USB_OHCI0 120
  7676. +#define CLK_USB_PHY0 121
  7677. +#define CLK_USB_OHCI1 122
  7678. +#define CLK_USB_PHY1 123
  7679. +#define CLK_BUS_OHCI0 124
  7680. +#define CLK_BUS_OHCI1 125
  7681. +#define CLK_BUS_EHCI0 126
  7682. +#define CLK_BUS_EHCI1 127
  7683. +#define CLK_BUS_OTG 128
  7684. +#define CLK_BUS_LRADC 129
  7685. +#define CLK_BUS_DPSS_TOP0 130
  7686. +#define CLK_BUS_DPSS_TOP1 131
  7687. +#define CLK_MIPI_DSI 132
  7688. +#define CLK_BUS_MIPI_DSI 133
  7689. +#define CLK_TCON_LCD0 134
  7690. +#define CLK_TCON_LCD1 135
  7691. +#define CLK_BUS_TCON_LCD0 136
  7692. +#define CLK_BUS_TCON_LCD1 137
  7693. +#define CLK_LEDC 138
  7694. +#define CLK_BUS_LEDC 139
  7695. +#define CLK_CSI_TOP 140
  7696. +#define CLK_CSI0_MCLK 141
  7697. +#define CLK_CSI1_MCLK 142
  7698. +#define CLK_BUS_CSI 143
  7699. +#define CLK_CSI_ISP 144
  7700. +
  7701. +/* Only for ccu-displl.c driver */
  7702. +#define CLK_DISPLL 0
  7703. +
  7704. +#endif /* _DT_BINDINGS_CLK_SUN50IW10_H_ */
  7705. diff --git a/include/dt-bindings/clock/sun50iw10-r-ccu.h b/include/dt-bindings/clock/sun50iw10-r-ccu.h
  7706. new file mode 100644
  7707. index 000000000000..2647e0f1f01c
  7708. --- /dev/null
  7709. +++ b/include/dt-bindings/clock/sun50iw10-r-ccu.h
  7710. @@ -0,0 +1,26 @@
  7711. +/* SPDX-License-Identifier: GPL-2.0 */
  7712. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7713. +/*
  7714. + * Copyright (c) 2020 [email protected]
  7715. + */
  7716. +
  7717. +#ifndef _DT_BINDINGS_CLK_SUN50IW10_R_CCU_H_
  7718. +#define _DT_BINDINGS_CLK_SUN50IW10_R_CCU_H_
  7719. +
  7720. +#define CLK_CPUS 0
  7721. +#define CLK_R_AHB 1
  7722. +#define CLK_R_APB1 2
  7723. +#define CLK_R_APB2 3
  7724. +#define CLK_R_APB1_TIMER 4
  7725. +#define CLK_R_APB1_TWD 5
  7726. +#define CLK_R_APB1_PWM 6
  7727. +#define CLK_R_APB1_BUS_PWM 7
  7728. +#define CLK_R_APB1_PPU 8
  7729. +#define CLK_R_APB2_UART 9
  7730. +#define CLK_R_APB2_I2C0 10
  7731. +#define CLK_R_APB2_I2C1 11
  7732. +#define CLK_R_APB1_IR 12
  7733. +#define CLK_R_APB1_BUS_IR 13
  7734. +#define CLK_R_AHB_BUS_RTC 14
  7735. +
  7736. +#endif /* _DT_BINDINGS_CLK_SUN50IW10_R_CCU_H_ */
  7737. diff --git a/include/dt-bindings/clock/sun50iw10-rtc.h b/include/dt-bindings/clock/sun50iw10-rtc.h
  7738. new file mode 100644
  7739. index 000000000000..012a69941844
  7740. --- /dev/null
  7741. +++ b/include/dt-bindings/clock/sun50iw10-rtc.h
  7742. @@ -0,0 +1,16 @@
  7743. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7744. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7745. +/*
  7746. + * Copyright (C) 2020 [email protected]
  7747. + */
  7748. +
  7749. +#ifndef _DT_BINDINGS_CLK_SUN50IW10_RTC_H_
  7750. +#define _DT_BINDINGS_CLK_SUN50IW10_RTC_H_
  7751. +
  7752. +#define CLK_DCXO24M_OUT 0
  7753. +#define CLK_IOSC 1
  7754. +#define CLK_OSC32K 2
  7755. +#define CLK_OSC32K_OUT 3
  7756. +#define CLK_RTC_1K 4
  7757. +
  7758. +#endif /* _DT_BINDINGS_CLK_SUN50IW10_RTC_H_ */
  7759. diff --git a/include/dt-bindings/clock/sun50iw12-ccu.h b/include/dt-bindings/clock/sun50iw12-ccu.h
  7760. new file mode 100644
  7761. index 000000000000..722852ce5ad7
  7762. --- /dev/null
  7763. +++ b/include/dt-bindings/clock/sun50iw12-ccu.h
  7764. @@ -0,0 +1,146 @@
  7765. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7766. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7767. +/*
  7768. + * Copyright (C) 2020 [email protected]
  7769. + */
  7770. +
  7771. +#ifndef _DT_BINDINGS_CLK_SUN50IW12_H_
  7772. +#define _DT_BINDINGS_CLK_SUN50IW12_H_
  7773. +
  7774. +#define CLK_OSC12M 0
  7775. +#define CLK_PLL_CPUX 1
  7776. +#define CLK_PLL_DDR0 2
  7777. +#define CLK_PLL_PERIPH0 3
  7778. +#define CLK_PLL_PERIPH0_2X 4
  7779. +#define CLK_PLL_PERIPH1 5
  7780. +#define CLK_PLL_PERIPH1_2X 6
  7781. +#define CLK_PLL_GPU 7
  7782. +#define CLK_PLL_VIDEO0 8
  7783. +#define CLK_PLL_VIDEO0_4X 9
  7784. +#define CLK_PLL_VIDEO1 10
  7785. +#define CLK_PLL_VIDEO1_4X 11
  7786. +#define CLK_PLL_VIDEO2 12
  7787. +#define CLK_PLL_VIDEO2_4X 13
  7788. +#define CLK_PLL_VE 14
  7789. +#define CLK_PLL_ADC 15
  7790. +#define CLK_PLL_VIDEO3 16
  7791. +#define CLK_PLL_VIDEO3_4X 17
  7792. +#define CLK_PLL_AUDIO 18
  7793. +#define CLK_CPUX 19
  7794. +#define CLK_AXI 20
  7795. +#define CLK_CPUX_APB 21
  7796. +#define CLK_AHB 22
  7797. +#define CLK_APB0 23
  7798. +#define CLK_APB1 24
  7799. +#define CLK_MBUS 25
  7800. +#define CLK_MIPS 26
  7801. +#define CLK_BUS_MIPS 27
  7802. +#define CLK_GPU 28
  7803. +#define CLK_BUS_GPU 29
  7804. +#define CLK_CE 30
  7805. +#define CLK_BUS_CE 31
  7806. +#define CLK_VE_CORE 32
  7807. +#define CLK_BUS_VE 33
  7808. +#define CLK_BUS_AV1 34
  7809. +#define CLK_BUS_VE3 35
  7810. +#define CLK_BUS_DMA 36
  7811. +#define CLK_MSGBOX 37
  7812. +#define CLK_SPINLOCK 38
  7813. +#define CLK_TIMER0 39
  7814. +#define CLK_TIMER1 40
  7815. +#define CLK_TIMER2 41
  7816. +#define CLK_TIMER3 42
  7817. +#define CLK_TIMER4 43
  7818. +#define CLK_TIMER5 44
  7819. +#define CLK_BUS_TIMER0 45
  7820. +#define CLK_BUS_DBG 46
  7821. +#define CLK_BUS_PWM 47
  7822. +#define CLK_BUS_IOMMU 48
  7823. +#define CLK_DRAM 49
  7824. +#define CLK_MBUS_DMA 50
  7825. +#define CLK_MBUS_VE3 51
  7826. +#define CLK_MBUS_CE 52
  7827. +#define CLK_MBUS_AV1 53
  7828. +#define CLK_MBUS_NAND 54
  7829. +#define CLK_BUS_DRAM 55
  7830. +#define CLK_NAND0 56
  7831. +#define CLK_NAND1 57
  7832. +#define CLK_BUS_NAND 58
  7833. +#define CLK_MMC0 59
  7834. +#define CLK_MMC1 60
  7835. +#define CLK_MMC2 61
  7836. +#define CLK_BUS_MMC0 62
  7837. +#define CLK_BUS_MMC1 63
  7838. +#define CLK_BUS_MMC2 64
  7839. +#define CLK_BUS_UART0 65
  7840. +#define CLK_BUS_UART1 66
  7841. +#define CLK_BUS_UART2 67
  7842. +#define CLK_BUS_UART3 68
  7843. +#define CLK_BUS_I2C0 69
  7844. +#define CLK_BUS_I2C1 70
  7845. +#define CLK_BUS_I2C2 71
  7846. +#define CLK_BUS_I2C3 72
  7847. +#define CLK_SPI0 73
  7848. +#define CLK_SPI1 74
  7849. +#define CLK_BUS_SPI0 75
  7850. +#define CLK_BUS_SPI1 76
  7851. +#define CLK_EMAC_25M 77
  7852. +#define CLK_BUS_EMAC 78
  7853. +#define CLK_BUS_GPADC 79
  7854. +#define CLK_BUS_THS 80
  7855. +#define CLK_I2S0 81
  7856. +#define CLK_I2S1 82
  7857. +#define CLK_I2S2 83
  7858. +#define CLK_BUS_I2S0 84
  7859. +#define CLK_BUS_I2S1 85
  7860. +#define CLK_BUS_I2S2 86
  7861. +#define CLK_SPDIF0_RX 87
  7862. +#define CLK_SPDIF0_TX 88
  7863. +#define CLK_SPDIF1_RX 89
  7864. +#define CLK_SPDIF1_TX 90
  7865. +#define CLK_BUS_SPDIF0 91
  7866. +#define CLK_BUS_SPDIF1 92
  7867. +#define CLK_AUDIO_HUB 93
  7868. +#define CLK_AUDIO_CODEC_DAC 94
  7869. +#define CLK_AUDIO_CODEC_ADC 95
  7870. +#define CLK_BUS_AUDIO_CODEC 96
  7871. +#define CLK_USB_OHCI0 97
  7872. +#define CLK_USB_OHCI1 98
  7873. +#define CLK_USB_OHCI2 99
  7874. +#define CLK_BUS_OHCI0 100
  7875. +#define CLK_BUS_OHCI1 101
  7876. +#define CLK_BUS_OHCI2 102
  7877. +#define CLK_BUS_EHCI0 103
  7878. +#define CLK_BUS_EHCI1 104
  7879. +#define CLK_BUS_EHCI2 105
  7880. +#define CLK_BUS_OTG 106
  7881. +#define CLK_BUS_LRADC 107
  7882. +#define CLK_ADC 108
  7883. +#define CLK_DTMB_120M 109
  7884. +#define CLK_TVFE_1296M 110
  7885. +#define CLK_I2H 111
  7886. +#define CLK_CIP_TSX 112
  7887. +#define CLK_CIP_MCX 113
  7888. +#define CLK_CIP_TSP 114
  7889. +#define CLK_TSA_TSP 115
  7890. +#define CLK_CIP27 116
  7891. +#define CLK_CIP_MTS0 117
  7892. +#define CLK_AUDIO_CPU 118
  7893. +#define CLK_AUDIO_UMAC 119
  7894. +#define CLK_AUDIO_IHB 120
  7895. +#define CLK_TSA432 121
  7896. +#define CLK_MPG0 122
  7897. +#define CLK_MPG1 123
  7898. +#define CLK_BUS_DEMOD 124
  7899. +#define CLK_TCD3 125
  7900. +#define CLK_VINCAP_DMA 126
  7901. +#define CLK_BUS_HDMI_AUDIO 127
  7902. +#define CLK_BUS_CAP_300M 128
  7903. +#define CLK_HDMI_AUDIO 129
  7904. +#define CLK_BUS_TVCAP 130
  7905. +#define CLK_DEINT 131
  7906. +#define CLK_SVP_DTL 132
  7907. +#define CLK_AFBD 133
  7908. +#define CLK_BUS_DISP 134
  7909. +
  7910. +#endif /* _DT_BINDINGS_CLK_SUN50IW12_H_ */
  7911. diff --git a/include/dt-bindings/clock/sun50iw12-r-ccu.h b/include/dt-bindings/clock/sun50iw12-r-ccu.h
  7912. new file mode 100644
  7913. index 000000000000..01252add89d6
  7914. --- /dev/null
  7915. +++ b/include/dt-bindings/clock/sun50iw12-r-ccu.h
  7916. @@ -0,0 +1,33 @@
  7917. +/* SPDX-License-Identifier: GPL-2.0 */
  7918. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7919. +/*
  7920. + * Copyright (c) 2020 [email protected]
  7921. + */
  7922. +
  7923. +#ifndef _DT_BINDINGS_CLK_SUN50IW12_R_CCU_H_
  7924. +#define _DT_BINDINGS_CLK_SUN50IW12_R_CCU_H_
  7925. +
  7926. +#define CLK_CPUS 0
  7927. +#define CLK_R_AHB 1
  7928. +#define CLK_R_APB0 2
  7929. +#define CLK_R_APB1 3
  7930. +#define CLK_R_APB0_TIMER0 4
  7931. +#define CLK_R_APB0_TIMER1 5
  7932. +#define CLK_R_APB0_TIMER2 6
  7933. +#define CLK_R_APB0_BUS_TIMER0 7
  7934. +#define CLK_R_APB0_EDID 8
  7935. +#define CLK_R_APB0_BUS_WDT1 9
  7936. +#define CLK_R_APB0_PWM 10
  7937. +#define CLK_R_APB0_BUS_PWM 11
  7938. +#define CLK_R_APB1_BUS_UART 12
  7939. +#define CLK_R_APB1_BUS_I2C0 13
  7940. +#define CLK_R_APB1_BUS_I2C1 14
  7941. +#define CLK_R_APB1_BUS_PPU 15
  7942. +#define CLK_R_APB1_BUS_TZMA 16
  7943. +#define CLK_R_CPUS_BUS_BIST 17
  7944. +#define CLK_R_APB0_IR 18
  7945. +#define CLK_R_APB0_BUS_IR 19
  7946. +#define CLK_R_AHB_BUS_RTC 20
  7947. +#define CLK_R_AHB_BUS_CPUCFG 21
  7948. +
  7949. +#endif /* _DT_BINDINGS_CLK_SUN50IW12_R_CCU_H_ */
  7950. diff --git a/include/dt-bindings/clock/sun50iw12-rtc.h b/include/dt-bindings/clock/sun50iw12-rtc.h
  7951. new file mode 100644
  7952. index 000000000000..91ddad86f024
  7953. --- /dev/null
  7954. +++ b/include/dt-bindings/clock/sun50iw12-rtc.h
  7955. @@ -0,0 +1,16 @@
  7956. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  7957. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7958. +/*
  7959. + * Copyright (C) 2020 [email protected]
  7960. + */
  7961. +
  7962. +#ifndef _DT_BINDINGS_CLK_SUN50IW12_RTC_H_
  7963. +#define _DT_BINDINGS_CLK_SUN50IW12_RTC_H_
  7964. +
  7965. +#define CLK_DCXO24M_OUT 0
  7966. +#define CLK_IOSC 1
  7967. +#define CLK_OSC32K 2
  7968. +#define CLK_OSC32K_OUT 3
  7969. +#define CLK_RTC_1K 4
  7970. +
  7971. +#endif /* _DT_BINDINGS_CLK_SUN50IW10_RTC_H_ */
  7972. diff --git a/include/dt-bindings/clock/sun50iw9-ccu-rtc.h b/include/dt-bindings/clock/sun50iw9-ccu-rtc.h
  7973. new file mode 100644
  7974. index 000000000000..70fe5eaa918c
  7975. --- /dev/null
  7976. +++ b/include/dt-bindings/clock/sun50iw9-ccu-rtc.h
  7977. @@ -0,0 +1,16 @@
  7978. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  7979. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  7980. +/*
  7981. + * Copyright (C) 2020 [email protected]
  7982. + */
  7983. +
  7984. +#ifndef _DT_BINDINGS_CLK_SUN50IW9_CCU_RTC_H_
  7985. +#define _DT_BINDINGS_CLK_SUN50IW9_CCU_RTC_H_
  7986. +
  7987. +#define CLK_RTC_1K 0
  7988. +#define CLK_PLL_PERIPHO_2X_32K 1
  7989. +#define CLK_DCXO_32K 2
  7990. +#define CLK_DCXO_32K_OUT 3
  7991. +#define CLK_OSC32K_OUT 4
  7992. +
  7993. +#endif /* _DT_BINDINGS_CLK_SUN50IW9_RTC_H_ */
  7994. diff --git a/include/dt-bindings/clock/sun50iw9-ccu.h b/include/dt-bindings/clock/sun50iw9-ccu.h
  7995. new file mode 100644
  7996. index 000000000000..144093593838
  7997. --- /dev/null
  7998. +++ b/include/dt-bindings/clock/sun50iw9-ccu.h
  7999. @@ -0,0 +1,151 @@
  8000. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8001. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8002. +/*
  8003. + * Copyright (C) 2020 [email protected]
  8004. + */
  8005. +
  8006. +#ifndef _DT_BINDINGS_CLK_SUN50IW9_H_
  8007. +#define _DT_BINDINGS_CLK_SUN50IW9_H_
  8008. +
  8009. +#define CLK_OSC12M 0
  8010. +#define CLK_PLL_CPUX 1
  8011. +#define CLK_PLL_DDR0 2
  8012. +#define CLK_PLL_DDR1 3
  8013. +#define CLK_PLL_PERIPH0 4
  8014. +#define CLK_PLL_PERIPH0_2X 5
  8015. +#define CLK_PLL_PERIPH1 6
  8016. +#define CLK_PLL_PERIPH1_2X 7
  8017. +#define CLK_PLL_GPU 8
  8018. +#define CLK_PLL_VIDEO0 9
  8019. +#define CLK_PLL_VIDEO0_4X 10
  8020. +#define CLK_PLL_VIDEO1 11
  8021. +#define CLK_PLL_VIDEO1_4X 12
  8022. +#define CLK_PLL_VIDEO2 13
  8023. +#define CLK_PLL_VIDEO2_4X 14
  8024. +#define CLK_PLL_VE 15
  8025. +#define CLK_PLL_DE 16
  8026. +#define CLK_PLL_AUDIO 17
  8027. +#define CLK_PLL_AUDIO_2X 18
  8028. +#define CLK_PLL_AUDIO_4X 19
  8029. +#define CLK_PLL_CSI 20
  8030. +#define CLK_CPUX 21
  8031. +#define CLK_AXI 22
  8032. +#define CLK_CPUX_APB 23
  8033. +#define CLK_PSI_AHB1_AHB2 24
  8034. +#define CLK_AHB3 25
  8035. +#define CLK_APB1 26
  8036. +#define CLK_APB2 27
  8037. +#define CLK_MBUS 28
  8038. +#define CLK_DE 29
  8039. +#define CLK_BUS_DE 30
  8040. +#define CLK_DI 31
  8041. +#define CLK_BUS_DI 32
  8042. +#define CLK_G2D 33
  8043. +#define CLK_BUS_G2D 34
  8044. +#define CLK_GPU0 35
  8045. +#define CLK_GPU1 36
  8046. +#define CLK_BUS_GPU 37
  8047. +#define CLK_CE 38
  8048. +#define CLK_BUS_CE 39
  8049. +#define CLK_VE 40
  8050. +#define CLK_BUS_VE 41
  8051. +#define CLK_BUS_DMA 42
  8052. +#define CLK_BUS_HSTIMER 43
  8053. +#define CLK_AVS 44
  8054. +#define CLK_BUS_DBG 45
  8055. +#define CLK_BUS_PSI 46
  8056. +#define CLK_BUS_PWM 47
  8057. +#define CLK_BUS_IOMMU 48
  8058. +#define CLK_DRAM 49
  8059. +#define CLK_MBUS_DMA 50
  8060. +#define CLK_MBUS_VE 51
  8061. +#define CLK_MBUS_CE 52
  8062. +#define CLK_MBUS_TS 53
  8063. +#define CLK_MBUS_NAND 54
  8064. +#define CLK_MBUS_CSI 55
  8065. +#define CLK_MBUS_G2D 56
  8066. +#define CLK_BUS_DRAM 57
  8067. +#define CLK_NAND0 58
  8068. +#define CLK_NAND1 59
  8069. +#define CLK_BUS_NAND 60
  8070. +#define CLK_MMC0 61
  8071. +#define CLK_MMC1 62
  8072. +#define CLK_MMC2 63
  8073. +#define CLK_BUS_MMC0 64
  8074. +#define CLK_BUS_MMC1 65
  8075. +#define CLK_BUS_MMC2 66
  8076. +#define CLK_BUS_UART0 67
  8077. +#define CLK_BUS_UART1 68
  8078. +#define CLK_BUS_UART2 69
  8079. +#define CLK_BUS_UART3 70
  8080. +#define CLK_BUS_UART4 71
  8081. +#define CLK_BUS_UART5 72
  8082. +#define CLK_BUS_I2C0 73
  8083. +#define CLK_BUS_I2C1 74
  8084. +#define CLK_BUS_I2C2 75
  8085. +#define CLK_BUS_I2C3 76
  8086. +#define CLK_BUS_I2C4 77
  8087. +#define CLK_BUS_SCR 78
  8088. +#define CLK_SPI0 79
  8089. +#define CLK_SPI1 80
  8090. +#define CLK_BUS_SPI0 81
  8091. +#define CLK_BUS_SPI1 82
  8092. +#define CLK_EMAC_25M 83
  8093. +#define CLK_BUS_EMAC0 84
  8094. +#define CLK_BUS_EMAC1 85
  8095. +#define CLK_TS 86
  8096. +#define CLK_BUS_TS 87
  8097. +#define CLK_BUS_GPADC 88
  8098. +#define CLK_BUS_THS 89
  8099. +#define CLK_SPDIF 90
  8100. +#define CLK_BUS_SPDIF 91
  8101. +#define CLK_DMIC 92
  8102. +#define CLK_BUS_DMIC 93
  8103. +#define CLK_AUDIO 94
  8104. +#define CLK_AUDIO_4X 95
  8105. +#define CLK_BUS_AUDIO_CODEC 96
  8106. +#define CLK_AUDIO_HUB 97
  8107. +#define CLK_BUS_AUDIO_HUB 98
  8108. +#define CLK_USB_OHCI0 99
  8109. +#define CLK_USB_PHY0 100
  8110. +#define CLK_USB_OHCI1 101
  8111. +#define CLK_USB_PHY1 102
  8112. +#define CLK_USB_OHCI2 103
  8113. +#define CLK_USB_PHY2 104
  8114. +#define CLK_USB_OHCI3 105
  8115. +#define CLK_USB_PHY3 106
  8116. +#define CLK_BUS_OHCI0 107
  8117. +#define CLK_BUS_OHCI1 108
  8118. +#define CLK_BUS_OHCI2 109
  8119. +#define CLK_BUS_OHCI3 110
  8120. +#define CLK_BUS_EHCI0 111
  8121. +#define CLK_BUS_EHCI1 112
  8122. +#define CLK_BUS_EHCI2 113
  8123. +#define CLK_BUS_EHCI3 114
  8124. +#define CLK_BUS_OTG 115
  8125. +#define CLK_BUS_LRADC 116
  8126. +#define CLK_HDMI 117
  8127. +#define CLK_HDMI_SLOW 118
  8128. +#define CLK_PLL_PERIPH0_2X_DIV 119
  8129. +#define CLK_HDMI_CEC 120
  8130. +#define CLK_BUS_HDMI 121
  8131. +#define CLK_BUS_DISPLAY_IF_TOP 122
  8132. +#define CLK_TCON_LCD0 123
  8133. +#define CLK_TCON_LCD1 124
  8134. +#define CLK_BUS_TCON_LCD0 125
  8135. +#define CLK_BUS_TCON_LCD1 126
  8136. +#define CLK_TCON_TV0 127
  8137. +#define CLK_TCON_TV1 128
  8138. +#define CLK_BUS_TCON_TV0 129
  8139. +#define CLK_BUS_TCON_TV1 130
  8140. +#define CLK_TVE 131
  8141. +#define CLK_BUS_TVE 132
  8142. +#define CLK_BUS_TVE_TOP 133
  8143. +#define CLK_CSI_TOP 134
  8144. +#define CLK_CSI0_MCLK 135
  8145. +#define CLK_CSI1_MCLK 136
  8146. +#define CLK_BUS_CSI 137
  8147. +#define CLK_HDMI_HDCP 138
  8148. +#define CLK_BUS_HDMI_HDCP 139
  8149. +
  8150. +#endif /* _DT_BINDINGS_CLK_SUN50IW9_H_ */
  8151. diff --git a/include/dt-bindings/clock/sun50iw9-r-ccu.h b/include/dt-bindings/clock/sun50iw9-r-ccu.h
  8152. new file mode 100644
  8153. index 000000000000..20a3bf620335
  8154. --- /dev/null
  8155. +++ b/include/dt-bindings/clock/sun50iw9-r-ccu.h
  8156. @@ -0,0 +1,20 @@
  8157. +/* SPDX-License-Identifier: GPL-2.0 */
  8158. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8159. +/*
  8160. + * Copyright (c) 2020 [email protected]
  8161. + */
  8162. +
  8163. +#ifndef _DT_BINDINGS_CLK_SUN50IW9_R_CCU_H_
  8164. +#define _DT_BINDINGS_CLK_SUN50IW9_R_CCU_H_
  8165. +
  8166. +#define CLK_R_CPUS 0
  8167. +#define CLK_R_AHB 1
  8168. +#define CLK_R_APB1 2
  8169. +#define CLK_R_APB2 3
  8170. +#define CLK_R_APB1_TWD 4
  8171. +#define CLK_R_APB2_I2C 5
  8172. +#define CLK_R_APB1_IR 6
  8173. +#define CLK_R_APB1_BUS_IR 7
  8174. +#define CLK_R_AHB_BUS_RTC 8
  8175. +
  8176. +#endif /* _DT_BINDINGS_CLK_SUN50IW9_R_CCU_H_ */
  8177. diff --git a/include/dt-bindings/clock/sun55iw3-ccu.h b/include/dt-bindings/clock/sun55iw3-ccu.h
  8178. new file mode 100644
  8179. index 000000000000..f4ef44eae8e8
  8180. --- /dev/null
  8181. +++ b/include/dt-bindings/clock/sun55iw3-ccu.h
  8182. @@ -0,0 +1,207 @@
  8183. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8184. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8185. +/*
  8186. + * Copyright (C) 2022 [email protected]
  8187. + */
  8188. +
  8189. +#ifndef _DT_BINDINGS_CLK_SUN55IW3_H_
  8190. +#define _DT_BINDINGS_CLK_SUN55IW3_H_
  8191. +
  8192. +#define CLK_PLL_DDR 0
  8193. +#define CLK_PLL_PERI0_PARENT 1
  8194. +#define CLK_PLL_PERI0_2X 2
  8195. +#define CLK_PERI0_DIV3 3
  8196. +#define CLK_PLL_PERI0_800M 4
  8197. +#define CLK_PLL_PERI0_480M 5
  8198. +#define CLK_PLL_PERI0_600M 6
  8199. +#define CLK_PLL_PERI0_400M 7
  8200. +#define CLK_PLL_PERI0_300M 8
  8201. +#define CLK_PLL_PERI0_200M 9
  8202. +#define CLK_PLL_PERI0_160M 10
  8203. +#define CLK_PLL_PERI0_16M 11
  8204. +#define CLK_PLL_PERI0_150M 12
  8205. +#define CLK_PLL_PERI0_25M 13
  8206. +#define CLK_PLL_PERI1_PARENT 14
  8207. +#define CLK_PLL_PERI1_2X 15
  8208. +#define CLK_PLL_PERI1_800M 16
  8209. +#define CLK_PLL_PERI1_480M 17
  8210. +#define CLK_PLL_PERI1_600M 18
  8211. +#define CLK_PLL_PERI1_400M 19
  8212. +#define CLK_PLL_PERI1_300M 20
  8213. +#define CLK_PLL_PERI1_200M 21
  8214. +#define CLK_PLL_PERI1_160M 22
  8215. +#define CLK_PLL_PERI1_150M 23
  8216. +#define CLK_PLL_GPU 24
  8217. +#define CLK_PLL_VIDEO0_PARENT 25
  8218. +#define CLK_PLL_VIDEO0_4X 26
  8219. +#define CLK_PLL_VIDEO0_3X 27
  8220. +#define CLK_PLL_VIDEO1_PARENT 28
  8221. +#define CLK_PLL_VIDEO1_4X 29
  8222. +#define CLK_PLL_VIDEO1_3X 30
  8223. +#define CLK_PLL_VIDEO2_PARENT 31
  8224. +#define CLK_PLL_VIDEO2_4X 32
  8225. +#define CLK_PLL_VIDEO2_3X 33
  8226. +#define CLK_PLL_VIDEO3_PARENT 34
  8227. +#define CLK_PLL_VIDEO3_4X 35
  8228. +#define CLK_PLL_VIDEO3_3X 36
  8229. +#define CLK_PLL_VE 37
  8230. +#define CLK_PLL_AUDIO0_4X 38
  8231. +#define CLK_PLL_AUDIO0_2X 39
  8232. +#define CLK_PLL_AUDIO0_1X 40
  8233. +#define CLK_PLL_AUDIO0_DIV_48M 41
  8234. +#define CLK_PLL_NPU_4X 42
  8235. +#define CLK_PLL_NPU_2X 43
  8236. +#define CLK_PLL_NPU_1X 44
  8237. +#define CLK_TRACE 45
  8238. +#define CLK_AHB 46
  8239. +#define CLK_APB0 47
  8240. +#define CLK_APB1 48
  8241. +#define CLK_MBUS 49
  8242. +#define CLK_NSI 50
  8243. +#define CLK_GIC 51
  8244. +#define CLK_DE 52
  8245. +#define CLK_DE0 53
  8246. +#define CLK_DI 54
  8247. +#define CLK_BUS_DI 55
  8248. +#define CLK_G2D 56
  8249. +#define CLK_BUS_G2D 57
  8250. +#define CLK_GPU 58
  8251. +#define CLK_BUS_GPU 59
  8252. +#define CLK_CE 60
  8253. +#define CLK_CE_SYS 61
  8254. +#define CLK_BUS_CE 62
  8255. +#define CLK_VE 63
  8256. +#define CLK_BUS_VE 64
  8257. +#define CLK_NPU 65
  8258. +#define CLK_DMA 66
  8259. +#define CLK_MSGBOX0 67
  8260. +#define CLK_SPINLOCK 68
  8261. +#define CLK_TIMER 69
  8262. +#define CLK_DBGSYS 70
  8263. +#define CLK_PWM1 71
  8264. +#define CLK_PWM 72
  8265. +#define CLK_IOMMU 73
  8266. +#define CLK_BUS_IOMMU 74
  8267. +#define CLK_TIMER0 75
  8268. +#define CLK_TIMER1 76
  8269. +#define CLK_TIMER2 77
  8270. +#define CLK_TIMER3 78
  8271. +#define CLK_TIMER4 79
  8272. +#define CLK_TIMER5 80
  8273. +#define CLK_DRAM 81
  8274. +#define CLK_GMAC1_MBUS_GATE 82
  8275. +#define CLK_ISP_MBUS_GATE 83
  8276. +#define CLK_CSI_MBUS_GATE 84
  8277. +#define CLK_USB3_MBUS_GATE 85
  8278. +#define CLK_NAND_MBUS_GATE 86
  8279. +#define CLK_CE_MBUS_GATE 87
  8280. +#define CLK_VE_MBUS_GATE 88
  8281. +#define CLK_DMA_MBUS_GATE 89
  8282. +#define CLK_BUS_DRAM 90
  8283. +#define CLK_NAND0 91
  8284. +#define CLK_NAND0_CLK0 92
  8285. +#define CLK_NAND0_CLK1 93
  8286. +#define CLK_SMHC0 94
  8287. +#define CLK_SMHC1 95
  8288. +#define CLK_SMHC2 96
  8289. +#define CLK_BUS_SMHC2 97
  8290. +#define CLK_BUS_SMHC1 98
  8291. +#define CLK_BUS_SMHC0 99
  8292. +#define CLK_SYSDAP 100
  8293. +#define CLK_UART7 101
  8294. +#define CLK_UART6 102
  8295. +#define CLK_UART5 103
  8296. +#define CLK_UART4 104
  8297. +#define CLK_UART3 105
  8298. +#define CLK_UART2 106
  8299. +#define CLK_BUS_UART1 107
  8300. +#define CLK_BUS_UART0 108
  8301. +#define CLK_TWI5 109
  8302. +#define CLK_TWI4 110
  8303. +#define CLK_TWI3 111
  8304. +#define CLK_TWI2 112
  8305. +#define CLK_TWI1 113
  8306. +#define CLK_TWI0 114
  8307. +#define CLK_SPI0 115
  8308. +#define CLK_SPI1 116
  8309. +#define CLK_SPI2 117
  8310. +#define CLK_SPIF 118
  8311. +#define CLK_BUS_SPIF 119
  8312. +#define CLK_BUS_SPI2 120
  8313. +#define CLK_BUS_SPI1 121
  8314. +#define CLK_BUS_SPI0 122
  8315. +#define CLK_GMAC0_25M 123
  8316. +#define CLK_GMAC1_25M 124
  8317. +#define CLK_GMAC1 125
  8318. +#define CLK_GMAC0 126
  8319. +#define CLK_IRRX 127
  8320. +#define CLK_BUS_IRRX 128
  8321. +#define CLK_IRTX 129
  8322. +#define CLK_BUS_IRTX 130
  8323. +#define CLK_GPADC0_24M 131
  8324. +#define CLK_GPADC1_24M 132
  8325. +#define CLK_BUS_GPADC0 133
  8326. +#define CLK_BUS_GPADC1 134
  8327. +#define CLK_THS 135
  8328. +#define CLK_DCXO12M 136
  8329. +#define CLK_USB0 137
  8330. +#define CLK_USB1 138
  8331. +#define CLK_USB2_REF 139
  8332. +#define CLK_USB3_REF 140
  8333. +#define CLK_USB3_SUSPEND 141
  8334. +#define CLK_USBOTG0 142
  8335. +#define CLK_USBEHCI1 143
  8336. +#define CLK_USBEHCI0 144
  8337. +#define CLK_USBOHCI1 145
  8338. +#define CLK_USBOHCI0 146
  8339. +#define CLK_LRADC 147
  8340. +#define CLK_PCIE_AUX 148
  8341. +#define CLK_DPSS_TOP0 149
  8342. +#define CLK_DPSS_TOP1 150
  8343. +#define CLK_HDMI_24M 151
  8344. +#define CLK_HDMI_CEC 152
  8345. +#define CLK_HDMI 153
  8346. +#define CLK_DSI0 154
  8347. +#define CLK_DSI1 155
  8348. +#define CLK_BUS_DSI1 156
  8349. +#define CLK_BUS_DSI0 157
  8350. +#define CLK_VO0_TCONLCD0 158
  8351. +#define CLK_VO0_TCONLCD1 159
  8352. +#define CLK_VO1_TCONLCD0 160
  8353. +#define CLK_COMBPHY0 161
  8354. +#define CLK_COMBPHY1 162
  8355. +#define CLK_BUS_VO1_TCONLCD0 163
  8356. +#define CLK_BUS_VO0_TCONLCD1 164
  8357. +#define CLK_BUS_VO0_TCONLCD0 165
  8358. +#define CLK_TCONTV 166
  8359. +#define CLK_TCONTV1 167
  8360. +#define CLK_BUS_TCONTV1 168
  8361. +#define CLK_BUS_TCONTV 169
  8362. +#define CLK_EDP 170
  8363. +#define CLK_BUS_EDP 171
  8364. +#define CLK_LEDC 172
  8365. +#define CLK_BUS_LEDC 173
  8366. +#define CLK_CSI 174
  8367. +#define CLK_CSI_MASTER0 175
  8368. +#define CLK_CSI_MASTER1 176
  8369. +#define CLK_CSI_MASTER2 177
  8370. +#define CLK_CSI_MASTER3 178
  8371. +#define CLK_BUS_CSI 179
  8372. +#define CLK_ISP 180
  8373. +#define CLK_DSP 181
  8374. +#define CLK_CPUS_HCLK_GATE 182
  8375. +#define CLK_USB_24M 183
  8376. +#define CLK_FANOUT_50M 184
  8377. +#define CLK_FANOUT_25M 185
  8378. +#define CLK_FANOUT_16M 186
  8379. +#define CLK_FANOUT_12M 187
  8380. +#define CLK_FANOUT_24M 188
  8381. +#define CLK_CLK27M_FANOUT 189
  8382. +#define CLK_CLK_FANOUT 190
  8383. +#define CLK_FANOUT2 191
  8384. +#define CLK_FANOUT1 192
  8385. +#define CLK_FANOUT0 193
  8386. +
  8387. +#define CLK_MAX_NO (CLK_FANOUT0 + 1)
  8388. +
  8389. +#endif /* _DT_BINDINGS_CLK_SUN55IW3_H_ */
  8390. diff --git a/include/dt-bindings/clock/sun55iw3-displl-ccu.h b/include/dt-bindings/clock/sun55iw3-displl-ccu.h
  8391. new file mode 100644
  8392. index 000000000000..6cfc6da4005e
  8393. --- /dev/null
  8394. +++ b/include/dt-bindings/clock/sun55iw3-displl-ccu.h
  8395. @@ -0,0 +1,19 @@
  8396. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8397. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8398. +/*
  8399. + * Copyright (C) 2022 [email protected]
  8400. + */
  8401. +
  8402. +#ifndef _DT_BINDINGS_CLK_SUN55IW3_DISPLL_H_
  8403. +#define _DT_BINDINGS_CLK_SUN55IW3_DISPLL_H_
  8404. +
  8405. +#define CLK_PLL_CPU0 0
  8406. +#define CLK_PLL_CPU1 1
  8407. +#define CLK_PLL_CPU2 2
  8408. +#define CLK_PLL_CPU3 3
  8409. +#define CLK_PLL_CPUA 4
  8410. +#define CLK_PLL_CPUB 5
  8411. +
  8412. +#define CLK_DISPLL_MAX_NO (CLK_PLL_CPUB + 1)
  8413. +
  8414. +#endif /* _DT_BINDINGS_CLK_SUN55IW3_H_ */
  8415. diff --git a/include/dt-bindings/clock/sun55iw3-mcu-ccu.h b/include/dt-bindings/clock/sun55iw3-mcu-ccu.h
  8416. new file mode 100644
  8417. index 000000000000..130ec207d24b
  8418. --- /dev/null
  8419. +++ b/include/dt-bindings/clock/sun55iw3-mcu-ccu.h
  8420. @@ -0,0 +1,58 @@
  8421. +/* SPDX-License-Identifier: GPL-2.0 */
  8422. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8423. +/*
  8424. + * Copyright (c) 2022 [email protected]
  8425. + */
  8426. +
  8427. +#ifndef _DT_BINDINGS_CLK_SUN55IW3_MCU_CCU_H_
  8428. +#define _DT_BINDINGS_CLK_SUN55IW3_MCU_CCU_H_
  8429. +
  8430. +#define CLK_PLL_MCU_AUDIO1 0
  8431. +#define CLK_PLL_MCU_AUDIO1_DIV2 1
  8432. +#define CLK_PLL_MCU_AUDIO1_DIV5 2
  8433. +#define CLK_PLL_MCU_AUDIO_OUT 3
  8434. +#define CLK_DSP_DSP 4
  8435. +#define CLK_MCU_I2S0 5
  8436. +#define CLK_MCU_I2S1 6
  8437. +#define CLK_MCU_I2S2 7
  8438. +#define CLK_MCU_I2S3 8
  8439. +#define CLK_MCU_I2S3_ASRC 9
  8440. +#define CLK_BUS_MCU_I2S0 10
  8441. +#define CLK_BUS_MCU_I2S1 11
  8442. +#define CLK_BUS_MCU_I2S2 12
  8443. +#define CLK_BUS_MCU_I2S3 13
  8444. +#define CLK_MCU_OWA_TX 14
  8445. +#define CLK_MCU_OWA_RX 15
  8446. +#define CLK_BUS_MCU_OWA 16
  8447. +#define CLK_MCU_DMIC 17
  8448. +#define CLK_BUS_MCU_DMIC 18
  8449. +#define CLK_MCU_AUDIO_CODEC_DAC 19
  8450. +#define CLK_MCU_AUDIO_CODEC_ADC 20
  8451. +#define CLK_BUS_MCU_AUDIO_CODEC 21
  8452. +#define CLK_BUS_DSP_MSG 22
  8453. +#define CLK_BUS_DSP_CFG 23
  8454. +#define CLK_BUS_MCU_NPU_ACLK 24
  8455. +#define CLK_BUS_MCU_NPU_HCLK 25
  8456. +#define CLK_MCU_TIMER0 27
  8457. +#define CLK_MCU_TIMER1 28
  8458. +#define CLK_MCU_TIMER2 29
  8459. +#define CLK_MCU_TIMER3 30
  8460. +#define CLK_MCU_TIMER4 31
  8461. +#define CLK_MCU_TIMER5 32
  8462. +#define CLK_BUS_MCU_TIMER 33
  8463. +#define CLK_BUS_MCU_DMA 34
  8464. +#define CLK_BUS_MCU_TZMA0 35
  8465. +#define CLK_BUS_MCU_TZMA1 36
  8466. +#define CLK_BUS_PUBSRAM 37
  8467. +#define CLK_BUS_MCU_MBUS 38
  8468. +#define CLK_BUS_MCU_DMA_MBUS 39
  8469. +#define CLK_BUS_RV 40
  8470. +#define CLK_BUS_RV_CFG 41
  8471. +#define CLK_BUS_MCU_RISCV_MSG 42
  8472. +#define CLK_MCU_PWM 43
  8473. +#define CLK_BUS_MCU_PWM 44
  8474. +#define CLK_BUS_MCU_AHB_AUTO 45
  8475. +
  8476. +#define CLK_MCU_NUMBER (CLK_BUS_MCU_AHB_AUTO + 1)
  8477. +
  8478. +#endif /* _DT_BINDINGS_CLK_SUN55IW3_MCU_CCU_H_ */
  8479. diff --git a/include/dt-bindings/clock/sun55iw3-r-ccu.h b/include/dt-bindings/clock/sun55iw3-r-ccu.h
  8480. new file mode 100644
  8481. index 000000000000..e6949fcab52c
  8482. --- /dev/null
  8483. +++ b/include/dt-bindings/clock/sun55iw3-r-ccu.h
  8484. @@ -0,0 +1,40 @@
  8485. +/* SPDX-License-Identifier: GPL-2.0 */
  8486. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8487. +/*
  8488. + * Copyright (c) 2022 [email protected]
  8489. + */
  8490. +
  8491. +#ifndef _DT_BINDINGS_CLK_SUN55IW3_R_CCU_H_
  8492. +#define _DT_BINDINGS_CLK_SUN55IW3_R_CCU_H_
  8493. +
  8494. +#define CLK_R_AHB 0
  8495. +#define CLK_R_APBS0 1
  8496. +#define CLK_R_APBS1 2
  8497. +#define CLK_R_TIMER0 3
  8498. +#define CLK_R_TIMER1 4
  8499. +#define CLK_R_TIMER2 5
  8500. +#define CLK_BUS_R_TIMER 6
  8501. +#define CLK_BUS_R_TWD 7
  8502. +#define CLK_R_PWM 8
  8503. +#define CLK_BUS_R_PWM 9
  8504. +#define CLK_R_SPI 11
  8505. +#define CLK_BUS_R_SPI 12
  8506. +#define CLK_BUS_R_SPLOCK 13
  8507. +#define CLK_BUS_R_MBOX 14
  8508. +#define CLK_BUS_R_UART1 15
  8509. +#define CLK_BUS_R_UART0 16
  8510. +#define CLK_BUS_R_TWI2 17
  8511. +#define CLK_BUS_R_TWI1 18
  8512. +#define CLK_BUS_R_TWI0 19
  8513. +#define CLK_R_PPU1 20
  8514. +#define CLK_R_PPU 21
  8515. +#define CLK_BUS_R_TZMA 22
  8516. +#define CLK_BUS_R_BIST 23
  8517. +#define CLK_R_IRRX 24
  8518. +#define CLK_BUS_R_IRRX 25
  8519. +#define CLK_DMA_CLKEN_SW 26
  8520. +#define CLK_BUS_R_RTC 27
  8521. +#define CLK_BUS_R_CPUCFG 28
  8522. +#define CLK_R_NUMBER (CLK_BUS_R_CPUCFG + 1)
  8523. +
  8524. +#endif /* _DT_BINDINGS_CLK_SUN55IW3_R_CCU_H_ */
  8525. diff --git a/include/dt-bindings/clock/sun55iw3-rtc.h b/include/dt-bindings/clock/sun55iw3-rtc.h
  8526. new file mode 100644
  8527. index 000000000000..ca77ca7e5ec6
  8528. --- /dev/null
  8529. +++ b/include/dt-bindings/clock/sun55iw3-rtc.h
  8530. @@ -0,0 +1,24 @@
  8531. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8532. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8533. +/*
  8534. + * Copyright (C) 2022 [email protected]
  8535. + */
  8536. +
  8537. +#ifndef _DT_BINDINGS_CLK_SUN55IW3_RTC_H_
  8538. +#define _DT_BINDINGS_CLK_SUN55IW3_RTC_H_
  8539. +
  8540. +
  8541. +#define CLK_DCXO24M_OUT 0
  8542. +#define CLK_IOSC 1
  8543. +#define CLK_EXT32K_GATE 2
  8544. +#define CLK_IOSC_DIV32K 3
  8545. +#define CLK_OSC32K 4
  8546. +#define CLK_DCXO24M_DIV32K 5
  8547. +#define CLK_RTC32K 6
  8548. +#define CLK_RTC_1K 7
  8549. +#define CLK_OSC32K_OUT 8
  8550. +#define CLK_RTC_SPI 9
  8551. +
  8552. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  8553. +
  8554. +#endif /* _DT_BINDINGS_CLK_SUN55IW3_RTC_H_ */
  8555. diff --git a/include/dt-bindings/clock/sun55iw5-ccu.h b/include/dt-bindings/clock/sun55iw5-ccu.h
  8556. new file mode 100644
  8557. index 000000000000..4b3345fc9e91
  8558. --- /dev/null
  8559. +++ b/include/dt-bindings/clock/sun55iw5-ccu.h
  8560. @@ -0,0 +1,151 @@
  8561. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8562. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8563. +/*
  8564. + * Copyright (C) 2023 [email protected]
  8565. + */
  8566. +
  8567. +#ifndef _DT_BINDINGS_CLK_SUN55IW5_H_
  8568. +#define _DT_BINDINGS_CLK_SUN55IW5_H_
  8569. +
  8570. +#define CLK_PLL_DDR 0
  8571. +#define CLK_PLL_PERI0_PARENT 1
  8572. +#define CLK_PLL_PERI0_2X 2
  8573. +#define CLK_PERI0_DIV3 3
  8574. +#define CLK_PLL_PERI0_800M 4
  8575. +#define CLK_PLL_PERI0_480M 5
  8576. +#define CLK_PLL_PERI0_600M 6
  8577. +#define CLK_PLL_PERI0_400M 7
  8578. +#define CLK_PLL_PERI0_300M 8
  8579. +#define CLK_PLL_PERI0_200M 9
  8580. +#define CLK_PLL_PERI0_160M 10
  8581. +#define CLK_PLL_PERI0_16M 11
  8582. +#define CLK_PLL_PERI0_150M 12
  8583. +#define CLK_PLL_PERI0_25M 13
  8584. +#define CLK_PLL_PERI1_PARENT 14
  8585. +#define CLK_PLL_PERI1_2X 15
  8586. +#define CLK_PLL_PERI1_800M 16
  8587. +#define CLK_PLL_PERI1_480M 17
  8588. +#define CLK_PLL_PERI1_600M 18
  8589. +#define CLK_PLL_PERI1_400M 19
  8590. +#define CLK_PLL_PERI1_300M 20
  8591. +#define CLK_PLL_PERI1_200M 21
  8592. +#define CLK_PLL_PERI1_160M 22
  8593. +#define CLK_PLL_PERI1_150M 23
  8594. +#define CLK_PLL_GPU 24
  8595. +#define CLK_PLL_VIDEO0_4X 25
  8596. +#define CLK_PLL_VIDEO2_4X 26
  8597. +#define CLK_PLL_VE 27
  8598. +#define CLK_PLL_ADC 28
  8599. +#define CLK_PLL_VIDEO3_4X 29
  8600. +#define CLK_AHB 30
  8601. +#define CLK_APB0 31
  8602. +#define CLK_APB1 32
  8603. +#define CLK_MBUS 33
  8604. +#define CLK_TRACE 34
  8605. +#define CLK_GIC 35
  8606. +#define CLK_TVDISP_AHB_GATE 36
  8607. +#define CLK_TVCAP_AHB_GATE 37
  8608. +#define CLK_TVFE_AHB_GATE 38
  8609. +#define CLK_SMHC2_AHB_GATE 39
  8610. +#define CLK_SMHC1_AHB_GATE 40
  8611. +#define CLK_SMHC0_AHB_GATE 41
  8612. +#define CLK_USB2_AHB_GATE 42
  8613. +#define CLK_GMAC_AHB_GATE 43
  8614. +#define CLK_GPU_AHB_GATE 44
  8615. +#define CLK_TVDISP_MBUS_GATE 45
  8616. +#define CLK_TVCAP_MBUS_GATE 46
  8617. +#define CLK_TVFE_MBUS_GATE 47
  8618. +#define CLK_GPU_MBUS_GATE 48
  8619. +#define CLK_GPU 49
  8620. +#define CLK_CE 50
  8621. +#define CLK_CE_SYS 51
  8622. +#define CLK_BUS_CE 52
  8623. +#define CLK_VE_CORE 53
  8624. +#define CLK_AV1 54
  8625. +#define CLK_VE 55
  8626. +#define CLK_DMA 56
  8627. +#define CLK_MSGBOX 57
  8628. +#define CLK_SPINLOCK 58
  8629. +#define CLK_TIMER0 59
  8630. +#define CLK_TIMER1 60
  8631. +#define CLK_TIMER2 61
  8632. +#define CLK_BUS_TIMER0 62
  8633. +#define CLK_DBGSYS 63
  8634. +#define CLK_PWM 64
  8635. +#define CLK_IOMMU 65
  8636. +#define CLK_DRAM 66
  8637. +#define CLK_MBUS_AV1 67
  8638. +#define CLK_MBUS_CE 68
  8639. +#define CLK_MBUS_VE3 69
  8640. +#define CLK_MBUS_DMA 70
  8641. +#define CLK_MBUS_DRAM 71
  8642. +#define CLK_SMHC0 72
  8643. +#define CLK_SMHC1 73
  8644. +#define CLK_SMHC2 74
  8645. +#define CLK_BUS_SMHC2 75
  8646. +#define CLK_BUS_SMHC1 76
  8647. +#define CLK_BUS_SMHC0 77
  8648. +#define CLK_BUS_UART3 78
  8649. +#define CLK_BUS_UART2 79
  8650. +#define CLK_BUS_UART1 80
  8651. +#define CLK_BUS_UART0 81
  8652. +#define CLK_TWI4 82
  8653. +#define CLK_TWI3 83
  8654. +#define CLK_TWI2 84
  8655. +#define CLK_TWI1 85
  8656. +#define CLK_TWI0 86
  8657. +#define CLK_SPI0 87
  8658. +#define CLK_SPI1 88
  8659. +#define CLK_SPI2 89
  8660. +#define CLK_BUS_SPI2 90
  8661. +#define CLK_BUS_SPI1 91
  8662. +#define CLK_BUS_SPI0 92
  8663. +#define CLK_GMAC0_25M 93
  8664. +#define CLK_GMAC0 94
  8665. +#define CLK_I2SPCM0 95
  8666. +#define CLK_BUS_I2SPCM0 96
  8667. +#define CLK_SPDIF1 97
  8668. +#define CLK_SPDIF0 98
  8669. +#define CLK_SPDIF0_RX 99
  8670. +#define CLK_SPDIF0_TX 100
  8671. +#define CLK_SPDIF1_RX 101
  8672. +#define CLK_SPDIF1_TX 102
  8673. +#define CLK_AUDIO_CODEC_DAC_1X 103
  8674. +#define CLK_AUDIO_CODEC_ADC_1X 104
  8675. +#define CLK_AUDIO_CODEC 105
  8676. +#define CLK_USB0 106
  8677. +#define CLK_USB1 107
  8678. +#define CLK_USB2 108
  8679. +#define CLK_USBOTG 109
  8680. +#define CLK_USBEHCI2 110
  8681. +#define CLK_USBEHCI1 111
  8682. +#define CLK_USBEHCI0 112
  8683. +#define CLK_USBOHCI2 113
  8684. +#define CLK_USBOHCI1 114
  8685. +#define CLK_USBOHCI0 115
  8686. +#define CLK_TVFE_AXI 116
  8687. +#define CLK_ADC 117
  8688. +#define CLK_TSDM_TS 118
  8689. +#define CLK_DTMB_CLK120M 119
  8690. +#define CLK_TVFE_1296M 120
  8691. +#define CLK_I2H 121
  8692. +#define CLK_AUDIO_CPU 122
  8693. +#define CLK_AUDIO_UMAC 123
  8694. +#define CLK_AUDIO_IHB 124
  8695. +#define CLK_MPG0 125
  8696. +#define CLK_MPG1 126
  8697. +#define CLK_DEMOD 127
  8698. +#define CLK_TCD3 128
  8699. +#define CLK_VINCAP_DMA 129
  8700. +#define CLK_HDMI_AUDIO 130
  8701. +#define CLK_TVCAP 131
  8702. +#define CLK_DEINT 132
  8703. +#define CLK_PANEL 133
  8704. +#define CLK_SVP_DTL 134
  8705. +#define CLK_KSC 135
  8706. +#define CLK_AFBD 136
  8707. +#define CLK_DISP 137
  8708. +
  8709. +#define CLK_MAX_NO (CLK_DISP + 1)
  8710. +
  8711. +#endif /* _DT_BINDINGS_CLK_SUN55IW5_H_ */
  8712. diff --git a/include/dt-bindings/clock/sun55iw5-r-ccu.h b/include/dt-bindings/clock/sun55iw5-r-ccu.h
  8713. new file mode 100644
  8714. index 000000000000..e8cb01ecc264
  8715. --- /dev/null
  8716. +++ b/include/dt-bindings/clock/sun55iw5-r-ccu.h
  8717. @@ -0,0 +1,40 @@
  8718. +/* SPDX-License-Identifier: GPL-2.0 */
  8719. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8720. +/*
  8721. + * Copyright (c) 2023 [email protected]
  8722. + */
  8723. +
  8724. +#ifndef _DT_BINDINGS_CLK_SUN55IW5_R_CCU_H_
  8725. +#define _DT_BINDINGS_CLK_SUN55IW5_R_CCU_H_
  8726. +
  8727. +#define CLK_R_TIMER0 0
  8728. +#define CLK_R_TIMER1 1
  8729. +#define CLK_R_TIMER2 2
  8730. +#define CLK_R_TIMER 3
  8731. +#define CLK_R_EDID 4
  8732. +#define CLK_WDT1 5
  8733. +#define CLK_R_PWM 6
  8734. +#define CLK_BUS_R_PWM 7
  8735. +#define CLK_R_UART0 8
  8736. +#define CLK_R_TWI1 9
  8737. +#define CLK_R_TWI0 10
  8738. +#define CLK_R_PPU 11
  8739. +#define CLK_R_TZMA 12
  8740. +#define CLK_R_CPUS_BIST 13
  8741. +#define CLK_R_IRRX 14
  8742. +#define CLK_BUS_R_IRRX 15
  8743. +#define CLK_R_GPADC 16
  8744. +#define CLK_BUS_R_GPADC 17
  8745. +#define CLK_R_THS 18
  8746. +#define CLK_R_RTC 19
  8747. +#define CLK_R_CPUCFG 20
  8748. +#define CLK_VDD_USB2CPUS 21
  8749. +#define CLK_VDD_SYS2USB 22
  8750. +#define CLK_VDD_SYS2CPUS 23
  8751. +#define CLK_TT_AUTO 24
  8752. +#define CLK_CPU_ICACHE_AUTO 25
  8753. +#define CLK_AHBS_AUTO_CLK 26
  8754. +
  8755. +#define CLK_R_NUMBER (CLK_AHBS_AUTO_CLK + 1)
  8756. +
  8757. +#endif /* _DT_BINDINGS_CLK_SUN55IW5_R_CCU_H_ */
  8758. diff --git a/include/dt-bindings/clock/sun55iw5-rtc.h b/include/dt-bindings/clock/sun55iw5-rtc.h
  8759. new file mode 100644
  8760. index 000000000000..b3bd851234d4
  8761. --- /dev/null
  8762. +++ b/include/dt-bindings/clock/sun55iw5-rtc.h
  8763. @@ -0,0 +1,24 @@
  8764. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8765. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8766. +/*
  8767. + * Copyright (C) 2023 [email protected]
  8768. + */
  8769. +
  8770. +#ifndef _DT_BINDINGS_CLK_SUN55IW5_RTC_H_
  8771. +#define _DT_BINDINGS_CLK_SUN55IW5_RTC_H_
  8772. +
  8773. +
  8774. +#define CLK_DCXO24M_OUT 0
  8775. +#define CLK_IOSC 1
  8776. +#define CLK_EXT32K_GATE 2
  8777. +#define CLK_IOSC_DIV32K 3
  8778. +#define CLK_OSC32K 4
  8779. +#define CLK_DCXO24M_DIV32K 5
  8780. +#define CLK_RTC32K 6
  8781. +#define CLK_RTC_1K 7
  8782. +#define CLK_OSC32K_OUT 8
  8783. +#define CLK_RTC_SPI 9
  8784. +
  8785. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  8786. +
  8787. +#endif /* _DT_BINDINGS_CLK_SUN55IW5_RTC_H_ */
  8788. diff --git a/include/dt-bindings/clock/sun55iw6-ccu.h b/include/dt-bindings/clock/sun55iw6-ccu.h
  8789. new file mode 100644
  8790. index 000000000000..38af72db55f9
  8791. --- /dev/null
  8792. +++ b/include/dt-bindings/clock/sun55iw6-ccu.h
  8793. @@ -0,0 +1,227 @@
  8794. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  8795. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  8796. +/*
  8797. + * Copyright (C) 2023 [email protected]
  8798. + */
  8799. +
  8800. +#ifndef _DT_BINDINGS_CLK_SUN55IW6_H_
  8801. +#define _DT_BINDINGS_CLK_SUN55IW6_H_
  8802. +
  8803. +#define CLK_PLL_DDR 0
  8804. +#define CLK_PLL_PERI0_PARENT 1
  8805. +#define CLK_PLL_PERI0_2X 2
  8806. +#define CLK_PERI0_DIV3 3
  8807. +#define CLK_PLL_PERI0_800M 4
  8808. +#define CLK_PLL_PERI0_480M 5
  8809. +#define CLK_PLL_PERI0_600M 6
  8810. +#define CLK_PLL_PERI0_400M 7
  8811. +#define CLK_PLL_PERI0_300M 8
  8812. +#define CLK_PLL_PERI0_200M 9
  8813. +#define CLK_PLL_PERI0_160M 10
  8814. +#define CLK_PLL_PERI0_16M 11
  8815. +#define CLK_PLL_PERI0_150M 12
  8816. +#define CLK_PLL_PERI0_25M 13
  8817. +#define CLK_PLL_PERI1_PARENT 14
  8818. +#define CLK_PLL_PERI1_2X 15
  8819. +#define CLK_PLL_PERI1_800M 16
  8820. +#define CLK_PLL_PERI1_480M 17
  8821. +#define CLK_PLL_PERI1_600M 18
  8822. +#define CLK_PLL_PERI1_400M 19
  8823. +#define CLK_PLL_PERI1_300M 20
  8824. +#define CLK_PLL_PERI1_200M 21
  8825. +#define CLK_PLL_PERI1_160M 22
  8826. +#define CLK_PLL_PERI1_150M 23
  8827. +#define CLK_PLL_VIDEO0_4X 24
  8828. +#define CLK_PLL_VIDEO1_4X 25
  8829. +#define CLK_PLL_VE 26
  8830. +#define CLK_PLL_NPU_4X 27
  8831. +#define CLK_AHB 28
  8832. +#define CLK_APB0 29
  8833. +#define CLK_APB1 30
  8834. +#define CLK_APB_UART 31
  8835. +#define CLK_TRACE 32
  8836. +#define CLK_GIC 33
  8837. +#define CLK_ITS0_ACLK 34
  8838. +#define CLK_ITS0_HCLK 35
  8839. +#define CLK_NSI 36
  8840. +#define CLK_NSI_CFG 37
  8841. +#define CLK_MBUS 38
  8842. +#define CLK_IOMMU 39
  8843. +#define CLK_GMAC1_MBUS_GATE 40
  8844. +#define CLK_GMAC0_MBUS_GATE 41
  8845. +#define CLK_ISP_MBUS_GATE 42
  8846. +#define CLK_CSI_MBUS_GATE 43
  8847. +#define CLK_NAND_MBUS_GATE 44
  8848. +#define CLK_DMA1_MBUS_GATE 45
  8849. +#define CLK_CE_MBUS_GATE 46
  8850. +#define CLK_VE_MBUS_GATE 47
  8851. +#define CLK_DMA0_MBUS_GATE 48
  8852. +#define CLK_DMA0 49
  8853. +#define CLK_DMA1 50
  8854. +#define CLK_SPINLOCK 51
  8855. +#define CLK_MSGBOX0 52
  8856. +#define CLK_MSGBOX_CORE0 53
  8857. +#define CLK_MSGBOX_CORE1 54
  8858. +#define CLK_MSGBOX_CORE2 55
  8859. +#define CLK_MSGBOX_CORE3 56
  8860. +#define CLK_MSGBOX_RV 57
  8861. +#define CLK_PWM0 58
  8862. +#define CLK_PWM1 59
  8863. +#define CLK_PWM2 60
  8864. +#define CLK_DBGSYS 61
  8865. +#define CLK_SYSDAP 62
  8866. +#define CLK_TIMER0 63
  8867. +#define CLK_TIMER1 64
  8868. +#define CLK_TIMER2 65
  8869. +#define CLK_TIMER3 66
  8870. +#define CLK_TIMER4 67
  8871. +#define CLK_TIMER5 68
  8872. +#define CLK_TIMER6 69
  8873. +#define CLK_TIMER7 70
  8874. +#define CLK_BUS_TIMER 71
  8875. +#define CLK_TIMER0_RV 72
  8876. +#define CLK_TIMER1_RV 73
  8877. +#define CLK_TIMER2_RV 74
  8878. +#define CLK_TIMER3_RV 75
  8879. +#define CLK_RV_BUS_TIMER 76
  8880. +#define CLK_DE 77
  8881. +#define CLK_DE0 78
  8882. +#define CLK_G2D 79
  8883. +#define CLK_BUS_G2D 80
  8884. +#define CLK_VE 81
  8885. +#define CLK_BUS_VE 82
  8886. +#define CLK_CE 83
  8887. +#define CLK_CE_SYS 84
  8888. +#define CLK_BUS_CE 85
  8889. +#define CLK_NPU 86
  8890. +#define CLK_NPU_TZMA 87
  8891. +#define CLK_BUS_NPU 88
  8892. +#define CLK_RV_CORE 89
  8893. +#define CLK_RV_TS 90
  8894. +#define CLK_RV_CFG 91
  8895. +#define CLK_DRAM 92
  8896. +#define CLK_BUS_DRAM 93
  8897. +#define CLK_NAND0 94
  8898. +#define CLK_NAND0_CLK2X 95
  8899. +#define CLK_BUS_NAND0 96
  8900. +#define CLK_SMHC0 97
  8901. +#define CLK_BUS_SMHC0 98
  8902. +#define CLK_SMHC1 99
  8903. +#define CLK_BUS_SMHC1 100
  8904. +#define CLK_SMHC2 101
  8905. +#define CLK_BUS_SMHC2 102
  8906. +#define CLK_BUS_UART0 103
  8907. +#define CLK_BUS_UART1 104
  8908. +#define CLK_BUS_UART2 105
  8909. +#define CLK_BUS_UART3 106
  8910. +#define CLK_BUS_UART4 107
  8911. +#define CLK_BUS_UART5 108
  8912. +#define CLK_BUS_UART6 109
  8913. +#define CLK_BUS_UART7 110
  8914. +#define CLK_BUS_UART8 111
  8915. +#define CLK_BUS_UART9 112
  8916. +#define CLK_BUS_UART10 113
  8917. +#define CLK_BUS_UART11 114
  8918. +#define CLK_BUS_UART12 115
  8919. +#define CLK_BUS_UART13 116
  8920. +#define CLK_BUS_UART14 117
  8921. +#define CLK_TWI0 118
  8922. +#define CLK_TWI1 119
  8923. +#define CLK_TWI2 120
  8924. +#define CLK_TWI3 121
  8925. +#define CLK_TWI4 122
  8926. +#define CLK_TWI5 123
  8927. +#define CLK_TWI6 124
  8928. +#define CLK_SPI0 125
  8929. +#define CLK_BUS_SPI0 126
  8930. +#define CLK_SPI1 127
  8931. +#define CLK_BUS_SPI1 128
  8932. +#define CLK_SPI2 129
  8933. +#define CLK_BUS_SPI2 130
  8934. +#define CLK_SPIF 131
  8935. +#define CLK_BUS_SPIF 132
  8936. +#define CLK_SPI3 133
  8937. +#define CLK_BUS_SPI3 134
  8938. +#define CLK_SPI4 135
  8939. +#define CLK_BUS_SPI4 136
  8940. +#define CLK_GPADC0 137
  8941. +#define CLK_BUS_GPADC0 138
  8942. +#define CLK_GPADC1 139
  8943. +#define CLK_BUS_GPADC1 140
  8944. +#define CLK_GPADC2 141
  8945. +#define CLK_BUS_GPADC2 142
  8946. +#define CLK_GPADC3 143
  8947. +#define CLK_BUS_GPADC3 144
  8948. +#define CLK_THS 145
  8949. +#define CLK_IRRX0 146
  8950. +#define CLK_BUS_IRRX0 147
  8951. +#define CLK_IRTX 148
  8952. +#define CLK_BUS_IRTX 149
  8953. +#define CLK_LRADC 150
  8954. +#define CLK_TPADC_24M 151
  8955. +#define CLK_TPADC 152
  8956. +#define CLK_LBC 153
  8957. +#define CLK_LBC_NSI_AHB 154
  8958. +#define CLK_BUS_LBC 155
  8959. +#define CLK_IRRX1 156
  8960. +#define CLK_BUS_IRRX1 157
  8961. +#define CLK_IRRX2 158
  8962. +#define CLK_BUS_IRRX2 159
  8963. +#define CLK_IRRX3 160
  8964. +#define CLK_BUS_IRRX3 161
  8965. +#define CLK_I2SPCM0 162
  8966. +#define CLK_BUS_I2SPCM0 163
  8967. +#define CLK_I2SPCM1 164
  8968. +#define CLK_BUS_I2SPCM1 165
  8969. +#define CLK_I2SPCM2 166
  8970. +#define CLK_BUS_I2SPCM2 167
  8971. +#define CLK_I2SPCM3 168
  8972. +#define CLK_BUS_I2SPCM3 169
  8973. +#define CLK_OWA_TX 170
  8974. +#define CLK_OWA_RX 171
  8975. +#define CLK_OWA 172
  8976. +#define CLK_DMIC 173
  8977. +#define CLK_BUS_DMIC 174
  8978. +#define CLK_AUDIO_CODEC_DAC_1X 175
  8979. +#define CLK_AUDIO_CODEC 176
  8980. +#define CLK_USB 177
  8981. +#define CLK_USB20_0_DEVICE 178
  8982. +#define CLK_USB20_0_HOST_EHCI 179
  8983. +#define CLK_USB20_0_HOST_OHCI 180
  8984. +#define CLK_USB1 181
  8985. +#define CLK_USB20_1_HOST_EHCI 182
  8986. +#define CLK_USB20_1_HOST_OHCI 183
  8987. +#define CLK_USB2_REF 184
  8988. +#define CLK_USB2_SUSPEND 185
  8989. +#define CLK_USB3_REF 186
  8990. +#define CLK_USB30 187
  8991. +#define CLK_PCIE_REF_AUX 188
  8992. +#define CLK_PCIE_SLV 189
  8993. +#define CLK_SERDES_PHY_CFG 190
  8994. +#define CLK_SERDES_PHY_REF 191
  8995. +#define CLK_SERDES_AXI 192
  8996. +#define CLK_GMAC0_PHY 193
  8997. +#define CLK_GMAC0_PTP 194
  8998. +#define CLK_GMAC0 195
  8999. +#define CLK_GMAC1_PHY 196
  9000. +#define CLK_GMAC1_PTP 197
  9001. +#define CLK_GMAC1 198
  9002. +#define CLK_GMAC_NSI 199
  9003. +#define CLK_VO0_TCONLCD0 200
  9004. +#define CLK_BUS_VO0_TCONLCD0 201
  9005. +#define CLK_DSI0 202
  9006. +#define CLK_BUS_DSI0 203
  9007. +#define CLK_VO0_COMBPHY0 204
  9008. +#define CLK_DPSS 205
  9009. +#define CLK_LEDC 206
  9010. +#define CLK_BUS_LEDC 207
  9011. +#define CLK_CSI_MASTER0 208
  9012. +#define CLK_CSI_MASTER1 209
  9013. +#define CLK_CSI_MASTER2 210
  9014. +#define CLK_CSI_MASTER3 211
  9015. +#define CLK_CSI 212
  9016. +#define CLK_BUS_CSI 213
  9017. +#define CLK_ISP 214
  9018. +#define CLK_BUS_ISP 215
  9019. +
  9020. +#endif /* _DT_BINDINGS_CLK_SUN55IW6_H_ */
  9021. diff --git a/include/dt-bindings/clock/sun55iw6-r-ccu.h b/include/dt-bindings/clock/sun55iw6-r-ccu.h
  9022. new file mode 100644
  9023. index 000000000000..c165d9d6aa0c
  9024. --- /dev/null
  9025. +++ b/include/dt-bindings/clock/sun55iw6-r-ccu.h
  9026. @@ -0,0 +1,41 @@
  9027. +/* SPDX-License-Identifier: GPL-2.0 */
  9028. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9029. +/*
  9030. + * Copyright (c) 2023 [email protected]
  9031. + */
  9032. +
  9033. +#ifndef _DT_BINDINGS_CLK_SUN55IW6_R_CCU_H_
  9034. +#define _DT_BINDINGS_CLK_SUN55IW6_R_CCU_H_
  9035. +
  9036. +#define CLK_R_TIMER0 0
  9037. +#define CLK_R_TIMER1 1
  9038. +#define CLK_R_TIMER2 2
  9039. +#define CLK_R_TIMER3 3
  9040. +#define CLK_R_TIMER 4
  9041. +#define CLK_R_TWD 5
  9042. +#define CLK_R_PWM 6
  9043. +#define CLK_R_BUS_PWM 7
  9044. +#define CLK_R_SPI 8
  9045. +#define CLK_R_BUS_SPI 9
  9046. +#define CLK_R_MBOX 10
  9047. +#define CLK_R_UART1 11
  9048. +#define CLK_R_UART0 12
  9049. +#define CLK_R_TWI1 13
  9050. +#define CLK_R_TWI0 14
  9051. +#define CLK_R_PPU 15
  9052. +#define CLK_R_TZMA 16
  9053. +#define CLK_R_CPUS_BIST 17
  9054. +#define CLK_R_IRRX 18
  9055. +#define CLK_R_BUS_IRRX 19
  9056. +#define CLK_RTC 20
  9057. +#define CLK_R_CPUCFG 21
  9058. +#define CLK_VDD_USB2CPUS 22
  9059. +#define CLK_VDD_SYS2CPUS 23
  9060. +#define CLK_VDD_DDR 24
  9061. +#define CLK_TT_AUTO 25
  9062. +#define CLK_CPU_ICACHE_AUTO 26
  9063. +#define CLK_AHBS_AUTO_CLK 27
  9064. +
  9065. +#define CLK_R_NUMBER (CLK_AHBS_AUTO_CLK + 1)
  9066. +
  9067. +#endif /* _DT_BINDINGS_CLK_SUN55IW6_R_CCU_H_ */
  9068. diff --git a/include/dt-bindings/clock/sun55iw6-rtc.h b/include/dt-bindings/clock/sun55iw6-rtc.h
  9069. new file mode 100644
  9070. index 000000000000..2defc93cfc8a
  9071. --- /dev/null
  9072. +++ b/include/dt-bindings/clock/sun55iw6-rtc.h
  9073. @@ -0,0 +1,24 @@
  9074. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9075. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9076. +/*
  9077. + * Copyright (C) 2023 [email protected]
  9078. + */
  9079. +
  9080. +#ifndef _DT_BINDINGS_CLK_SUN55IW6_RTC_H_
  9081. +#define _DT_BINDINGS_CLK_SUN55IW6_RTC_H_
  9082. +
  9083. +
  9084. +#define CLK_DCXO24M_OUT 0
  9085. +#define CLK_IOSC 1
  9086. +#define CLK_EXT32K_GATE 2
  9087. +#define CLK_IOSC_DIV32K 3
  9088. +#define CLK_OSC32K 4
  9089. +#define CLK_DCXO24M_DIV32K 5
  9090. +#define CLK_RTC32K 6
  9091. +#define CLK_RTC_1K 7
  9092. +#define CLK_OSC32K_OUT 8
  9093. +#define CLK_RTC_SPI 9
  9094. +
  9095. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  9096. +
  9097. +#endif /* _DT_BINDINGS_CLK_SUN55IW6_RTC_H_ */
  9098. diff --git a/include/dt-bindings/clock/sun60iw1-ccu.h b/include/dt-bindings/clock/sun60iw1-ccu.h
  9099. new file mode 100644
  9100. index 000000000000..31719f802d77
  9101. --- /dev/null
  9102. +++ b/include/dt-bindings/clock/sun60iw1-ccu.h
  9103. @@ -0,0 +1,256 @@
  9104. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9105. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9106. +/*
  9107. + * Copyright (C) 2022 [email protected]
  9108. + */
  9109. +
  9110. +#ifndef _DT_BINDINGS_CLK_SUN60IW1_H_
  9111. +#define _DT_BINDINGS_CLK_SUN60IW1_H_
  9112. +
  9113. +#define CLK_PLL_REF 0
  9114. +#define CLK_PLL_DDR 1
  9115. +#define CLK_PLL_PERI0 2
  9116. +#define CLK_PLL_PERI0_2X 3
  9117. +#define CLK_PERI0_DIV3 4
  9118. +#define CLK_PLL_PERI0_800M 5
  9119. +#define CLK_PLL_PERI0_480M 6
  9120. +#define CLK_PLL_PERI0_600M 7
  9121. +#define CLK_PLL_PERI0_400M 8
  9122. +#define CLK_PLL_PERI0_300M 9
  9123. +#define CLK_PLL_PERI0_200M 10
  9124. +#define CLK_PLL_PERI0_160M 11
  9125. +#define CLK_PLL_PERI0_150M 12
  9126. +#define CLK_PLL_PERI1 13
  9127. +#define CLK_PLL_PERI1_2X 14
  9128. +#define CLK_PLL_PERI1_800M 15
  9129. +#define CLK_PLL_PERI1_480M 16
  9130. +#define CLK_PLL_PERI1_600M 17
  9131. +#define CLK_PLL_PERI1_400M 18
  9132. +#define CLK_PLL_PERI1_300M 19
  9133. +#define CLK_PLL_PERI1_200M 20
  9134. +#define CLK_PLL_PERI1_160M 21
  9135. +#define CLK_PLL_PERI1_150M 22
  9136. +#define CLK_PLL_GPU0 23
  9137. +#define CLK_PLL_VIDEO0_4X 24
  9138. +#define CLK_PLL_VIDEO0_3X 25
  9139. +#define CLK_PLL_VIDEO1_4X 26
  9140. +#define CLK_PLL_VIDEO1_3X 27
  9141. +#define CLK_PLL_VIDEO2_4X 28
  9142. +#define CLK_PLL_VIDEO2_3X 29
  9143. +#define CLK_PLL_VIDEO3_4X 30
  9144. +#define CLK_PLL_VIDEO3_3X 31
  9145. +#define CLK_PLL_VE0 32
  9146. +#define CLK_PLL_VE1 33
  9147. +#define CLK_PLL_AUDIO0_4X 34
  9148. +#define CLK_PLL_NPU 35
  9149. +#define CLK_PLL_DE_4X 36
  9150. +#define CLK_PLL_DE_3X 37
  9151. +#define CLK_PLL_CCI 38
  9152. +#define CLK_AHB 39
  9153. +#define CLK_APB0 40
  9154. +#define CLK_APB1 41
  9155. +#define CLK_APB_UART 42
  9156. +#define CLK_TRACE 43
  9157. +#define CLK_CCI 44
  9158. +#define CLK_GIC0 45
  9159. +#define CLK_GIC1 46
  9160. +#define CLK_NSI 47
  9161. +#define CLK_MBUS 48
  9162. +#define CLK_MSI_LITE0 49
  9163. +#define CLK_MSI_LITE1 50
  9164. +#define CLK_VE_ENC1_MBUS 51
  9165. +#define CLK_VE_DEC_MBUS 52
  9166. +#define CLK_GMAC1_MBUS 53
  9167. +#define CLK_GMAC0_MBUS 54
  9168. +#define CLK_ISP_MBUS 55
  9169. +#define CLK_CSI_MBUS 56
  9170. +#define CLK_NAND_MBUS 57
  9171. +#define CLK_DMA1_MBUS 58
  9172. +#define CLK_CE_MBUS 59
  9173. +#define CLK_VE_ENC0_MBUS 60
  9174. +#define CLK_DMA0_MBUS 61
  9175. +#define CLK_DMA0_BUS 62
  9176. +#define CLK_DMA1_BUS 63
  9177. +#define CLK_SPINLOCK_BUS 64
  9178. +#define CLK_MSGBOX0_CLK 65
  9179. +#define CLK_MSGBOX1_CLK 66
  9180. +#define CLK_MSGBOX2_CLK 67
  9181. +#define CLK_PWM0_CLK 68
  9182. +#define CLK_PWM1_CLK 69
  9183. +#define CLK_DBGSYS_CLK 70
  9184. +#define CLK_DBGPAD_CLK 71
  9185. +#define CLK_TIMER0_CLK0 72
  9186. +#define CLK_TIMER0_CLK1 73
  9187. +#define CLK_TIMER0_CLK2 74
  9188. +#define CLK_TIMER0_CLK3 75
  9189. +#define CLK_TIMER0_CLK4 76
  9190. +#define CLK_TIMER0_CLK5 77
  9191. +#define CLK_TIMER0_CLK6 78
  9192. +#define CLK_TIMER0_CLK7 79
  9193. +#define CLK_TIMER0_CLK8 80
  9194. +#define CLK_TIMER0_CLK9 81
  9195. +#define CLK_TIMER0 82
  9196. +#define CLK_TIMER1_CLK0 83
  9197. +#define CLK_TIMER1_CLK1 84
  9198. +#define CLK_TIMER1_CLK2 85
  9199. +#define CLK_TIMER1_CLK3 86
  9200. +#define CLK_TIMER1_CLK4 87
  9201. +#define CLK_TIMER1_CLK5 88
  9202. +#define CLK_TIMER1 89
  9203. +#define CLK_DE0 90
  9204. +#define CLK_DE0_BUS 91
  9205. +#define CLK_DE1 92
  9206. +#define CLK_DE1_BUS 93
  9207. +#define CLK_DI 94
  9208. +#define CLK_DI_BUS 95
  9209. +#define CLK_G2D 96
  9210. +#define CLK_G2D_BUS 97
  9211. +#define CLK_VE_ENC0 98
  9212. +#define CLK_VE_ENC1 99
  9213. +#define CLK_VE_DEC 100
  9214. +#define CLK_VE_ENC1_BUS 101
  9215. +#define CLK_VE_ENC0_BUS 102
  9216. +#define CLK_CE 103
  9217. +#define CLK_CE_SYS 104
  9218. +#define CLK_CE_BUS 105
  9219. +#define CLK_NPU 106
  9220. +#define CLK_NPU_BUS 107
  9221. +#define CLK_AIPU 108
  9222. +#define CLK_AIPU_BUS 109
  9223. +#define CLK_GPU0 110
  9224. +#define CLK_GPU0_BUS 111
  9225. +#define CLK_DSP 112
  9226. +#define CLK_DRAM0 113
  9227. +#define CLK_DRAM0_BUS 114
  9228. +#define CLK_NAND0_CLK0 115
  9229. +#define CLK_NAND0_CLK1 116
  9230. +#define CLK_NAND0_BUS 117
  9231. +#define CLK_SMHC0 118
  9232. +#define CLK_SMHC0_24M 119
  9233. +#define CLK_SMHC0_BUS 120
  9234. +#define CLK_SMHC1 121
  9235. +#define CLK_SMHC1_BUS 122
  9236. +#define CLK_SMHC2 123
  9237. +#define CLK_SMHC2_24M 124
  9238. +#define CLK_SMHC2_BUS 125
  9239. +#define CLK_SMHC3 126
  9240. +#define CLK_SMHC3_24M 127
  9241. +#define CLK_SMHC3_BUS 128
  9242. +#define CLK_UFS_AXI 129
  9243. +#define CLK_UFS 130
  9244. +#define CLK_UART0 131
  9245. +#define CLK_UART1 132
  9246. +#define CLK_UART2 133
  9247. +#define CLK_UART3 134
  9248. +#define CLK_UART4 135
  9249. +#define CLK_UART5 136
  9250. +#define CLK_UART6 137
  9251. +#define CLK_UART7 138
  9252. +#define CLK_UART8 139
  9253. +#define CLK_TWI0 140
  9254. +#define CLK_TWI1 141
  9255. +#define CLK_TWI2 142
  9256. +#define CLK_TWI3 143
  9257. +#define CLK_TWI4 144
  9258. +#define CLK_TWI5 145
  9259. +#define CLK_TWI6 146
  9260. +#define CLK_TWI7 147
  9261. +#define CLK_TWI8 148
  9262. +#define CLK_SPI0 149
  9263. +#define CLK_SPI0_BUS 150
  9264. +#define CLK_SPI1 151
  9265. +#define CLK_SPI1_BUS 152
  9266. +#define CLK_SPI2 153
  9267. +#define CLK_SPI2_BUS 154
  9268. +#define CLK_SPIF 155
  9269. +#define CLK_SPIF_BUS 156
  9270. +#define CLK_SPIF3 157
  9271. +#define CLK_SPIF3_BUS 158
  9272. +#define CLK_SPIF4 159
  9273. +#define CLK_SPIF4_BUS 160
  9274. +#define CLK_SPIF5 161
  9275. +#define CLK_SPIF5_BUS 162
  9276. +#define CLK_SPIF6 163
  9277. +#define CLK_SPIF6_BUS 164
  9278. +#define CLK_GPADC0_24M 165
  9279. +#define CLK_GPADC0 166
  9280. +#define CLK_GPADC1_24M 167
  9281. +#define CLK_GPADC1 168
  9282. +#define CLK_THS0 169
  9283. +#define CLK_IRRX 170
  9284. +#define CLK_IRRX_BUS 171
  9285. +#define CLK_IRTX 172
  9286. +#define CLK_IRTX_BUS 173
  9287. +#define CLK_LRADC 174
  9288. +#define CLK_LBC 175
  9289. +#define CLK_LBC_BUS 176
  9290. +#define CLK_I2SPCM1 177
  9291. +#define CLK_I2SPCM1_BUS 178
  9292. +#define CLK_I2SPCM2 179
  9293. +#define CLK_I2SPCM2_ASRC 180
  9294. +#define CLK_I2SPCM2_BUS 181
  9295. +#define CLK_I2SPCM3 182
  9296. +#define CLK_I2SPCM4 183
  9297. +#define CLK_I2SPCM4_BUS 184
  9298. +#define CLK_I2SPCM5 185
  9299. +#define CLK_I2SPCM5_BUS 186
  9300. +#define CLK_SPDIF_TX 187
  9301. +#define CLK_SPDIF_RX 188
  9302. +#define CLK_SPDIF 189
  9303. +#define CLK_USB2_HOST0 190
  9304. +#define CLK_USB2_OTG0 191
  9305. +#define CLK_USB2_EHCI0 192
  9306. +#define CLK_USB2_OHCI0 193
  9307. +#define CLK_USB2_HOST1 194
  9308. +#define CLK_USB2_OHCI1 195
  9309. +#define CLK_USB2_HOST2 196
  9310. +#define CLK_USB2_EHCI2 197
  9311. +#define CLK_USB2_OHCI2 198
  9312. +#define CLK_USB2_REF 199
  9313. +#define CLK_USB3_USB2_REF 200
  9314. +#define CLK_USB3_SUSPEND 201
  9315. +#define CLK_USB3_MF 202
  9316. +#define CLK_PCIE0_AUX 203
  9317. +#define CLK_GMAC_PTP 204
  9318. +#define CLK_GMAC0_PHY 205
  9319. +#define CLK_GMAC0 206
  9320. +#define CLK_GMAC1_PHY 207
  9321. +#define CLK_GMAC1 208
  9322. +#define CLK_VO0_TCONLCD0 209
  9323. +#define CLK_VO0_TCONLCD0_BUS 210
  9324. +#define CLK_VO0_TCONLCD1 211
  9325. +#define CLK_VO0_TCONLCD1_BUS 212
  9326. +#define CLK_VO0_TCONLCD2 213
  9327. +#define CLK_VO0_TCONLCD2_BUS 214
  9328. +#define CLK_VO0_TCONLCD3 215
  9329. +#define CLK_VO0_TCONLCD3_BUS 216
  9330. +#define CLK_DSI0 217
  9331. +#define CLK_DSI0_BUS 218
  9332. +#define CLK_DSI1 219
  9333. +#define CLK_DSI1_BUS 220
  9334. +#define CLK_COMBPHY0 221
  9335. +#define CLK_COMBPHY1 222
  9336. +#define CLK_TCONTV0 223
  9337. +#define CLK_TCONTV0_BUS 224
  9338. +#define CLK_TCONTV1 225
  9339. +#define CLK_TCONTV2 226
  9340. +#define CLK_EDP_CLK0 227
  9341. +#define CLK_EDP_CLK1 228
  9342. +#define CLK_EDP_BUS 229
  9343. +#define CLK_HDMI_REF 230
  9344. +#define CLK_HDMI_PRE 231
  9345. +#define CLK_HDMI_HDCP 232
  9346. +#define CLK_HDMI 233
  9347. +#define CLK_DPSS_TOP0 234
  9348. +#define CLK_DPSS_TOP1 235
  9349. +#define CLK_LEDC 236
  9350. +#define CLK_LEDC_BUS 237
  9351. +#define CLK_CSI_MASTER0 238
  9352. +#define CLK_CSI_MASTER1 239
  9353. +#define CLK_CSI_MASTER2 240
  9354. +#define CLK_CSI_MASTER3 241
  9355. +#define CLK_CSI 242
  9356. +#define CLK_BUS_CSI 243
  9357. +#define CLK_ISP 244
  9358. +
  9359. +#endif /* _DT_BINDINGS_CLK_SUN60IW1_H_ */
  9360. diff --git a/include/dt-bindings/clock/sun60iw1-dsp-ccu.h b/include/dt-bindings/clock/sun60iw1-dsp-ccu.h
  9361. new file mode 100644
  9362. index 000000000000..c3bbfb904ab3
  9363. --- /dev/null
  9364. +++ b/include/dt-bindings/clock/sun60iw1-dsp-ccu.h
  9365. @@ -0,0 +1,49 @@
  9366. +/* SPDX-License-Identifier: GPL-2.0 */
  9367. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9368. +/*
  9369. + * Copyright (c) 2022 [email protected]
  9370. + */
  9371. +
  9372. +#ifndef _DT_BINDINGS_CLK_SUN60IW1_DSP_CCU_H_
  9373. +#define _DT_BINDINGS_CLK_SUN60IW1_DSP_CCU_H_
  9374. +
  9375. +#define CLK_PLL_AUDIO1 0
  9376. +#define CLK_PLL_AUDIO1_DIV2 1
  9377. +#define CLK_STANDBY 2
  9378. +#define CLK_PLL_AUDIO1_DIV5 3
  9379. +#define CLK_PLL_AUDIO1_4X 4
  9380. +#define CLK_RV 5
  9381. +#define CLK_RV_BUS 6
  9382. +#define CLK_RV_CFG 7
  9383. +#define CLK_RISCV_MSG 8
  9384. +#define CLK_RV_TIMER0 9
  9385. +#define CLK_RV_TIMER1 10
  9386. +#define CLK_RV_TIMER2 11
  9387. +#define CLK_RV_TIMER3 12
  9388. +#define CLK_BUS_RV_TIMER 13
  9389. +#define CLK_MCU_TZMA1 14
  9390. +#define CLK_MCU_TZMA0 15
  9391. +#define CLK_DMA_MCLK 16
  9392. +#define CLK_DMA_HCLK 17
  9393. +#define CLK_I2S 18
  9394. +#define CLK_MCU_I2S 19
  9395. +#define CLK_DSP_TIMER0 20
  9396. +#define CLK_DSP_TIMER1 21
  9397. +#define CLK_DSP_TIMER2 22
  9398. +#define CLK_DSP_TIMER3 23
  9399. +#define CLK_BUS_DSP_TIMER 24
  9400. +#define CLK_DSP_DSP 25
  9401. +#define CLK_DSP_CFG 26
  9402. +#define CLK_DSP_MSG 27
  9403. +#define CLK_DSP_TZMA 28
  9404. +#define CLK_DSP_SPINLOCK 29
  9405. +#define CLK_DMIC 30
  9406. +#define CLK_DMIC_BUS 31
  9407. +#define CLK_MSI_BUS 32
  9408. +#define CLK_TBU_BUS 33
  9409. +#define CLK_PUBSRAM0 34
  9410. +#define CLK_PUBSRAM1 35
  9411. +
  9412. +#define CLK_DSP_NUMBER (CLK_PUBSRAM1 + 1)
  9413. +
  9414. +#endif /* _DT_BINDINGS_CLK_SUN60IW1_DSP_CCU_H_ */
  9415. diff --git a/include/dt-bindings/clock/sun60iw1-r-ccu.h b/include/dt-bindings/clock/sun60iw1-r-ccu.h
  9416. new file mode 100644
  9417. index 000000000000..5bac9135879a
  9418. --- /dev/null
  9419. +++ b/include/dt-bindings/clock/sun60iw1-r-ccu.h
  9420. @@ -0,0 +1,41 @@
  9421. +/* SPDX-License-Identifier: GPL-2.0 */
  9422. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9423. +/*
  9424. + * Copyright (c) 2022 [email protected]
  9425. + */
  9426. +
  9427. +#ifndef _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
  9428. +#define _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
  9429. +
  9430. +#define CLK_R_AHB 0
  9431. +#define CLK_R_APBS0 1
  9432. +#define CLK_R_APBS1 2
  9433. +#define CLK_R_TIMER0 3
  9434. +#define CLK_R_TIMER1 4
  9435. +#define CLK_R_TIMER2 5
  9436. +#define CLK_R_TIMER3 6
  9437. +#define CLK_R_BUS_TIMER 7
  9438. +#define CLK_R_BUS_TWD 8
  9439. +#define CLK_R_PWM 9
  9440. +#define CLK_R_BUS_PWM 10
  9441. +#define CLK_R_SPI 11
  9442. +#define CLK_R_BUS_SPI 12
  9443. +#define CLK_R_BUS_MBOX 13
  9444. +#define CLK_R_BUS_UART2 14
  9445. +#define CLK_R_BUS_UART1 15
  9446. +#define CLK_R_BUS_UART0 16
  9447. +#define CLK_R_BUS_TWI2 17
  9448. +#define CLK_R_BUS_TWI1 18
  9449. +#define CLK_R_BUS_TWI0 19
  9450. +#define CLK_R_BUS_PPU 20
  9451. +#define CLK_R_BUS_TZMA 21
  9452. +#define CLK_R_CPUS_BUS_BIST 22
  9453. +#define CLK_R_IRRX 23
  9454. +#define CLK_R_BUS_IRRX 24
  9455. +#define CLK_DMA_CLKEN_SW 25
  9456. +#define CLK_R_BUS_RTC 26
  9457. +#define CLK_R_BUS_CPUCFG 27
  9458. +
  9459. +#define CLK_R_NUMBER (CLK_R_BUS_CPUCFG + 1)
  9460. +
  9461. +#endif /* _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_ */
  9462. diff --git a/include/dt-bindings/clock/sun60iw1-rtc.h b/include/dt-bindings/clock/sun60iw1-rtc.h
  9463. new file mode 100644
  9464. index 000000000000..9441250d2ff1
  9465. --- /dev/null
  9466. +++ b/include/dt-bindings/clock/sun60iw1-rtc.h
  9467. @@ -0,0 +1,23 @@
  9468. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9469. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9470. +/*
  9471. + * Copyright (C) 2022 [email protected]
  9472. + */
  9473. +
  9474. +#ifndef _DT_BINDINGS_CLK_SUN60IW1_RTC_H_
  9475. +#define _DT_BINDINGS_CLK_SUN60IW1_RTC_H_
  9476. +
  9477. +#define CLK_IOSC 0
  9478. +#define CLK_EXT32K_GATE 1
  9479. +#define CLK_IOSC_DIV32K 2
  9480. +#define CLK_OSC32K 3
  9481. +#define CLK_DCXO24M_DIV32K 4
  9482. +#define CLK_RTC32K 5
  9483. +#define CLK_RTC_1K 6
  9484. +#define CLK_RTC_32K_FANOUT 7
  9485. +#define CLK_RTC_SPI 8
  9486. +#define CLK_DCXO 9
  9487. +
  9488. +#define CLK_RTC_MAX_NO CLK_DCXO
  9489. +
  9490. +#endif /* _DT_BINDINGS_CLK_SUN60IW1_RTC_H_ */
  9491. diff --git a/include/dt-bindings/clock/sun60iw2-ccu.h b/include/dt-bindings/clock/sun60iw2-ccu.h
  9492. new file mode 100644
  9493. index 000000000000..54689b563fa2
  9494. --- /dev/null
  9495. +++ b/include/dt-bindings/clock/sun60iw2-ccu.h
  9496. @@ -0,0 +1,336 @@
  9497. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9498. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9499. +/*
  9500. + * Copyright (C) 2023 [email protected]
  9501. + */
  9502. +
  9503. +#ifndef _DT_BINDINGS_CLK_SUN60IW2_H_
  9504. +#define _DT_BINDINGS_CLK_SUN60IW2_H_
  9505. +
  9506. +#define CLK_PLL_REF 0
  9507. +#define CLK_PLL_DDR 1
  9508. +#define CLK_PLL_PERI0 2
  9509. +#define CLK_PLL_PERI0_2X 3
  9510. +#define CLK_PLL_PERI0_800M 4
  9511. +#define CLK_PLL_PERI0_480M 5
  9512. +#define CLK_PLL_PERI0_600M 6
  9513. +#define CLK_PLL_PERI0_400M 7
  9514. +#define CLK_PLL_PERI0_300M 8
  9515. +#define CLK_PLL_PERI0_200M 9
  9516. +#define CLK_PLL_PERI0_160M 10
  9517. +#define CLK_PLL_PERI0_150M 11
  9518. +#define CLK_PLL_PERI1 12
  9519. +#define CLK_PLL_PERI1_2X 13
  9520. +#define CLK_PLL_PERI1_800M 14
  9521. +#define CLK_PLL_PERI1_480M 15
  9522. +#define CLK_PLL_PERI1_600M 16
  9523. +#define CLK_PLL_PERI1_400M 17
  9524. +#define CLK_PLL_PERI1_300M 18
  9525. +#define CLK_PLL_PERI1_200M 19
  9526. +#define CLK_PLL_PERI1_160M 20
  9527. +#define CLK_PLL_PERI1_150M 21
  9528. +#define CLK_HDMI_CEC_32K 22
  9529. +#define CLK_PLL_GPU0 23
  9530. +#define CLK_PLL_VIDEO0 24
  9531. +#define CLK_PLL_VIDEO0_4X 25
  9532. +#define CLK_PLL_VIDEO0_3X 26
  9533. +#define CLK_PLL_VIDEO1 27
  9534. +#define CLK_PLL_VIDEO1_4X 28
  9535. +#define CLK_PLL_VIDEO1_3X 29
  9536. +#define CLK_PLL_VIDEO2 30
  9537. +#define CLK_PLL_VIDEO2_4X 31
  9538. +#define CLK_PLL_VIDEO2_3X 32
  9539. +#define CLK_PLL_VE0 33
  9540. +#define CLK_PLL_VE1 34
  9541. +#define CLK_PLL_AUDIO0_4X 35
  9542. +#define CLK_PLL_AUDIO1 36
  9543. +#define CLK_PLL_AUDIO1_DIV2 37
  9544. +#define CLK_PLL_AUDIO1_DIV5 38
  9545. +#define CLK_PLL_NPU 39
  9546. +#define CLK_PLL_DE 40
  9547. +#define CLK_PLL_DE_4X 41
  9548. +#define CLK_PLL_DE_3X 42
  9549. +#define CLK_AHB 43
  9550. +#define CLK_APB0 44
  9551. +#define CLK_APB1 45
  9552. +#define CLK_APB_UART 46
  9553. +#define CLK_TRACE 47
  9554. +#define CLK_GIC 48
  9555. +#define CLK_CPU_PERI 49
  9556. +#define CLK_ITS_PCIE0_A 50
  9557. +#define CLK_NSI 51
  9558. +#define CLK_NSI_CFG 52
  9559. +#define CLK_MBUS 53
  9560. +#define CLK_IOMMU0_SYS_H 54
  9561. +#define CLK_IOMMU0_SYS_P 55
  9562. +#define CLK_IOMMU0_SYS_MBUS 56
  9563. +#define CLK_MSI_LITE0 57
  9564. +#define CLK_MSI_LITE1 58
  9565. +#define CLK_MSI_LITE2 59
  9566. +#define CLK_IOMMU1_SYS_H 60
  9567. +#define CLK_IOMMU1_SYS_P 61
  9568. +#define CLK_IOMMU1_SYS_MBUS 62
  9569. +#define CLK_CPUS_HCLK_GATE 63
  9570. +#define CLK_STORE_AHB_GATE 64
  9571. +#define CLK_MSILITE0_AHB_GATE 65
  9572. +#define CLK_USB_SYS_AHB_GATE 66
  9573. +#define CLK_SERDES_AHB_GATE 67
  9574. +#define CLK_GPU0_AHB_GATE 68
  9575. +#define CLK_NPU_AHB_GATE 69
  9576. +#define CLK_DE_AHB_GATE 70
  9577. +#define CLK_VID_OUT1_AHB_GATE 71
  9578. +#define CLK_VID_OUT0_AHB_GATE 72
  9579. +#define CLK_VID_IN_AHB_GATE 73
  9580. +#define CLK_VE_ENC_AHB_GATE 74
  9581. +#define CLK_VE_AHB_GATE 75
  9582. +#define CLK_MBUS_MSILITE2_GATE 76
  9583. +#define CLK_MBUS_STORE_GATE 77
  9584. +#define CLK_MBUS_MSILITE0_GATE 78
  9585. +#define CLK_MBUS_SERDES_GATE 79
  9586. +#define CLK_MBUS_VID_IN_GATE 80
  9587. +#define CLK_MBUS_NPU_GATE 81
  9588. +#define CLK_MBUS_GPU0_GATE 82
  9589. +#define CLK_DEC_MBUS_GATE 83
  9590. +#define CLK_MBUS_VE_GATE 84
  9591. +#define CLK_MBUS_DESYS_GATE 85
  9592. +#define CLK_IOMMU1_MBUS_GATE 86
  9593. +#define CLK_IOMMU0_MBUS_GATE 87
  9594. +#define CLK_VE_DEC_MBUS 88
  9595. +#define CLK_GMAC1_MBUS 89
  9596. +#define CLK_GMAC0_MBUS 90
  9597. +#define CLK_ISP_MBUS 91
  9598. +#define CLK_CSI_MBUS 92
  9599. +#define CLK_NAND_MBUS 93
  9600. +#define CLK_DMA1_MBUS 94
  9601. +#define CLK_MBUS_CE 95
  9602. +#define CLK_MBUS_VE 96
  9603. +#define CLK_MBUS_DMA0 97
  9604. +#define CLK_DMA0 98
  9605. +#define CLK_DMA1 99
  9606. +#define CLK_SPINLOCK 100
  9607. +#define CLK_MSGBOX0 101
  9608. +#define CLK_PWM0 102
  9609. +#define CLK_PWM1 103
  9610. +#define CLK_DBGSYS 104
  9611. +#define CLK_SYSDAP 105
  9612. +#define CLK_TIMER0 106
  9613. +#define CLK_TIMER1 107
  9614. +#define CLK_TIMER2 108
  9615. +#define CLK_TIMER3 109
  9616. +#define CLK_TIMER4 110
  9617. +#define CLK_TIMER5 111
  9618. +#define CLK_TIMER6 112
  9619. +#define CLK_TIMER7 113
  9620. +#define CLK_TIMER8 114
  9621. +#define CLK_TIMER9 115
  9622. +#define CLK_BUS_TIMER 116
  9623. +#define CLK_AVS 117
  9624. +#define CLK_DE0 118
  9625. +#define CLK_BUS_DE0 119
  9626. +#define CLK_DI 120
  9627. +#define CLK_DI_GATE 121
  9628. +#define CLK_G2D 122
  9629. +#define CLK_G2D_GATE 123
  9630. +#define CLK_EINK 124
  9631. +#define CLK_EINK_PANEL 125
  9632. +#define CLK_EINK_GATE 126
  9633. +#define CLK_VE_ENC0 127
  9634. +#define CLK_VE_DEC 128
  9635. +#define CLK_BUS_VE_DEC 129
  9636. +#define CLK_BUS_VE_ENC 130
  9637. +#define CLK_CE 131
  9638. +#define CLK_CE_SYS 132
  9639. +#define CLK_BUS_CE 133
  9640. +#define CLK_NPU 134
  9641. +#define CLK_BUS_NPU 135
  9642. +#define CLK_GPU0 136
  9643. +#define CLK_BUS_GPU0 137
  9644. +#define CLK_DRAM0 138
  9645. +#define CLK_BUS_DRAM0 139
  9646. +#define CLK_NAND0_CLK0 140
  9647. +#define CLK_NAND0_CLK1 141
  9648. +#define CLK_BUS_NAND0 142
  9649. +#define CLK_SMHC0 143
  9650. +#define CLK_BUS_SMHC0 144
  9651. +#define CLK_SMHC1 145
  9652. +#define CLK_BUS_SMHC1 146
  9653. +#define CLK_SMHC2 147
  9654. +#define CLK_BUS_SMHC2 148
  9655. +#define CLK_SMHC3 149
  9656. +#define CLK_BUS_SMHC3 150
  9657. +#define CLK_UFS_AXI 151
  9658. +#define CLK_UFS_CFG 152
  9659. +#define CLK_UFS 153
  9660. +#define CLK_UART0 154
  9661. +#define CLK_UART1 155
  9662. +#define CLK_UART2 156
  9663. +#define CLK_UART3 157
  9664. +#define CLK_UART4 158
  9665. +#define CLK_UART5 159
  9666. +#define CLK_UART6 160
  9667. +#define CLK_TWI0 161
  9668. +#define CLK_TWI1 162
  9669. +#define CLK_TWI2 163
  9670. +#define CLK_TWI3 164
  9671. +#define CLK_TWI4 165
  9672. +#define CLK_TWI5 166
  9673. +#define CLK_TWI6 167
  9674. +#define CLK_TWI7 168
  9675. +#define CLK_TWI8 169
  9676. +#define CLK_TWI9 170
  9677. +#define CLK_TWI10 171
  9678. +#define CLK_TWI11 172
  9679. +#define CLK_TWI12 173
  9680. +#define CLK_SPI0 174
  9681. +#define CLK_BUS_SPI0 175
  9682. +#define CLK_SPI1 176
  9683. +#define CLK_BUS_SPI1 177
  9684. +#define CLK_SPI2 178
  9685. +#define CLK_BUS_SPI2 179
  9686. +#define CLK_SPIF 180
  9687. +#define CLK_BUS_SPIF 181
  9688. +#define CLK_SPI3 182
  9689. +#define CLK_BUS_SPI3 183
  9690. +#define CLK_SPI4 184
  9691. +#define CLK_BUS_SPI4 185
  9692. +#define CLK_GPADC0_24M 186
  9693. +#define CLK_GPADC0 187
  9694. +#define CLK_THS0 188
  9695. +#define CLK_IRRX 189
  9696. +#define CLK_IRRX_GATE 190
  9697. +#define CLK_IRTX 191
  9698. +#define CLK_IRTX_GATE 192
  9699. +#define CLK_LRADC 193
  9700. +#define CLK_SGPIO 194
  9701. +#define CLK_BUS_SGPIO 195
  9702. +#define CLK_LPC 196
  9703. +#define CLK_BUS_LPC 197
  9704. +#define CLK_I2SPCM0 198
  9705. +#define CLK_BUS_I2SPCM0 199
  9706. +#define CLK_I2SPCM1 200
  9707. +#define CLK_BUS_I2SPCM1 201
  9708. +#define CLK_I2SPCM2 202
  9709. +#define CLK_I2SPCM2_ASRC 203
  9710. +#define CLK_BUS_I2SPCM2 204
  9711. +#define CLK_I2SPCM3 205
  9712. +#define CLK_BUS_I2SPCM3 206
  9713. +#define CLK_I2SPCM4 207
  9714. +#define CLK_BUS_I2SPCM4 208
  9715. +#define CLK_OWA_TX 209
  9716. +#define CLK_OWA_RX 210
  9717. +#define CLK_BUS_OWA 211
  9718. +#define CLK_DMIC 212
  9719. +#define CLK_BUS_DMIC 213
  9720. +#define CLK_USB 214
  9721. +#define CLK_USB0_DEVICE 215
  9722. +#define CLK_USB0_EHCI 216
  9723. +#define CLK_USB0_OHCI 217
  9724. +#define CLK_USB1 218
  9725. +#define CLK_USB1_EHCI 219
  9726. +#define CLK_USB1_OHCI 220
  9727. +#define CLK_USB_REF 221
  9728. +#define CLK_USB2_U2_REF 222
  9729. +#define CLK_USB2_SUSPEND 223
  9730. +#define CLK_USB2_MF 224
  9731. +#define CLK_USB2_U3_UTMI 225
  9732. +#define CLK_USB2_U2_PIPE 226
  9733. +#define CLK_PCIE0_AUX 227
  9734. +#define CLK_PCIE0_AXI_SLV 228
  9735. +#define CLK_SERDES_PHY_CFG 229
  9736. +#define CLK_GMAC_PTP 230
  9737. +#define CLK_GMAC0_PHY 231
  9738. +#define CLK_GMAC0 232
  9739. +#define CLK_GMAC1_PHY 233
  9740. +#define CLK_GMAC1 234
  9741. +#define CLK_VO0_TCONLCD0 235
  9742. +#define CLK_BUS_VO0_TCONLCD0 236
  9743. +#define CLK_VO0_TCONLCD1 237
  9744. +#define CLK_BUS_VO0_TCONLCD1 238
  9745. +#define CLK_VO0_TCONLCD2 239
  9746. +#define CLK_BUS_VO0_TCONLCD2 240
  9747. +#define CLK_DSI0 241
  9748. +#define CLK_BUS_DSI0 242
  9749. +#define CLK_DSI1 243
  9750. +#define CLK_BUS_DSI1 244
  9751. +#define CLK_COMBPHY0 245
  9752. +#define CLK_COMBPHY1 246
  9753. +#define CLK_TCONTV0 247
  9754. +#define CLK_TCONTV1 248
  9755. +#define CLK_EDP_TV 249
  9756. +#define CLK_EDP 250
  9757. +#define CLK_HDMI_REF 251
  9758. +#define CLK_HDMI_TV 252
  9759. +#define CLK_HDMI 253
  9760. +#define CLK_HDMI_SFR 254
  9761. +#define CLK_HDCP_ESM 255
  9762. +#define CLK_DPSS_TOP0 256
  9763. +#define CLK_DPSS_TOP1 257
  9764. +#define CLK_LEDC 258
  9765. +#define CLK_BUS_LEDC 259
  9766. +#define CLK_DSC 260
  9767. +#define CLK_CSI_MASTER0 261
  9768. +#define CLK_CSI_MASTER1 262
  9769. +#define CLK_CSI_MASTER2 263
  9770. +#define CLK_CSI 264
  9771. +#define CLK_BUS_CSI 265
  9772. +#define CLK_ISP 266
  9773. +#define CLK_RES_DCAP_24M 267
  9774. +#define CLK_APB2JTAG 268
  9775. +#define CLK_FANOUT_25M 269
  9776. +#define CLK_FANOUT_16M 270
  9777. +#define CLK_FANOUT_12M 271
  9778. +#define CLK_FANOUT_24M 272
  9779. +#define CLK_CLK27M_FANOUT 273
  9780. +#define CLK_CLK_FANOUT 274
  9781. +#define CLK_SYS_12M 275
  9782. +#define CLK_PLL_PERI0_16M 276
  9783. +#define CLK_PLL_PERI0_25M 277
  9784. +#define CLK_FANOUT3 278
  9785. +#define CLK_FANOUT2 279
  9786. +#define CLK_FANOUT1 280
  9787. +#define CLK_FANOUT0 281
  9788. +#define CLK_BUS_DEBUG 282
  9789. +#define CLK_PLL_DDR_AUTO 283
  9790. +#define CLK_PLL_PERI0_2X_AUTO 284
  9791. +#define CLK_PLL_PERI0_800M_AUTO 285
  9792. +#define CLK_PLL_PERI0_600M_AUTO 286
  9793. +#define CLK_PLL_PERI0_480M_ALL_AUTO 287
  9794. +#define CLK_PLL_PERI0_480M_AUTO 288
  9795. +#define CLK_PLL_PERI0_160M_AUTO 289
  9796. +#define CLK_PLL_PERI0_300M_ALL_AUTO 290
  9797. +#define CLK_PLL_PERI0_300M_AUTO 291
  9798. +#define CLK_PLL_PERI0_150M_AUTO 292
  9799. +#define CLK_PLL_PERI0_400M_ALL_AUTO 293
  9800. +#define CLK_PLL_PERI0_400M_AUTO 294
  9801. +#define CLK_PLL_PERI0_200M_AUTO 295
  9802. +#define CLK_PLL_PERI1_800M_AUTO 296
  9803. +#define CLK_PLL_PERI1_600M_ALL_AUTO 297
  9804. +#define CLK_PLL_PERI1_600M_AUTO 298
  9805. +#define CLK_PLL_PERI1_480M_ALL_AUTO 299
  9806. +#define CLK_PLL_PERI1_480M_AUTO 300
  9807. +#define CLK_PLL_PERI1_160M_AUTO 301
  9808. +#define CLK_PLL_PERI1_300M_ALL_AUTO 302
  9809. +#define CLK_PLL_PERI1_300M_AUTO 303
  9810. +#define CLK_PLL_PERI1_150M_AUTO 304
  9811. +#define CLK_PLL_PERI1_400M_ALL_AUTO 305
  9812. +#define CLK_PLL_PERI1_400M_AUTO 306
  9813. +#define CLK_PLL_PERI1_200M_AUTO 307
  9814. +#define CLK_PLL_VIDEO2_3X_AUTO 308
  9815. +#define CLK_PLL_VIDEO1_3X_AUTO 309
  9816. +#define CLK_PLL_VIDEO0_3X_AUTO 310
  9817. +#define CLK_PLL_VIDEO2_4X_AUTO 311
  9818. +#define CLK_PLL_VIDEO1_4X_AUTO 312
  9819. +#define CLK_PLL_VIDEO0_4X_AUTO 313
  9820. +#define CLK_PLL_GPU0_AUTO 314
  9821. +#define CLK_PLL_VE1_AUTO 315
  9822. +#define CLK_PLL_VE0_AUTO 316
  9823. +#define CLK_PLL_AUDIO1_DIV5_AUTO 317
  9824. +#define CLK_PLL_AUDIO1_DIV2_AUTO 318
  9825. +#define CLK_PLL_AUDIO0_4X_AUTO 319
  9826. +#define CLK_PLL_NPU_AUTO 320
  9827. +#define CLK_PLL_DE_3X_AUTO 321
  9828. +#define CLK_PLL_DE_4X_AUTO 322
  9829. +
  9830. +#define CLK_MAX_NO (CLK_PLL_DE_4X_AUTO + 1)
  9831. +
  9832. +#endif /* _DT_BINDINGS_CLK_SUN60IW2_H_ */
  9833. diff --git a/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h b/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h
  9834. new file mode 100644
  9835. index 000000000000..cd791eba207d
  9836. --- /dev/null
  9837. +++ b/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h
  9838. @@ -0,0 +1,18 @@
  9839. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9840. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9841. +
  9842. +#ifndef _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_
  9843. +#define _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_
  9844. +
  9845. +
  9846. +#define CLK_PLL_CPU_BACK 0
  9847. +#define CLK_PLL_CPU_L 1
  9848. +#define CLK_PLL_CPU_B 2
  9849. +#define CLK_PLL_CPU_DSU 3
  9850. +#define CLK_CPU_L 4
  9851. +#define CLK_CPU_B 5
  9852. +#define CLK_CPU_DSU 6
  9853. +
  9854. +#define CLK_CPUPLL_MAX_NO (CLK_CPU_DSU + 1)
  9855. +
  9856. +#endif /* _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_ */
  9857. diff --git a/include/dt-bindings/clock/sun60iw2-r-ccu.h b/include/dt-bindings/clock/sun60iw2-r-ccu.h
  9858. new file mode 100644
  9859. index 000000000000..7bd8983a39ef
  9860. --- /dev/null
  9861. +++ b/include/dt-bindings/clock/sun60iw2-r-ccu.h
  9862. @@ -0,0 +1,49 @@
  9863. +/* SPDX-License-Identifier: GPL-2.0 */
  9864. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9865. +/*
  9866. + * Copyright (c) 2023 [email protected]
  9867. + */
  9868. +
  9869. +#ifndef _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
  9870. +#define _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_
  9871. +
  9872. +#define CLK_R_AHB 0
  9873. +#define CLK_R_APBS0 1
  9874. +#define CLK_R_APBS1 2
  9875. +#define CLK_R_TIMER0 3
  9876. +#define CLK_R_TIMER1 4
  9877. +#define CLK_R_TIMER2 5
  9878. +#define CLK_R_TIMER3 6
  9879. +#define CLK_R_TIMER 7
  9880. +#define CLK_R_TWD 8
  9881. +#define CLK_R_BUS_PWM 9
  9882. +#define CLK_R_PWM 10
  9883. +#define CLK_R_SPI 11
  9884. +#define CLK_R_BUS_SPI 12
  9885. +#define CLK_R_MBOX 13
  9886. +#define CLK_R_UART1 14
  9887. +#define CLK_R_UART0 15
  9888. +#define CLK_R_TWI2 16
  9889. +#define CLK_R_TWI1 17
  9890. +#define CLK_R_TWI0 18
  9891. +#define CLK_R_PPU 19
  9892. +#define CLK_R_TZMA 20
  9893. +#define CLK_R_CPUS_BIST 21
  9894. +#define CLK_R_IRRX 22
  9895. +#define CLK_R_BUS_IRRX 23
  9896. +#define CLK_RTC 24
  9897. +#define CLK_RISCV_24M 25
  9898. +#define CLK_RISCV_CFG 26
  9899. +#define CLK_RISCV 27
  9900. +#define CLK_R_CPUCFG 28
  9901. +#define CLK_VDD_USB2CPUS 29
  9902. +#define CLK_VDD_SYS2USB 30
  9903. +#define CLK_VDD_SYS2CPUS 31
  9904. +#define CLK_VDD_DDR 32
  9905. +#define CLK_TT_AUTO 33
  9906. +#define CLK_CPU_ICACHE_AUTO 34
  9907. +#define CLK_AHBS_AUTO_CLK 35
  9908. +
  9909. +#define CLK_R_NUMBER (CLK_AHBS_AUTO_CLK + 1)
  9910. +
  9911. +#endif /* _DT_BINDINGS_CLK_SUN60IW2_R_CCU_H_ */
  9912. diff --git a/include/dt-bindings/clock/sun60iw2-rtc.h b/include/dt-bindings/clock/sun60iw2-rtc.h
  9913. new file mode 100644
  9914. index 000000000000..83fc97d75370
  9915. --- /dev/null
  9916. +++ b/include/dt-bindings/clock/sun60iw2-rtc.h
  9917. @@ -0,0 +1,26 @@
  9918. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9919. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9920. +/*
  9921. + * Copyright (C) 2023 [email protected]
  9922. + */
  9923. +
  9924. +#ifndef _DT_BINDINGS_CLK_SUN60IW2_RTC_H_
  9925. +#define _DT_BINDINGS_CLK_SUN60IW2_RTC_H_
  9926. +
  9927. +#define CLK_IOSC 0
  9928. +#define CLK_EXT32K_GATE 1
  9929. +#define CLK_IOSC_DIV32K 2
  9930. +#define CLK_OSC32K 3
  9931. +#define CLK_DCXO24M_DIV32K 4
  9932. +#define CLK_RTC32K 5
  9933. +#define CLK_RTC_1K 6
  9934. +#define CLK_RTC_32K_FANOUT 7
  9935. +#define CLK_RTC_DCXO_WAKEUP 8
  9936. +#define CLK_RTC_DCXO_SERDES1 9
  9937. +#define CLK_RTC_DCXO_SERDES0 10
  9938. +#define CLK_RTC_SPI 11
  9939. +#define CLK_DCXO 12
  9940. +
  9941. +#define CLK_RTC_MAX_NO (CLK_DCXO + 1)
  9942. +
  9943. +#endif /* _DT_BINDINGS_CLK_SUN60IW2_RTC_H_ */
  9944. diff --git a/include/dt-bindings/clock/sun65iw1-ccu.h b/include/dt-bindings/clock/sun65iw1-ccu.h
  9945. new file mode 100644
  9946. index 000000000000..4be9718fec23
  9947. --- /dev/null
  9948. +++ b/include/dt-bindings/clock/sun65iw1-ccu.h
  9949. @@ -0,0 +1,188 @@
  9950. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  9951. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  9952. +/*
  9953. + * Copyright (C) 2023 [email protected]
  9954. + */
  9955. +
  9956. +#ifndef _DT_BINDINGS_CLK_SUN65IW1_H_
  9957. +#define _DT_BINDINGS_CLK_SUN65IW1_H_
  9958. +
  9959. +#define CLK_PLL_PERI0_PARENT 0
  9960. +#define CLK_PLL_PERI0_2X 1
  9961. +#define CLK_PLL_PERI0_DIV3 2
  9962. +#define CLK_PLL_PERI0_800M 3
  9963. +#define CLK_PLL_PERI0_480M 4
  9964. +#define CLK_PLL_PERI0_600M 5
  9965. +#define CLK_PLL_PERI0_400M 6
  9966. +#define CLK_PLL_PERI0_300M 7
  9967. +#define CLK_PLL_PERI0_200M 8
  9968. +#define CLK_PLL_PERI0_160M 9
  9969. +#define CLK_PLL_PERI0_16M 10
  9970. +#define CLK_PLL_PERI0_150M 11
  9971. +#define CLK_PLL_PERI1_PARENT 12
  9972. +#define CLK_PLL_PERI1_2X 13
  9973. +#define CLK_PLL_PERI1_800M 14
  9974. +#define CLK_PLL_PERI1_480M 15
  9975. +#define CLK_PLL_PERI1_600M 16
  9976. +#define CLK_PLL_PERI1_400M 17
  9977. +#define CLK_PLL_PERI1_300M 18
  9978. +#define CLK_PLL_PERI1_200M 19
  9979. +#define CLK_PLL_PERI1_160M 20
  9980. +#define CLK_PLL_PERI1_150M 21
  9981. +#define CLK_PLL_OUTP 22
  9982. +#define CLK_PLL_GPU 23
  9983. +#define CLK_PLL_VIDEO0_PARENT 24
  9984. +#define CLK_PLL_VIDEO0_4X 25
  9985. +#define CLK_PLL_VIDEO0_3X 26
  9986. +#define CLK_PLL_VIDEO1_PARENT 27
  9987. +#define CLK_PLL_VIDEO1_4X 28
  9988. +#define CLK_PLL_VIDEO1_3X 29
  9989. +#define CLK_PLL_VIDEO2_PARENT 30
  9990. +#define CLK_PLL_VIDEO2_4X 31
  9991. +#define CLK_PLL_VIDEO2_3X 32
  9992. +#define CLK_PLL_VE 33
  9993. +#define CLK_AHB 34
  9994. +#define CLK_APB0 35
  9995. +#define CLK_APB1 36
  9996. +#define CLK_APB_UART 37
  9997. +#define CLK_CCI 38
  9998. +#define CLK_GIC 39
  9999. +#define CLK_NSI 40
  10000. +#define CLK_NSI_CFG 41
  10001. +#define CLK_MBUS 42
  10002. +#define CLK_APB_IOMMU 43
  10003. +#define CLK_STBY_PERI0PLL_CLK_GATE 44
  10004. +#define CLK_AHB_SMHC2_GATE 45
  10005. +#define CLK_AHB_SMHC1_GATE 46
  10006. +#define CLK_AHB_SMHC0_GATE 47
  10007. +#define CLK_AHB_HSI_GATE 48
  10008. +#define CLK_AHB_USB1_GATE 49
  10009. +#define CLK_AHB_USB0_GATE 50
  10010. +#define CLK_AHB_SECURE_SYS_GATE 51
  10011. +#define CLK_AHB_GPU_GATE 52
  10012. +#define CLK_AHB_VIDEO_OUT1_GATE 53
  10013. +#define CLK_AHB_VIDEO_OUT0_GATE 54
  10014. +#define CLK_AHB_VIDEO_IN_GATE 55
  10015. +#define CLK_AHB_VE0_GATE 56
  10016. +#define CLK_MBUS_DMAC0_GATE 57
  10017. +#define CLK_GMAC0_AXI_GATE 58
  10018. +#define CLK_CE_SYS_AXI_GATE 59
  10019. +#define CLK_GPU_AXI_GATE 60
  10020. +#define CLK_MBUS_DE_SYS_GATE 61
  10021. +#define CLK_MBUS_VIDEO_OUT0_GATE 62
  10022. +#define CLK_MBUS_VIDEO_IN_GATE 63
  10023. +#define CLK_MBUS_VE0_GATE 64
  10024. +#define CLK_AHB_DMA 65
  10025. +#define CLK_AHB_SPINLOCK 66
  10026. +#define CLK_AHB_MSGBOX_CPUX 67
  10027. +#define CLK_AHB_MSGBOX_CPUS 68
  10028. +#define CLK_APB_PWM0 69
  10029. +#define CLK_DCU 70
  10030. +#define CLK_AHB_DAP 71
  10031. +#define CLK_TIMER0 72
  10032. +#define CLK_TIMER1 73
  10033. +#define CLK_TIMER2 74
  10034. +#define CLK_TIMER3 75
  10035. +#define CLK_AHB_TIMER 76
  10036. +#define CLK_DE 77
  10037. +#define CLK_AHB_DE0 78
  10038. +#define CLK_G2D 79
  10039. +#define CLK_AHB_G2D 80
  10040. +#define CLK_EINK_PANEL 81
  10041. +#define CLK_AHB_EINK 82
  10042. +#define CLK_VE0 83
  10043. +#define CLK_AHB_VE0 84
  10044. +#define CLK_CE_SYS 85
  10045. +#define CLK_AHB_GPU 86
  10046. +#define CLK_AHB_MEMC 87
  10047. +#define CLK_SMHC0 88
  10048. +#define CLK_BUS_SMHC0 89
  10049. +#define CLK_SMHC1 90
  10050. +#define CLK_BUS_SMHC1 91
  10051. +#define CLK_SMHC2 92
  10052. +#define CLK_BUS_SMHC2 93
  10053. +#define CLK_BUS_UART0 94
  10054. +#define CLK_BUS_UART1 95
  10055. +#define CLK_BUS_UART2 96
  10056. +#define CLK_BUS_UART3 97
  10057. +#define CLK_BUS_UART4 98
  10058. +#define CLK_BUS_UART5 99
  10059. +#define CLK_BUS_UART6 100
  10060. +#define CLK_BUS_UART7 101
  10061. +#define CLK_BUS_TWI0 102
  10062. +#define CLK_BUS_TWI1 103
  10063. +#define CLK_BUS_TWI2 104
  10064. +#define CLK_BUS_TWI3 105
  10065. +#define CLK_BUS_TWI4 106
  10066. +#define CLK_BUS_TWI5 107
  10067. +#define CLK_SPI0 108
  10068. +#define CLK_AHB_SPI0 109
  10069. +#define CLK_SPI1 110
  10070. +#define CLK_AHB_SPI1 111
  10071. +#define CLK_SPI2 112
  10072. +#define CLK_AHB_SPI2 113
  10073. +#define CLK_GPADC0 114
  10074. +#define CLK_APB_GPADC0 115
  10075. +#define CLK_APB_TSENSOR 116
  10076. +#define CLK_IRRX0 117
  10077. +#define CLK_APB_IRRX0 118
  10078. +#define CLK_IRTX 119
  10079. +#define CLK_APB_IRTX 120
  10080. +#define CLK_I2S0 121
  10081. +#define CLK_APB_I2S0 122
  10082. +#define CLK_I2S1 123
  10083. +#define CLK_APB_I2S1 124
  10084. +#define CLK_I2S2 125
  10085. +#define CLK_APB_I2S2 126
  10086. +#define CLK_I2S3 127
  10087. +#define CLK_I2S3_ASRC 128
  10088. +#define CLK_APB_I2S3 129
  10089. +#define CLK_OWA0_TX 130
  10090. +#define CLK_OWA0_RX 131
  10091. +#define CLK_APB_OWA0 132
  10092. +#define CLK_DMIC 133
  10093. +#define CLK_APB_DMIC 134
  10094. +#define CLK_ADDA_DAC 135
  10095. +#define CLK_ADDA_ADC 136
  10096. +#define CLK_APB_ADDA 137
  10097. +#define CLK_USB 138
  10098. +#define CLK_USB0_DEV 139
  10099. +#define CLK_USB0_EHCI 140
  10100. +#define CLK_USB0_OHCI 141
  10101. +#define CLK_BUS_USB 142
  10102. +#define CLK_USB1_EHCI 143
  10103. +#define CLK_USB1_OHCI 144
  10104. +#define CLK_USB0_USB1_PHY_REF 145
  10105. +#define CLK_AHB_USB0_USB1 146
  10106. +#define CLK_USB2_U2_PHY_REF 147
  10107. +#define CLK_USB2_SUSPEND 148
  10108. +#define CLK_USB2_REF 149
  10109. +#define CLK_USB2_U3_ONLY_UTMI 150
  10110. +#define CLK_USB2_U2_ONLY_PIPE 151
  10111. +#define CLK_PCIE0_AUX 152
  10112. +#define CLK_PCIE0_AXI_S 153
  10113. +#define CLK_HSI_PHY_CFG 154
  10114. +#define CLK_HSI_PHY_REF 155
  10115. +#define CLK_HSI_SYS 156
  10116. +#define CLK_HSI_AXI 157
  10117. +#define CLK_GMAC0_PHY 158
  10118. +#define CLK_AHB_GMAC0 159
  10119. +#define CLK_DSI0 160
  10120. +#define CLK_AHB_DSI 161
  10121. +#define CLK_TCON_TV0 162
  10122. +#define CLK_EDP 163
  10123. +#define CLK_AHB_VO0 164
  10124. +#define CLK_AHB_VO1 165
  10125. +#define CLK_LEDC 166
  10126. +#define CLK_APB_LEDC 167
  10127. +#define CLK_CSI_MASTER0 168
  10128. +#define CLK_CSI_MASTER1 169
  10129. +#define CLK_CSI_MASTER2 170
  10130. +#define CLK_CSI_MASTER3 171
  10131. +#define CLK_CSI 172
  10132. +#define CLK_ISP 173
  10133. +#define CLK_VIDEO_IN 174
  10134. +
  10135. +#define CLK_MAX_NO (CLK_VIDEO_IN + 1)
  10136. +
  10137. +#endif /* _DT_BINDINGS_CLK_SUN65IW1_H_ */
  10138. diff --git a/include/dt-bindings/clock/sun65iw1-r-ccu.h b/include/dt-bindings/clock/sun65iw1-r-ccu.h
  10139. new file mode 100644
  10140. index 000000000000..688489fcc899
  10141. --- /dev/null
  10142. +++ b/include/dt-bindings/clock/sun65iw1-r-ccu.h
  10143. @@ -0,0 +1,37 @@
  10144. +/* SPDX-License-Identifier: GPL-2.0 */
  10145. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10146. +/*
  10147. + * Copyright (c) 2023 [email protected]
  10148. + */
  10149. +
  10150. +#ifndef _DT_BINDINGS_CLK_SUN65IW1_R_CCU_H_
  10151. +#define _DT_BINDINGS_CLK_SUN65IW1_R_CCU_H_
  10152. +
  10153. +#define CLK_R_TIMER0 0
  10154. +#define CLK_R_TIMER1 1
  10155. +#define CLK_R_TIMER2 2
  10156. +#define CLK_R_TIMER3 3
  10157. +#define CLK_R_TIMER 4
  10158. +#define CLK_R_TWD 5
  10159. +#define CLK_R_PWM 6
  10160. +#define CLK_BUS_R_PWM 7
  10161. +#define CLK_R_SPI 8
  10162. +#define CLK_BUS_R_SPI 9
  10163. +#define CLK_R_UART1 10
  10164. +#define CLK_R_UART0 11
  10165. +#define CLK_R_TWI2 12
  10166. +#define CLK_R_TWI1 13
  10167. +#define CLK_R_TWI0 14
  10168. +#define CLK_R_PPU 15
  10169. +#define CLK_R_TZMA 16
  10170. +#define CLK_R_IRRX 17
  10171. +#define CLK_BUS_R_IRRX 18
  10172. +#define CLK_RTC 19
  10173. +#define CLK_E902_24M 20
  10174. +#define CLK_E902_CFG 21
  10175. +#define CLK_E902_CORE 22
  10176. +#define CLK_R_CPUCFG 23
  10177. +
  10178. +#define CLK_R_NUMBER (CLK_R_CPUCFG + 1)
  10179. +
  10180. +#endif /* _DT_BINDINGS_CLK_SUN65IW1_R_CCU_H_ */
  10181. diff --git a/include/dt-bindings/clock/sun65iw1-rtc.h b/include/dt-bindings/clock/sun65iw1-rtc.h
  10182. new file mode 100644
  10183. index 000000000000..4d296a275697
  10184. --- /dev/null
  10185. +++ b/include/dt-bindings/clock/sun65iw1-rtc.h
  10186. @@ -0,0 +1,23 @@
  10187. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10188. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10189. +/*
  10190. + * Copyright (C) 2023 [email protected]
  10191. + */
  10192. +
  10193. +#ifndef _DT_BINDINGS_CLK_SUN65IW1_RTC_H_
  10194. +#define _DT_BINDINGS_CLK_SUN65IW1_RTC_H_
  10195. +
  10196. +#define CLK_DCXO24M_OUT 0
  10197. +#define CLK_IOSC 1
  10198. +#define CLK_EXT32K_GATE 2
  10199. +#define CLK_IOSC_DIV32K 3
  10200. +#define CLK_OSC32K 4
  10201. +#define CLK_DCXO24M_DIV32K 5
  10202. +#define CLK_RTC32K 6
  10203. +#define CLK_RTC_1K 7
  10204. +#define CLK_OSC32K_OUT 8
  10205. +#define CLK_RTC_SPI 9
  10206. +
  10207. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  10208. +
  10209. +#endif /* _DT_BINDINGS_CLK_SUN65IW1_RTC_H_ */
  10210. diff --git a/include/dt-bindings/clock/sun8iw11-ccu.h b/include/dt-bindings/clock/sun8iw11-ccu.h
  10211. new file mode 100644
  10212. index 000000000000..353e67d87d78
  10213. --- /dev/null
  10214. +++ b/include/dt-bindings/clock/sun8iw11-ccu.h
  10215. @@ -0,0 +1,182 @@
  10216. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10217. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10218. +/*
  10219. + * Copyright (C) 2022 [email protected]
  10220. + */
  10221. +
  10222. +#ifndef _DT_BINDINGS_CLK_SUN8IW11_H_
  10223. +#define _DT_BINDINGS_CLK_SUN8IW11_H_
  10224. +
  10225. +#define CLK_PLL_CPUX 0
  10226. +#define CLK_PLL_AUDIO_1X 1
  10227. +#define CLK_PLL_AUDIO_4X 2
  10228. +#define CLK_PLL_AUDIO_8X 3
  10229. +#define CLK_PLL_AUDIO 4
  10230. +#define CLK_PLL_VIDEO0_1X 5
  10231. +#define CLK_PLL_VIDEO0_2X 6
  10232. +#define CLK_PLL_VE 7
  10233. +#define CLK_PLL_DDR0 8
  10234. +#define CLK_PLL_PERIPH0_2X 9
  10235. +#define CLK_PLL_PERIPH0_1X 10
  10236. +#define CLK_PLL_PERIPH1_2X 11
  10237. +#define CLK_PLL_PERIPH1_1X 12
  10238. +#define CLK_PLL_VIDEO1_1X 13
  10239. +#define CLK_PLL_VIDEO1_2X 14
  10240. +#define CLK_PLL_SATA 15
  10241. +#define CLK_PLL_GPU 16
  10242. +#define CLK_PLL_MIPI 17
  10243. +#define CLK_PLL_DE 18
  10244. +#define CLK_PLL_DDR1 19
  10245. +#define CLK_CPUX 20
  10246. +#define CLK_AXI 21
  10247. +#define CLK_PLL_PERIPHAHB0 22
  10248. +#define CLK_AHB1 23
  10249. +#define CLK_APB1 24
  10250. +#define CLK_APB2 25
  10251. +#define CLK_USB_OHCI2 26
  10252. +#define CLK_USB_OHCI1 27
  10253. +#define CLK_USB_OHCI0 28
  10254. +#define CLK_BUS_EHCI2 29
  10255. +#define CLK_BUS_EHCI1 30
  10256. +#define CLK_BUS_EHCI0 31
  10257. +#define CLK_BUS_OTG 32
  10258. +#define CLK_BUS_SATA 33
  10259. +#define CLK_BUS_SPI3 34
  10260. +#define CLK_BUS_SPI2 35
  10261. +#define CLK_BUS_SPI1 36
  10262. +#define CLK_BUS_SPI0 37
  10263. +#define CLK_BUS_HSTMR 38
  10264. +#define CLK_BUS_TS 39
  10265. +#define CLK_BUS_EMAC 40
  10266. +#define CLK_BUS_DRAM 41
  10267. +#define CLK_BUS_NAND 42
  10268. +#define CLK_BUS_MMC3 43
  10269. +#define CLK_BUS_MMC2 44
  10270. +#define CLK_BUS_MMC1 45
  10271. +#define CLK_BUS_MMC0 46
  10272. +#define CLK_BUS_DMA 47
  10273. +#define CLK_BUS_CE 48
  10274. +#define CLK_BUS_MIPIDSI 49
  10275. +#define CLK_BUS_TCONTOP 50
  10276. +#define CLK_BUS_TCONTV1 51
  10277. +#define CLK_BUS_TCONTV0 52
  10278. +#define CLK_BUS_TCONLCD1 53
  10279. +#define CLK_BUS_TCONLCD0 54
  10280. +#define CLK_BUS_TVDTOP 55
  10281. +#define CLK_BUS_TVD3 56
  10282. +#define CLK_BUS_TVD2 57
  10283. +#define CLK_BUS_TVD1 58
  10284. +#define CLK_BUS_TVD0 59
  10285. +#define CLK_BUS_GPU 60
  10286. +#define CLK_BUS_GMAC 61
  10287. +#define CLK_BUS_TVETOP 62
  10288. +#define CLK_BUS_TVE1 63
  10289. +#define CLK_BUS_TVE0 64
  10290. +#define CLK_BUS_DE 65
  10291. +#define CLK_BUS_HDMI1 66
  10292. +#define CLK_BUS_HDMI0 67
  10293. +#define CLK_BUS_CSI1 68
  10294. +#define CLK_BUS_CSI0 69
  10295. +#define CLK_BUS_DI 70
  10296. +#define CLK_BUS_MP 71
  10297. +#define CLK_BUS_VE 72
  10298. +#define CLK_BUS_DAUDIO2 73
  10299. +#define CLK_BUS_DAUDIO1 74
  10300. +#define CLK_BUS_DAUDIO0 75
  10301. +#define CLK_BUS_KEYPAD 76
  10302. +#define CLK_BUS_THS 77
  10303. +#define CLK_BUS_IR1 78
  10304. +#define CLK_BUS_IR0 79
  10305. +#define CLK_BUS_PIO 80
  10306. +#define CLK_BUS_AC97 81
  10307. +#define CLK_BUS_SPDIF 82
  10308. +#define CLK_BUS_AC_DIG 83
  10309. +#define CLK_BUS_UART7 84
  10310. +#define CLK_BUS_UART6 85
  10311. +#define CLK_BUS_UART5 86
  10312. +#define CLK_BUS_UART4 87
  10313. +#define CLK_BUS_UART3 88
  10314. +#define CLK_BUS_UART2 89
  10315. +#define CLK_BUS_UART1 90
  10316. +#define CLK_BUS_UART0 91
  10317. +#define CLK_BUS_TWI4 92
  10318. +#define CLK_BUS_PS2_1 93
  10319. +#define CLK_BUS_PS2_0 94
  10320. +#define CLK_BUS_SCR 95
  10321. +#define CLK_BUS_TWI3 96
  10322. +#define CLK_BUS_TWI2 97
  10323. +#define CLK_BUS_TWI1 98
  10324. +#define CLK_BUS_TWI0 99
  10325. +#define CLK_BUS_DBGSYS 100
  10326. +#define CLK_SDMM2_MOD 101
  10327. +#define CLK_THS 102
  10328. +#define CLK_NAND 103
  10329. +#define CLK_MMC0 104
  10330. +#define CLK_MMC1 105
  10331. +#define CLK_MMC2 106
  10332. +#define CLK_MMC3 107
  10333. +#define CLK_TS 108
  10334. +#define CLK_CE 109
  10335. +#define CLK_SPI0 110
  10336. +#define CLK_SPI1 111
  10337. +#define CLK_SPI2 112
  10338. +#define CLK_SPI3 113
  10339. +#define CLK_DAUDIO0 114
  10340. +#define CLK_DAUDIO1 115
  10341. +#define CLK_DAUDIO2 116
  10342. +#define CLK_AC97 117
  10343. +#define CLK_SPDIF 118
  10344. +#define CLK_KEYPAD 119
  10345. +#define CLK_SATA 120
  10346. +#define CLK_12M_FROM_48M 121
  10347. +#define CLK_12M_FROM_24M 122
  10348. +#define CLK_12M_FROM_32K 123
  10349. +#define CLK_32K_FROM_24M 124
  10350. +#define CLK_OHCI2_12M 125
  10351. +#define CLK_OHCI1_12M 126
  10352. +#define CLK_OHCI0_12M 127
  10353. +#define CLK_USBPHY2_GATE 128
  10354. +#define CLK_USBPHY1_GATE 129
  10355. +#define CLK_USBPHY0_GATE 130
  10356. +#define CLK_IR0 131
  10357. +#define CLK_IR1 132
  10358. +#define CLK_DRAM 133
  10359. +#define CLK_DI_GATE 134
  10360. +#define CLK_MP_GATE 135
  10361. +#define CLK_TVD_GATE 136
  10362. +#define CLK_TS_GATE 137
  10363. +#define CLK_CSI1_GATE 138
  10364. +#define CLK_CSI0_GATE 139
  10365. +#define CLK_VE_GATE 140
  10366. +#define CLK_DE 141
  10367. +#define CLK_DE_MP 142
  10368. +#define CLK_TCON_LCD0 143
  10369. +#define CLK_TCON_LCD1 144
  10370. +#define CLK_TCON_TV0 145
  10371. +#define CLK_TCON_TV1 146
  10372. +#define CLK_DEINTERLACE 147
  10373. +#define CLK_CSI_MISC 148
  10374. +#define CLK_CSI_SCLK 149
  10375. +#define CLK_CSI_MCLK0 150
  10376. +#define CLK_VE 151
  10377. +#define CLK_AC_DIGITAL_GATE 152
  10378. +#define CLK_AVS_GATE 153
  10379. +#define CLK_HDMI 154
  10380. +#define CLK_HDMI_DDC_GATE 155
  10381. +#define CLK_MBUS 156
  10382. +#define CLK_RMII_GATE 157
  10383. +#define CLK_EPIT_GATE 158
  10384. +#define CLK_MIPI_DSI 159
  10385. +#define CLK_TVE0 160
  10386. +#define CLK_TVE1 161
  10387. +#define CLK_TVD0 162
  10388. +#define CLK_TVD1 163
  10389. +#define CLK_TVD2 164
  10390. +#define CLK_TVD3 165
  10391. +#define CLK_GPU 166
  10392. +#define CLK_OUTA 167
  10393. +#define CLK_OUTB 168
  10394. +
  10395. +#define CLK_MAX_NO CLK_OUTB
  10396. +
  10397. +#endif /* _DT_BINDINGS_CLK_SUN8IW11_H_ */
  10398. diff --git a/include/dt-bindings/clock/sun8iw18-ccu.h b/include/dt-bindings/clock/sun8iw18-ccu.h
  10399. new file mode 100644
  10400. index 000000000000..f53dfc7b1ffb
  10401. --- /dev/null
  10402. +++ b/include/dt-bindings/clock/sun8iw18-ccu.h
  10403. @@ -0,0 +1,87 @@
  10404. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10405. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10406. +/*
  10407. + * Copyright (C) 2022 [email protected]
  10408. + */
  10409. +
  10410. +#ifndef _DT_BINDINGS_CLK_SUN8IW18_H_
  10411. +#define _DT_BINDINGS_CLK_SUN8IW18_H_
  10412. +
  10413. +#define CLK_PLL_CPU0 0
  10414. +#define CLK_PLL_DDR 1
  10415. +#define CLK_PLL_PERI0_2X 2
  10416. +#define CLK_PLL_PERI0_1X 3
  10417. +#define CLK_PLL_PERI1_2X 4
  10418. +#define CLK_PLL_PERI1_1X 5
  10419. +#define CLK_PLL_AUDIO0_4X 6
  10420. +#define CLK_PLL_AUDIO0_2X 7
  10421. +#define CLK_PLL_32K_CTRL 8
  10422. +#define CLK_CPUX 9
  10423. +#define CLK_PSI_AHB1_AHB2 10
  10424. +#define CLK_AHB3 11
  10425. +#define CLK_APB1 12
  10426. +#define CLK_APB2 13
  10427. +#define CLK_CE 14
  10428. +#define CLK_BUS_CE 15
  10429. +#define CLK_BUS_DMA 16
  10430. +#define CLK_BUS_HSTIMER 17
  10431. +#define CLK_AVS 18
  10432. +#define CLK_DBGSYS 19
  10433. +#define CLK_PSI 20
  10434. +#define CLK_PWM 21
  10435. +#define CLK_DRAM 22
  10436. +#define CLK_MBUS_NAND0 23
  10437. +#define CLK_MBUS_CE 24
  10438. +#define CLK_MBUS_DMA 25
  10439. +#define CLK_MBUS_DRAM 26
  10440. +#define CLK_NAND0_0 27
  10441. +#define CLK_NAND0_1 28
  10442. +#define CLK_BUS_NAND0 29
  10443. +#define CLK_SMHC1 30
  10444. +#define CLK_BUS_SMHC2 31
  10445. +#define CLK_BUS_SMHC1 32
  10446. +#define CLK_BUS_SMHC0 33
  10447. +#define CLK_BUS_UART3 34
  10448. +#define CLK_BUS_UART2 35
  10449. +#define CLK_BUS_UART1 36
  10450. +#define CLK_BUS_UART0 37
  10451. +#define CLK_TWI2 38
  10452. +#define CLK_TWI1 39
  10453. +#define CLK_TWI0 40
  10454. +#define CLK_SPI0 41
  10455. +#define CLK_SPI1 42
  10456. +#define CLK_BUS_SPI1 43
  10457. +#define CLK_BUS_SPI0 44
  10458. +#define CLK_BUS_GPADC 45
  10459. +#define CLK_BUS_THS 46
  10460. +#define CLK_I2S_PCM0 47
  10461. +#define CLK_I2S_PCM1 48
  10462. +#define CLK_I2S_PCM2 49
  10463. +#define CLK_BUS_I2S_PCM0 50
  10464. +#define CLK_BUS_I2S_PCM1 51
  10465. +#define CLK_BUS_I2S_PCM2 52
  10466. +#define CLK_SPDIF 53
  10467. +#define CLK_BUS_SPDIF 54
  10468. +#define CLK_DMIC 55
  10469. +#define CLK_BUS_DMIC 56
  10470. +#define CLK_AUDIO_CODEC_1X 57
  10471. +#define CLK_AUDIO_CODEC_4X 58
  10472. +#define CLK_AUDIO_CODEC 59
  10473. +#define CLK_USB0 60
  10474. +#define CLK_USBPHY0 61
  10475. +#define CLK_USBOTG 62
  10476. +#define CLK_USBEHCI1 63
  10477. +#define CLK_USBEHCI0 64
  10478. +#define CLK_USBOHCI1 65
  10479. +#define CLK_USBOHCI0 66
  10480. +#define CLK_MAD_CFG 67
  10481. +#define CLK_MAD_AD 68
  10482. +#define CLK_MAD 69
  10483. +#define CLK_LPSD 70
  10484. +#define CLK_LEDC 71
  10485. +#define CLK_BUS_LEDC 72
  10486. +#define CLK_ACODEC_24M 73
  10487. +
  10488. +#define CLK_MAX_NO (CLK_ACODEC_24M + 1)
  10489. +
  10490. +#endif /* _DT_BINDINGS_CLK_SUN8IW18_H_ */
  10491. diff --git a/include/dt-bindings/clock/sun8iw18-rtc.h b/include/dt-bindings/clock/sun8iw18-rtc.h
  10492. new file mode 100644
  10493. index 000000000000..faab9de11005
  10494. --- /dev/null
  10495. +++ b/include/dt-bindings/clock/sun8iw18-rtc.h
  10496. @@ -0,0 +1,16 @@
  10497. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10498. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10499. +/*
  10500. + * Copyright (C) 2022 [email protected]
  10501. + */
  10502. +
  10503. +#ifndef _DT_BINDINGS_CLK_SUN8IW18_RTC_H_
  10504. +#define _DT_BINDINGS_CLK_SUN8IW18_RTC_H_
  10505. +
  10506. +#define CLK_IOSC 0
  10507. +#define CLK_IOSC_DIV32K 1
  10508. +#define CLK_RTC32K 2
  10509. +
  10510. +#define CLK_RTC_MAX_NO CLK_RTC32K
  10511. +
  10512. +#endif /* _DT_BINDINGS_CLK_SUN8IW18_RTC_H_ */
  10513. diff --git a/include/dt-bindings/clock/sun8iw20-ccu.h b/include/dt-bindings/clock/sun8iw20-ccu.h
  10514. new file mode 100644
  10515. index 000000000000..bbab8e1a0628
  10516. --- /dev/null
  10517. +++ b/include/dt-bindings/clock/sun8iw20-ccu.h
  10518. @@ -0,0 +1,161 @@
  10519. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  10520. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10521. +/*
  10522. + * Copyright (C) 2020 [email protected]
  10523. + */
  10524. +
  10525. +#ifndef _DT_BINDINGS_CLK_SUN8IW20_H_
  10526. +#define _DT_BINDINGS_CLK_SUN8IW20_H_
  10527. +
  10528. +#define CLK_OSC12M 0
  10529. +#define CLK_PLL_CPUX 1
  10530. +#define CLK_PLL_DDR0 2
  10531. +#define CLK_PLL_PERIPH0_PARENT 3
  10532. +#define CLK_PLL_PERIPH0 4
  10533. +#define CLK_PLL_PERIPH0_2X 5
  10534. +#define CLK_PLL_PERIPH0_800M 6
  10535. +#define CLK_PLL_PERIPH0_DIV3 7
  10536. +#define CLK_PLL_VIDEO0 8
  10537. +#define CLK_PLL_VIDEO0_2X 9
  10538. +#define CLK_PLL_VIDEO0_4X 10
  10539. +#define CLK_PLL_VIDEO1 11
  10540. +#define CLK_PLL_VIDEO1_2X 12
  10541. +#define CLK_PLL_VIDEO1_4X 13
  10542. +#define CLK_PLL_VE 14
  10543. +#define CLK_PLL_AUDIO0 15
  10544. +#define CLK_PLL_AUDIO0_2X 16
  10545. +#define CLK_PLL_AUDIO0_4X 17
  10546. +#define CLK_PLL_AUDIO1 18
  10547. +#define CLK_PLL_AUDIO1_DIV2 19
  10548. +#define CLK_PLL_AUDIO1_DIV5 20
  10549. +#define CLK_PLL_CPUX_DIV 21
  10550. +#define CLK_CPUX 22
  10551. +#define CLK_AXI 23
  10552. +#define CLK_APB 24
  10553. +#define CLK_PSI_AHB 25
  10554. +#define CLK_APB0 26
  10555. +#define CLK_APB1 27
  10556. +#define CLK_MBUS 28
  10557. +#define CLK_DE0 29
  10558. +#define CLK_BUS_DE0 30
  10559. +#define CLK_DI 31
  10560. +#define CLK_BUS_DI 32
  10561. +#define CLK_G2D 33
  10562. +#define CLK_BUS_G2D 34
  10563. +#define CLK_CE 35
  10564. +#define CLK_BUS_CE 36
  10565. +#define CLK_VE 37
  10566. +#define CLK_BUS_VE 38
  10567. +#define CLK_BUS_DMA 39
  10568. +#define CLK_BUS_MSGBOX0 40
  10569. +#define CLK_BUS_MSGBOX1 41
  10570. +#define CLK_BUS_MSGBOX2 42
  10571. +#define CLK_BUS_SPINLOCK 43
  10572. +#define CLK_BUS_HSTIMER 44
  10573. +#define CLK_AVS 45
  10574. +#define CLK_BUS_DBG 46
  10575. +#define CLK_BUS_PWM 47
  10576. +#define CLK_BUS_IOMMU 48
  10577. +#define CLK_DRAM 49
  10578. +#define CLK_MBUS_DMA 50
  10579. +#define CLK_MBUS_VE 51
  10580. +#define CLK_MBUS_CE 52
  10581. +#define CLK_MBUS_TVIN 53
  10582. +#define CLK_MBUS_CSI 54
  10583. +#define CLK_MBUS_G2D 55
  10584. +#define CLK_BUS_DRAM 56
  10585. +#define CLK_MMC0 57
  10586. +#define CLK_MMC1 58
  10587. +#define CLK_MMC2 59
  10588. +#define CLK_BUS_MMC0 60
  10589. +#define CLK_BUS_MMC1 61
  10590. +#define CLK_BUS_MMC2 62
  10591. +#define CLK_BUS_UART0 63
  10592. +#define CLK_BUS_UART1 64
  10593. +#define CLK_BUS_UART2 65
  10594. +#define CLK_BUS_UART3 66
  10595. +#define CLK_BUS_UART4 67
  10596. +#define CLK_BUS_UART5 68
  10597. +#define CLK_BUS_I2C0 69
  10598. +#define CLK_BUS_I2C1 70
  10599. +#define CLK_BUS_I2C2 71
  10600. +#define CLK_BUS_I2C3 72
  10601. +#define CLK_SPI0 75
  10602. +#define CLK_SPI1 76
  10603. +#define CLK_BUS_SPI0 77
  10604. +#define CLK_BUS_SPI1 78
  10605. +#define CLK_EMAC0_25M 79
  10606. +#define CLK_BUS_EMAC0 80
  10607. +#define CLK_IR_TX 81
  10608. +#define CLK_BUS_IR_TX 82
  10609. +#define CLK_BUS_GPADC 83
  10610. +#define CLK_BUS_THS 84
  10611. +#define CLK_I2S0 85
  10612. +#define CLK_I2S1 86
  10613. +#define CLK_I2S2 87
  10614. +#define CLK_I2S2_ASRC 88
  10615. +#define CLK_BUS_I2S0 89
  10616. +#define CLK_BUS_I2S1 90
  10617. +#define CLK_BUS_I2S2 91
  10618. +#define CLK_SPDIF_TX 92
  10619. +#define CLK_SPDIF_RX 93
  10620. +#define CLK_BUS_SPDIF 94
  10621. +#define CLK_DMIC 95
  10622. +#define CLK_BUS_DMIC 96
  10623. +#define CLK_AUDIO_DAC 97
  10624. +#define CLK_AUDIO_ADC 98
  10625. +#define CLK_BUS_AUDIO_CODEC 99
  10626. +#define CLK_USB_OHCI0 100
  10627. +#define CLK_USB_OHCI1 101
  10628. +#define CLK_BUS_OHCI0 102
  10629. +#define CLK_BUS_OHCI1 103
  10630. +#define CLK_BUS_EHCI0 104
  10631. +#define CLK_BUS_EHCI1 105
  10632. +#define CLK_BUS_OTG 106
  10633. +#define CLK_BUS_LRADC 107
  10634. +#define CLK_BUS_DPSS_TOP0 108
  10635. +#define CLK_HDMI_24M 109
  10636. +#define CLK_HDMI_CEC 110
  10637. +#define CLK_HDMI_CEC_32K 111
  10638. +#define CLK_BUS_HDMI 112
  10639. +#define CLK_MIPI_DSI 113
  10640. +#define CLK_BUS_MIPI_DSI 114
  10641. +#define CLK_TCON_LCD0 115
  10642. +#define CLK_BUS_TCON_LCD0 116
  10643. +#define CLK_TCON_TV 117
  10644. +#define CLK_BUS_TCON_TV 118
  10645. +#define CLK_TVE 119
  10646. +#define CLK_BUS_TVE 120
  10647. +#define CLK_BUS_TVE_TOP 121
  10648. +#define CLK_TVD 122
  10649. +#define CLK_BUS_TVD 123
  10650. +#define CLK_BUS_TVD_TOP 124
  10651. +#define CLK_LEDC 125
  10652. +#define CLK_BUS_LEDC 126
  10653. +#define CLK_CSI_TOP 127
  10654. +#define CLK_CSI0_MCLK 128
  10655. +#define CLK_BUS_CSI 129
  10656. +#define CLK_TPADC 130
  10657. +#define CLK_BUS_TPADC 131
  10658. +#define CLK_BUS_TZMA 132
  10659. +#define CLK_DSP 133
  10660. +#define CLK_BUS_DSP_CFG 134
  10661. +#define CLK_RISCV 135
  10662. +#define CLK_RISCV_AXI 136
  10663. +#define CLK_BUS_RISCV_CFG 137
  10664. +#define CLK_FANOUT_24M 138
  10665. +#define CLK_FANOUT_12M 139
  10666. +#define CLK_FANOUT_16M 140
  10667. +#define CLK_FANOUT_25M 141
  10668. +#define CLK_FANOUT_32K 142
  10669. +#define CLK_FANOUT_27M 143
  10670. +#define CLK_FANOUT_PCLK 144
  10671. +#define CLK_FANOUT0_OUT 145
  10672. +#define CLK_FANOUT1_OUT 146
  10673. +#define CLK_FANOUT2_OUT 147
  10674. +#define CLK_RISCV_RST 148
  10675. +#define CLK_BUS_RISCV 149
  10676. +
  10677. +#define CLK_MAX_NO CLK_BUS_RISCV
  10678. +
  10679. +#endif /* _DT_BINDINGS_CLK_SUN8IW20_H_ */
  10680. diff --git a/include/dt-bindings/clock/sun8iw20-r-ccu.h b/include/dt-bindings/clock/sun8iw20-r-ccu.h
  10681. new file mode 100644
  10682. index 000000000000..d96ae9dc0471
  10683. --- /dev/null
  10684. +++ b/include/dt-bindings/clock/sun8iw20-r-ccu.h
  10685. @@ -0,0 +1,22 @@
  10686. +/* SPDX-License-Identifier: GPL-2.0 */
  10687. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10688. +/*
  10689. + * Copyright (c) 2020 [email protected]
  10690. + */
  10691. +
  10692. +#ifndef _DT_BINDINGS_CLK_SUN8IW20_R_CCU_H_
  10693. +#define _DT_BINDINGS_CLK_SUN8IW20_R_CCU_H_
  10694. +
  10695. +#define CLK_R_AHB 0
  10696. +#define CLK_R_APB0 1
  10697. +#define CLK_R_APB0_TIMER 2
  10698. +#define CLK_R_APB0_TWD 3
  10699. +#define CLK_R_PPU 4
  10700. +#define CLK_R_APB0_IRRX 5
  10701. +#define CLK_R_APB0_BUS_IRRX 6
  10702. +#define CLK_R_AHB_BUS_RTC 7
  10703. +#define CLK_R_APB0_CPUCFG 8
  10704. +
  10705. +#define CLK_R_MAX_NO CLK_R_APB0_CPUCFG
  10706. +
  10707. +#endif /* _DT_BINDINGS_CLK_SUN8IW20_R_CCU_H_ */
  10708. diff --git a/include/dt-bindings/clock/sun8iw20-rtc.h b/include/dt-bindings/clock/sun8iw20-rtc.h
  10709. new file mode 100644
  10710. index 000000000000..cf91765f1f0f
  10711. --- /dev/null
  10712. +++ b/include/dt-bindings/clock/sun8iw20-rtc.h
  10713. @@ -0,0 +1,22 @@
  10714. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10715. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10716. +/*
  10717. + * Copyright (C) 2020 [email protected]
  10718. + */
  10719. +
  10720. +#ifndef _DT_BINDINGS_CLK_SUN8IW20_RTC_H_
  10721. +#define _DT_BINDINGS_CLK_SUN8IW20_RTC_H_
  10722. +
  10723. +#define CLK_IOSC 0
  10724. +#define CLK_EXT32K_GATE 1
  10725. +#define CLK_IOSC_DIV32K 2
  10726. +#define CLK_OSC32K 3
  10727. +#define CLK_DCXO24M_DIV32K 4
  10728. +#define CLK_RTC32K 5
  10729. +#define CLK_RTC_1K 6
  10730. +#define CLK_RTC_32K_FANOUT 7
  10731. +#define CLK_RTC_SPI 8
  10732. +
  10733. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  10734. +
  10735. +#endif /* _DT_BINDINGS_CLK_SUN8IW20_RTC_H_ */
  10736. diff --git a/include/dt-bindings/clock/sun8iw21-ccu.h b/include/dt-bindings/clock/sun8iw21-ccu.h
  10737. new file mode 100644
  10738. index 000000000000..7bf0883a55e0
  10739. --- /dev/null
  10740. +++ b/include/dt-bindings/clock/sun8iw21-ccu.h
  10741. @@ -0,0 +1,139 @@
  10742. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10743. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10744. +/*
  10745. + * Copyright (C) 2023 [email protected]
  10746. + */
  10747. +
  10748. +#ifndef _DT_BINDINGS_CLK_SUN8IW21_H_
  10749. +#define _DT_BINDINGS_CLK_SUN8IW21_H_
  10750. +
  10751. +#define CLK_PLL_CPU 0
  10752. +#define CLK_PLL_DDR 1
  10753. +#define CLK_PLL_PERI_PARENT 2
  10754. +#define CLK_PLL_PERI_2X 3
  10755. +#define CLK_PLL_PERI_DIV3 4
  10756. +#define CLK_PLL_PERI_800M 5
  10757. +#define CLK_PLL_PERI_480M 6
  10758. +#define CLK_PLL_PERI_600M 7
  10759. +#define CLK_PLL_PERI_400M 8
  10760. +#define CLK_PLL_PERI_300M 9
  10761. +#define CLK_PLL_PERI_200M 10
  10762. +#define CLK_PLL_PERI_160M 11
  10763. +#define CLK_PLL_PERI_150M 12
  10764. +#define CLK_PLL_VIDEO_4X 13
  10765. +#define CLK_PLL_VIDEO_2X 14
  10766. +#define CLK_PLL_VIDEO_1X 15
  10767. +#define CLK_PLL_CSI_4X 16
  10768. +#define CLK_PLL_AUDIO_DIV2 17
  10769. +#define CLK_PLL_AUDIO_DIV5 18
  10770. +#define CLK_PLL_AUDIO_4X 19
  10771. +#define CLK_PLL_AUDIO_1X 20
  10772. +#define CLK_PLL_NPU_4X 21
  10773. +#define CLK_CPU 22
  10774. +#define CLK_CPU_AXI 23
  10775. +#define CLK_CPU_APB 24
  10776. +#define CLK_BUS_CPU 25
  10777. +#define CLK_AHB 26
  10778. +#define CLK_APB0 27
  10779. +#define CLK_APB1 28
  10780. +#define CLK_DE 29
  10781. +#define CLK_BUS_DE 30
  10782. +#define CLK_G2D 31
  10783. +#define CLK_BUS_G2D 32
  10784. +#define CLK_CE 33
  10785. +#define CLK_CE_SYS 34
  10786. +#define CLK_BUS_CE 35
  10787. +#define CLK_VE 36
  10788. +#define CLK_BUS_VE 37
  10789. +#define CLK_NPU 38
  10790. +#define CLK_BUS_NPU 39
  10791. +#define CLK_DMA 40
  10792. +#define CLK_MSGBOX1 41
  10793. +#define CLK_MSGBOX0 42
  10794. +#define CLK_SPINLOCK 43
  10795. +#define CLK_HSTIMER 44
  10796. +#define CLK_AVS 45
  10797. +#define CLK_DBGSYS 46
  10798. +#define CLK_PWM 47
  10799. +#define CLK_IOMMU 48
  10800. +#define CLK_DRAM 49
  10801. +#define CLK_MBUS_NPU_GATE 50
  10802. +#define CLK_MBUS_VID_IN_GATE 51
  10803. +#define CLK_MBUS_VID_OUT_GATE 52
  10804. +#define CLK_MBUS_G2D 53
  10805. +#define CLK_MBUS_ISP 54
  10806. +#define CLK_MBUS_CSI 55
  10807. +#define CLK_MBUS_CE_GATE 56
  10808. +#define CLK_MBUS_VE 57
  10809. +#define CLK_MBUS_DMA 58
  10810. +#define CLK_BUS_DRAM 59
  10811. +#define CLK_SMHC0 60
  10812. +#define CLK_SMHC1 61
  10813. +#define CLK_SMHC2 62
  10814. +#define CLK_BUS_SMHC2 63
  10815. +#define CLK_BUS_SMHC1 64
  10816. +#define CLK_BUS_SMHC0 65
  10817. +#define CLK_UART3 66
  10818. +#define CLK_UART2 67
  10819. +#define CLK_UART1 68
  10820. +#define CLK_UART0 69
  10821. +#define CLK_TWI4 70
  10822. +#define CLK_TWI3 71
  10823. +#define CLK_TWI2 72
  10824. +#define CLK_TWI1 73
  10825. +#define CLK_TWI0 74
  10826. +#define CLK_SPI0 75
  10827. +#define CLK_SPI1 76
  10828. +#define CLK_SPI2 77
  10829. +#define CLK_SPI3 78
  10830. +#define CLK_SPIF 79
  10831. +#define CLK_BUS_SPIF 80
  10832. +#define CLK_BUS_SPI3 81
  10833. +#define CLK_BUS_SPI2 82
  10834. +#define CLK_BUS_SPI1 83
  10835. +#define CLK_BUS_SPI0 84
  10836. +#define CLK_GMAC_25M 85
  10837. +#define CLK_GMAC_25M_CLK_SRC 86
  10838. +#define CLK_GMAC 87
  10839. +#define CLK_GPADC 88
  10840. +#define CLK_THS 89
  10841. +#define CLK_I2S0 90
  10842. +#define CLK_I2S1 91
  10843. +#define CLK_BUS_I2S1 92
  10844. +#define CLK_BUS_I2S0 93
  10845. +#define CLK_DMIC 94
  10846. +#define CLK_BUS_DMIC 95
  10847. +#define CLK_AUDIO_CODEC_DAC 96
  10848. +#define CLK_AUDIO_CODEC_ADC 97
  10849. +#define CLK_AUDIO_CODEC 98
  10850. +#define CLK_USB 99
  10851. +#define CLK_USBOTG0 100
  10852. +#define CLK_USBEHCI0 101
  10853. +#define CLK_USBOHCI0 102
  10854. +#define CLK_DPSS_TOP 103
  10855. +#define CLK_DSI 104
  10856. +#define CLK_BUS_DSI 105
  10857. +#define CLK_TCONLCD 106
  10858. +#define CLK_BUS_TCONLCD 107
  10859. +#define CLK_CSI 108
  10860. +#define CLK_CSI_MASTER0 109
  10861. +#define CLK_CSI_MASTER1 110
  10862. +#define CLK_CSI_MASTER2 111
  10863. +#define CLK_BUS_CSI 112
  10864. +#define CLK_WIEGAND 113
  10865. +#define CLK_E907_CORE_DIV 114
  10866. +#define CLK_E907_AXI_DIV 115
  10867. +#define CLK_E907_CORE_RST 116
  10868. +#define CLK_E907_DBG_RST 117
  10869. +#define CLK_E907_CORE_GATE 118
  10870. +#define CLK_RISCV_CFG 119
  10871. +#define CLK_CPUS_HCLK_GATE 120
  10872. +#define CLK_RES_DCAP_24M 121
  10873. +#define CLK_GPADC_24M 122
  10874. +#define CLK_WIEGAND_24M 123
  10875. +#define CLK_USB_24M 124
  10876. +#define CLK_GPADC_SEL 125
  10877. +
  10878. +#define CLK_MAX_NO (CLK_GPADC_SEL + 1)
  10879. +
  10880. +#endif /* _DT_BINDINGS_CLK_SUN8IW21_H_ */
  10881. diff --git a/include/dt-bindings/clock/sun8iw21-r-ccu.h b/include/dt-bindings/clock/sun8iw21-r-ccu.h
  10882. new file mode 100644
  10883. index 000000000000..f52b731e826b
  10884. --- /dev/null
  10885. +++ b/include/dt-bindings/clock/sun8iw21-r-ccu.h
  10886. @@ -0,0 +1,16 @@
  10887. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10888. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10889. +/*
  10890. + * Copyright (C) 2023 [email protected]
  10891. + */
  10892. +#ifndef _DT_BINDINGS_CLK_SUN8IW21_R_CCU_H_
  10893. +#define _DT_BINDINGS_CLK_SUN8IW21_R_CCU_H_
  10894. +
  10895. +#define CLK_R_TWD 0
  10896. +#define CLK_R_PPU 1
  10897. +#define CLK_R_RTC 2
  10898. +#define CLK_R_CPUCFG 3
  10899. +
  10900. +#define CLK_R_MAX_NO (CLK_R_CPUCFG + 1)
  10901. +
  10902. +#endif /* _DT_BINDINGS_CLK_SUN8IW21_R_CCU_H_ */
  10903. diff --git a/include/dt-bindings/clock/sun8iw21-rtc.h b/include/dt-bindings/clock/sun8iw21-rtc.h
  10904. new file mode 100644
  10905. index 000000000000..a1c0de1259a7
  10906. --- /dev/null
  10907. +++ b/include/dt-bindings/clock/sun8iw21-rtc.h
  10908. @@ -0,0 +1,24 @@
  10909. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10910. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10911. +/*
  10912. + * Copyright (C) 2023 [email protected]
  10913. + */
  10914. +
  10915. +#ifndef _DT_BINDINGS_CLK_SUN8IW21_RTC_H_
  10916. +#define _DT_BINDINGS_CLK_SUN8IW21_RTC_H_
  10917. +
  10918. +
  10919. +#define CLK_DCXO24M_OUT 0
  10920. +#define CLK_IOSC 1
  10921. +#define CLK_EXT32K_GATE 2
  10922. +#define CLK_IOSC_DIV32K 3
  10923. +#define CLK_OSC32K 4
  10924. +#define CLK_DCXO24M_DIV32K 5
  10925. +#define CLK_RTC32K 6
  10926. +#define CLK_RTC_1K 7
  10927. +#define CLK_OSC32K_OUT 8
  10928. +#define CLK_RTC_SPI 9
  10929. +
  10930. +#define CLK_RTC_MAX_NO CLK_RTC_SPI
  10931. +
  10932. +#endif /* _DT_BINDINGS_CLK_SUN8IW21_RTC_H_ */
  10933. diff --git a/include/dt-bindings/clock/sunxi-ccu.h b/include/dt-bindings/clock/sunxi-ccu.h
  10934. new file mode 100644
  10935. index 000000000000..7ba691de3d42
  10936. --- /dev/null
  10937. +++ b/include/dt-bindings/clock/sunxi-ccu.h
  10938. @@ -0,0 +1,41 @@
  10939. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10940. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10941. +/*
  10942. + * Copyright (C) 2023 [email protected]
  10943. + */
  10944. +
  10945. +#ifndef __DT_SUNXI_CLK_H
  10946. +#define __DT_SUNXI_CLK_H
  10947. +
  10948. +/**
  10949. + * TR_X represents different configurations in different boards
  10950. + * Such as:
  10951. + *
  10952. + * Type1 (for example: sun251w1)
  10953. + * TR_0: DC=0
  10954. + * TR_1: DC=1
  10955. + * TR_2: 1bit
  10956. + * TR_3: Nbit
  10957. + *
  10958. + * Type2 (for example: sun65w1)
  10959. + * TR_0: pulse swallow
  10960. + * TR_1: 1bit
  10961. + * TR_2: 2bit
  10962. + * TR_3: 3bit
  10963. + *
  10964. + */
  10965. +#define TR_0 0
  10966. +#define TR_1 1
  10967. +#define TR_2 2
  10968. +#define TR_3 3
  10969. +
  10970. +#define FREQ_31_5 0
  10971. +#define FREQ_32 1
  10972. +#define FREQ_32_5 2
  10973. +#define FREQ_33 3
  10974. +
  10975. +#define SDM_DIR_UP 0
  10976. +#define SDM_DIR_DOWN 1
  10977. +#define SDM_DIR_NONE 2
  10978. +
  10979. +#endif
  10980. diff --git a/include/dt-bindings/clock/sunxi-clk.h b/include/dt-bindings/clock/sunxi-clk.h
  10981. new file mode 100644
  10982. index 000000000000..7727a50f4e8e
  10983. --- /dev/null
  10984. +++ b/include/dt-bindings/clock/sunxi-clk.h
  10985. @@ -0,0 +1,18 @@
  10986. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  10987. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  10988. +/*
  10989. + * Copyright (C) 2022 [email protected]
  10990. + */
  10991. +
  10992. +#ifndef __DT_SUNXI_CLK_H
  10993. +#define __DT_SUNXI_CLK_H
  10994. +
  10995. +#define TR_1 0
  10996. +#define TR_N 1
  10997. +
  10998. +#define FREQ_31_5 0
  10999. +#define FREQ_32 1
  11000. +#define FREQ_32_5 2
  11001. +#define FREQ_33 3
  11002. +
  11003. +#endif
  11004. diff --git a/include/dt-bindings/display/lcd_command.h b/include/dt-bindings/display/lcd_command.h
  11005. new file mode 100644
  11006. index 000000000000..486c32757946
  11007. --- /dev/null
  11008. +++ b/include/dt-bindings/display/lcd_command.h
  11009. @@ -0,0 +1,48 @@
  11010. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  11011. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11012. +#ifndef __LCD_COMMAND_H__
  11013. +#define __LCD_COMMAND_H__
  11014. +
  11015. + /* void (*p_func)(u32 sel) */
  11016. +#define SUNXI_LCD_TCON_ENABLE 0
  11017. +#define SUNXI_LCD_TCON_DISABLE 1
  11018. +#define SUNXI_LCD_BACKLIGHT_ENABLE 2
  11019. +#define SUNXI_LCD_BACKLIGHT_DISABLE 3
  11020. +
  11021. + /* s32 (*p_func)(u32 sel) */
  11022. +#define SUNXI_LCD_PWM_ENABLE 10
  11023. +#define SUNXI_LCD_PWM_DISABLE 11
  11024. +#define SUNXI_LCD_CPU_SET_AUTO_MODE 12
  11025. +#define SUNXI_LCD_DSI_CLK_ENABLE 13
  11026. +#define SUNXI_LCD_DSI_CLK_DISABLE 14
  11027. +
  11028. + /* void (*p_func)(u32 sel, u32, u32) */
  11029. +#define SUNXI_LCD_DSI_MODE_SWITCH 20
  11030. +
  11031. + /* s32 (*p_func)(u32) */
  11032. +#define SUNXI_LCD_DELAY_MS 30
  11033. +#define SUNXI_LCD_DELAY_US 31
  11034. +
  11035. + /* void (*p_func)(u32 sel, u32) */
  11036. +#define SUNXI_LCD_POWER_ENABLE 40
  11037. +#define SUNXI_LCD_POWER_DISABLE 41
  11038. +#define SUNXI_LCD_CPU_WRITE_INDEX 42
  11039. +#define SUNXI_LCD_CPU_WRITE_DATA 43
  11040. +#define SUNXI_LCD_DSI_SET_MAX_RET_SIZE 44
  11041. +#define SUNXI_LCD_PIN_CFG 45
  11042. +
  11043. + /* s32 (*p_func)(u32 sel, u32, u32) */
  11044. +#define SUNXI_LCD_CPU_WRITE 50
  11045. +#define SUNXI_LCD_GPIO_SET_VALUE 51
  11046. +#define SUNXI_LCD_GPIO_SET_DIRECTION 52
  11047. +
  11048. + /* s32 (*p_func)(u32 sel, u8, u8 *, u32 *) */
  11049. +#define SUNXI_LCD_DSI_DCS_READ 80
  11050. +
  11051. + /* s32 (*p_func)(u32 sel, u8, u8 *, u32) */
  11052. +#define DSI_DCS_WR 90
  11053. +#define SUNXI_LCD_DSI_DCS_WRITE 91
  11054. +#define SUNXI_LCD_DSI_GEN_WRITE 92
  11055. +
  11056. +
  11057. +#endif
  11058. diff --git a/include/dt-bindings/display/sunxi-lcd.h b/include/dt-bindings/display/sunxi-lcd.h
  11059. new file mode 100644
  11060. index 000000000000..7b1100f9d1f6
  11061. --- /dev/null
  11062. +++ b/include/dt-bindings/display/sunxi-lcd.h
  11063. @@ -0,0 +1,33 @@
  11064. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  11065. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11066. +#ifndef __SUNXI_LCD_H__
  11067. +#define __SUNXI_LCD_H__
  11068. +
  11069. +/* displl */
  11070. +#define CLK_PLL_DISPLL 0
  11071. +#define CLK_DSI_LS 1
  11072. +#define CLK_DSI_HS 2
  11073. +#define CLK_LVDS_OR_RGB 3
  11074. +
  11075. +/* dsi */
  11076. +#define MIPI_DSI_MODE_VIDEO 1
  11077. +#define MIPI_DSI_MODE_VIDEO_BURST (1<<1)
  11078. +#define MIPI_DSI_MODE_NO_EOT_PACKET (1<<9)
  11079. +#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1<<10)
  11080. +#define MIPI_DSI_EN_3DFIFO (1<<21)
  11081. +#define MIPI_DSI_SLAVE_MODE (1<<22)
  11082. +#define MIPI_DSI_MODE_VRR (1<<24)
  11083. +#define MIPI_DSI_SYNC_INCELL (1<<25)
  11084. +#define MIPI_DSI_ASYNC_INCELL (1<<26)
  11085. +
  11086. +/* lvds */
  11087. +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010
  11088. +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
  11089. +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
  11090. +
  11091. +/* rgb */
  11092. +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017
  11093. +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
  11094. +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a
  11095. +
  11096. +#endif
  11097. diff --git a/include/dt-bindings/gpio/sun4i-gpio.h b/include/dt-bindings/gpio/sun4i-gpio.h
  11098. new file mode 100644
  11099. index 000000000000..44344c1ff16f
  11100. --- /dev/null
  11101. +++ b/include/dt-bindings/gpio/sun4i-gpio.h
  11102. @@ -0,0 +1,28 @@
  11103. +/* SPDX-License-Identifier: GPL-2.0-only */
  11104. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11105. +/*
  11106. + * Author: [email protected]
  11107. + */
  11108. +
  11109. +#ifndef __DT_SUN4I_GPIO_H
  11110. +#define __DT_SUN4I_GPIO_H
  11111. +
  11112. +/* pio */
  11113. +#define PA 0
  11114. +#define PB 1
  11115. +#define PC 2
  11116. +#define PD 3
  11117. +#define PE 4
  11118. +#define PF 5
  11119. +#define PG 6
  11120. +#define PH 7
  11121. +#define PI 8
  11122. +#define PJ 9
  11123. +#define PK 10
  11124. +
  11125. +/* r pio */
  11126. +#define PL 0
  11127. +#define PM 1
  11128. +#define PN 2
  11129. +
  11130. +#endif /* __DT_SUN4I_GPIO_H */
  11131. diff --git a/include/dt-bindings/gpio/sun55iw3-share-irq-dt.h b/include/dt-bindings/gpio/sun55iw3-share-irq-dt.h
  11132. new file mode 100644
  11133. index 000000000000..3dda39731d1c
  11134. --- /dev/null
  11135. +++ b/include/dt-bindings/gpio/sun55iw3-share-irq-dt.h
  11136. @@ -0,0 +1,99 @@
  11137. +/* SPDX-License-Identifier: GPL-2.0 */
  11138. +/*
  11139. + * sunxi's Remote Processor Share Interrupt Platform Head File
  11140. + *
  11141. + * Copyright (C) 2023 Allwinnertech - All Rights Reserved
  11142. + *
  11143. + * Author: lijiajian <[email protected]>
  11144. + *
  11145. + * This program is free software; you can redistribute it and/or modify
  11146. + * it under the terms of the GNU General Public License version 2 as
  11147. + * published by the Free Software Foundation.
  11148. + */
  11149. +
  11150. +#ifndef _SUN55IW3_SHARE_INTERRUPT_DT_H
  11151. +#define _SUN55IW3_SHARE_INTERRUPT_DT_H
  11152. +
  11153. +#define RINTC_IRQ_MASK 0xffff0000
  11154. +#define RISCV_IRQn(major, sub) ((major) * 100 + (sub))
  11155. +#define DSP_IRQn(major, sub) (((sub) * 200 + (major)) | RINTC_IRQ_MASK)
  11156. +#define ARM_IRQn(_x) ((_x) - 32)
  11157. +
  11158. +/* sunxi share-interrupt format
  11159. + * major type remote_core_irq flags
  11160. + *
  11161. + * Generic Type Define
  11162. + * type = 0x0 --- normal irq
  11163. + *
  11164. + * GPIO Type Define
  11165. + * type = 0x1 --- GPIOA
  11166. + * type = 0x2 --- GPIOB
  11167. + * type = 0x3 --- GPIOC
  11168. + * type = 0x4 --- GPIOD
  11169. + * type = 0x5 --- GPIOE
  11170. + * type = 0x6 --- GPIOF
  11171. + * type = 0x7 --- GPIOG
  11172. + * type = 0x8 --- GPIOH
  11173. + * type = 0x9 --- GPIOI
  11174. + * type = 0xa --- GPIOJ
  11175. + * type = 0xb --- GPIOK
  11176. + * type = 0xc --- GPIOL
  11177. + * type = 0xd --- GPIOM
  11178. + * type = 0xe --- GPION
  11179. + */
  11180. +
  11181. +#define RISCV_GPIOB (1 0x2 RISCV_IRQn(98, 6) ARM_IRQn(101))
  11182. +#define RISCV_GPIOC (2 0x3 RISCV_IRQn(98, 8) ARM_IRQn(103))
  11183. +#define RISCV_GPIOD (3 0x4 RISCV_IRQn(99, 2) ARM_IRQn(105))
  11184. +#define RISCV_GPIOE (4 0x5 RISCV_IRQn(99, 4) ARM_IRQn(107))
  11185. +#define RISCV_GPIOF (5 0x6 RISCV_IRQn(99, 6) ARM_IRQn(109))
  11186. +#define RISCV_GPIOG (6 0x7 RISCV_IRQn(99, 8) ARM_IRQn(111))
  11187. +#define RISCV_GPIOH (7 0x8 RISCV_IRQn(100, 2) ARM_IRQn(113))
  11188. +#define RISCV_GPIOI (8 0x9 RISCV_IRQn(100, 4) ARM_IRQn(115))
  11189. +#define RISCV_GPIOJ (9 0xa RISCV_IRQn(100, 6) ARM_IRQn(117))
  11190. +#define RISCV_GPIOK (10 0xb RISCV_IRQn(107, 5) ARM_IRQn(172))
  11191. +#define RISCV_GPIOL (11 0xc RISCV_IRQn(63, 0) ARM_IRQn(191))
  11192. +#define RISCV_GPIOM (12 0xd RISCV_IRQn(65, 0) ARM_IRQn(193))
  11193. +
  11194. +#define DSP_GPIOB (13 0x2 DSP_IRQn(46, 6) ARM_IRQn(101))
  11195. +#define DSP_GPIOC (14 0x3 DSP_IRQn(46, 8) ARM_IRQn(103))
  11196. +#define DSP_GPIOD (15 0x4 DSP_IRQn(47, 2) ARM_IRQn(105))
  11197. +#define DSP_GPIOE (16 0x5 DSP_IRQn(47, 4) ARM_IRQn(107))
  11198. +#define DSP_GPIOF (17 0x6 DSP_IRQn(47, 6) ARM_IRQn(109))
  11199. +#define DSP_GPIOG (18 0x7 DSP_IRQn(47, 8) ARM_IRQn(111))
  11200. +#define DSP_GPIOH (19 0x8 DSP_IRQn(48, 2) ARM_IRQn(113))
  11201. +#define DSP_GPIOI (20 0x9 DSP_IRQn(48, 4) ARM_IRQn(115))
  11202. +#define DSP_GPIOJ (21 0xa DSP_IRQn(48, 6) ARM_IRQn(117))
  11203. +#define DSP_GPIOK (22 0xb DSP_IRQn(55, 5) ARM_IRQn(172))
  11204. +#define DSP_GPIOL (23 0xc DSP_IRQn(2, 0) ARM_IRQn(191))
  11205. +#define DSP_GPIOM (24 0xd DSP_IRQn(4, 0) ARM_IRQn(193))
  11206. +
  11207. +#define ARM_PA_IRQ_NUM ARM_IRQn(99)
  11208. +#define ARM_PB_IRQ_NUM ARM_IRQn(101)
  11209. +#define ARM_PC_IRQ_NUM ARM_IRQn(103)
  11210. +#define ARM_PD_IRQ_NUM ARM_IRQn(105)
  11211. +#define ARM_PE_IRQ_NUM ARM_IRQn(107)
  11212. +#define ARM_PF_IRQ_NUM ARM_IRQn(109)
  11213. +#define ARM_PG_IRQ_NUM ARM_IRQn(111)
  11214. +#define ARM_PH_IRQ_NUM ARM_IRQn(113)
  11215. +#define ARM_PI_IRQ_NUM ARM_IRQn(115)
  11216. +#define ARM_PJ_IRQ_NUM ARM_IRQn(117)
  11217. +#define ARM_PK_IRQ_NUM ARM_IRQn(172)
  11218. +#define ARM_PL_IRQ_NUM ARM_IRQn(191)
  11219. +#define ARM_PM_IRQ_NUM ARM_IRQn(193)
  11220. +
  11221. +#define A55_PA_IRQ_NUM (99)
  11222. +#define A55_PB_IRQ_NUM (101)
  11223. +#define A55_PC_IRQ_NUM (103)
  11224. +#define A55_PD_IRQ_NUM (105)
  11225. +#define A55_PE_IRQ_NUM (107)
  11226. +#define A55_PF_IRQ_NUM (109)
  11227. +#define A55_PG_IRQ_NUM (111)
  11228. +#define A55_PH_IRQ_NUM (113)
  11229. +#define A55_PI_IRQ_NUM (115)
  11230. +#define A55_PJ_IRQ_NUM (117)
  11231. +#define A55_PK_IRQ_NUM (172)
  11232. +#define A55_PL_IRQ_NUM (191)
  11233. +#define A55_PM_IRQ_NUM (193)
  11234. +
  11235. +#endif
  11236. diff --git a/include/dt-bindings/gpio/sun8iw21-share-irq.h b/include/dt-bindings/gpio/sun8iw21-share-irq.h
  11237. new file mode 100644
  11238. index 000000000000..094317c30679
  11239. --- /dev/null
  11240. +++ b/include/dt-bindings/gpio/sun8iw21-share-irq.h
  11241. @@ -0,0 +1,54 @@
  11242. +/* SPDX-License-Identifier: GPL-2.0 */
  11243. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11244. +/*
  11245. + * sunxi's Remote Processor Share Interrupt Platform Head File
  11246. + *
  11247. + * Copyright (C) 2022 Allwinnertech - All Rights Reserved
  11248. + *
  11249. + * Author: lijiajian <[email protected]>
  11250. + *
  11251. + * This program is free software; you can redistribute it and/or modify
  11252. + * it under the terms of the GNU General Public License version 2 as
  11253. + * published by the Free Software Foundation.
  11254. + */
  11255. +
  11256. +#ifndef _DT_BINDINGS_SHATE_INTERRUPT_H
  11257. +#define _DT_BINDINGS_SHATE_INTERRUPT_H
  11258. +
  11259. +/* sunxi share-interrupt format
  11260. + * major type flags
  11261. + *
  11262. + * Generic Type Define
  11263. + * type = 0x0 --- normal irq
  11264. + *
  11265. + * GPIO Type Define
  11266. + * type = 0x1 --- GPIOA
  11267. + * type = 0x2 --- GPIOB
  11268. + * type = 0x3 --- GPIOC
  11269. + * type = 0x4 --- GPIOD
  11270. + * type = 0x5 --- GPIOE
  11271. + * type = 0x6 --- GPIOF
  11272. + * type = 0x7 --- GPIOG
  11273. + * type = 0x8 --- GPIOH
  11274. + * type = 0x9 --- GPIOI
  11275. + * ...
  11276. + */
  11277. +#define SH_GPIOA_IRQ 1 /* major */
  11278. +#define SH_GPIOC_IRQ 2 /* major */
  11279. +#define SH_GPIOD_IRQ 3 /* major */
  11280. +#define SH_GPIOE_IRQ 4 /* major */
  11281. +#define SH_GPIOF_IRQ 5 /* major */
  11282. +#define SH_GPIOG_IRQ 6 /* major */
  11283. +#define SH_GPIOH_IRQ 7 /* major */
  11284. +#define SH_GPIOI_IRQ 8 /* major */
  11285. +
  11286. +#define SH_GPIOA 0x1 /* type */
  11287. +#define SH_GPIOC 0x3 /* type */
  11288. +#define SH_GPIOD 0x4 /* type */
  11289. +#define SH_GPIOE 0x5 /* type */
  11290. +#define SH_GPIOF 0x6 /* type */
  11291. +#define SH_GPIOG 0x7 /* type */
  11292. +#define SH_GPIOH 0x8 /* type */
  11293. +#define SH_GPIOI 0x9 /* type */
  11294. +
  11295. +#endif
  11296. diff --git a/include/dt-bindings/power/a523-power.h b/include/dt-bindings/power/a523-power.h
  11297. new file mode 100644
  11298. index 000000000000..bea74bad660d
  11299. --- /dev/null
  11300. +++ b/include/dt-bindings/power/a523-power.h
  11301. @@ -0,0 +1,18 @@
  11302. +/* SPDX-License-Identifier: GPL-2.0 */
  11303. +#ifndef __DT_BINDINGS_POWER_A523_H__
  11304. +#define __DT_BINDINGS_POWER_A523_H__
  11305. +
  11306. +#define A523_PD_DSP 0
  11307. +#define A523_PD_NPU 1
  11308. +#define A523_PD_AUDIO 2
  11309. +#define A523_PD_SRAM 3
  11310. +#define A523_PD_RISCV 4
  11311. +#define A523_PCK_VE 0
  11312. +#define A523_PCK_GPU 1
  11313. +#define A523_PCK_VI 2
  11314. +#define A523_PCK_VO0 3
  11315. +#define A523_PCK_VO1 4
  11316. +#define A523_PCK_DE 5
  11317. +#define A523_PCK_NAND 6
  11318. +#define A523_PCK_PCIE 7
  11319. +#endif
  11320. diff --git a/include/dt-bindings/power/r528-power.h b/include/dt-bindings/power/r528-power.h
  11321. new file mode 100644
  11322. index 000000000000..e3de44ae7179
  11323. --- /dev/null
  11324. +++ b/include/dt-bindings/power/r528-power.h
  11325. @@ -0,0 +1,9 @@
  11326. +/* SPDX-License-Identifier: GPL-2.0 */
  11327. +#ifndef __DT_BINDINGS_POWER_R528_H__
  11328. +#define __DT_BINDINGS_POWER_R528_H__
  11329. +
  11330. +#define R528_PD_CPU 0
  11331. +#define R528_PD_VE 1
  11332. +#define R528_PD_DSP 2
  11333. +
  11334. +#endif
  11335. diff --git a/include/dt-bindings/power/sun60iw2-power.h b/include/dt-bindings/power/sun60iw2-power.h
  11336. new file mode 100644
  11337. index 000000000000..6f05062cabe9
  11338. --- /dev/null
  11339. +++ b/include/dt-bindings/power/sun60iw2-power.h
  11340. @@ -0,0 +1,17 @@
  11341. +/* SPDX-License-Identifier: GPL-2.0 */
  11342. +#ifndef __DT_BINDINGS_POWER_SUN60IW2_H__
  11343. +#define __DT_BINDINGS_POWER_SUN60IW2_H__
  11344. +
  11345. +#define SUN60IW2_PCK_VI 0
  11346. +#define SUN60IW2_PCK_DE_SYS 1
  11347. +#define SUN60IW2_PCK_VE_DEC 2
  11348. +#define SUN60IW2_PCK_VE_ENC 3
  11349. +#define SUN60IW2_PCK_NPU 4
  11350. +#define SUN60IW2_PCK_GPU_TOP 5
  11351. +#define SUN60IW2_PCK_GPU_CORE 6
  11352. +#define SUN60IW2_PCK_PCIE 7
  11353. +#define SUN60IW2_PCK_USB2 8
  11354. +#define SUN60IW2_PCK_VO 9
  11355. +#define SUN60IW2_PCK_VO1 10
  11356. +
  11357. +#endif
  11358. diff --git a/include/dt-bindings/power/tv303-power.h b/include/dt-bindings/power/tv303-power.h
  11359. new file mode 100644
  11360. index 000000000000..964d6a971989
  11361. --- /dev/null
  11362. +++ b/include/dt-bindings/power/tv303-power.h
  11363. @@ -0,0 +1,11 @@
  11364. +/* SPDX-License-Identifier: GPL-2.0 */
  11365. +#ifndef __DT_BINDINGS_POWER_TV303_H__
  11366. +#define __DT_BINDINGS_POWER_TV303_H__
  11367. +
  11368. +#define TV303_PD_GPU 0
  11369. +#define TV303_PD_TVFE 1
  11370. +#define TV303_PD_TVCAP 2
  11371. +#define TV303_PD_VE 3
  11372. +#define TV303_PD_AV1 4
  11373. +
  11374. +#endif
  11375. diff --git a/include/dt-bindings/power/v851-power.h b/include/dt-bindings/power/v851-power.h
  11376. new file mode 100644
  11377. index 000000000000..a6560a79d775
  11378. --- /dev/null
  11379. +++ b/include/dt-bindings/power/v851-power.h
  11380. @@ -0,0 +1,9 @@
  11381. +/* SPDX-License-Identifier: GPL-2.0 */
  11382. +#ifndef __DT_BINDINGS_POWER_V851_H__
  11383. +#define __DT_BINDINGS_POWER_V851_H__
  11384. +
  11385. +#define V851_PD_E907 0
  11386. +#define V851_PD_NPU 1
  11387. +#define V851_PD_VE 2
  11388. +
  11389. +#endif
  11390. diff --git a/include/dt-bindings/power/v853-power.h b/include/dt-bindings/power/v853-power.h
  11391. new file mode 100644
  11392. index 000000000000..123da9a24f2c
  11393. --- /dev/null
  11394. +++ b/include/dt-bindings/power/v853-power.h
  11395. @@ -0,0 +1,9 @@
  11396. +/* SPDX-License-Identifier: GPL-2.0 */
  11397. +#ifndef __DT_BINDINGS_POWER_V853_H__
  11398. +#define __DT_BINDINGS_POWER_V853_H__
  11399. +
  11400. +#define V853_PD_E907 0
  11401. +#define V853_PD_NPU 1
  11402. +#define V853_PD_VE 2
  11403. +
  11404. +#endif
  11405. diff --git a/include/dt-bindings/reset/sun20iw5-aon-ccu.h b/include/dt-bindings/reset/sun20iw5-aon-ccu.h
  11406. new file mode 100644
  11407. index 000000000000..fe6d40d0320b
  11408. --- /dev/null
  11409. +++ b/include/dt-bindings/reset/sun20iw5-aon-ccu.h
  11410. @@ -0,0 +1,12 @@
  11411. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11412. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11413. +/*
  11414. + * Copyright (c) 2023 [email protected]
  11415. + */
  11416. +
  11417. +#ifndef _DT_BINDINGS_RESET_SUN20IW5_AON_H_
  11418. +#define _DT_BINDINGS_RESET_SUN20IW5_AON_H_
  11419. +
  11420. +#define RST_BUS_WLAN 0
  11421. +
  11422. +#endif /* _DT_BINDINGS_RESET_SUN20IW5_H_ */
  11423. diff --git a/include/dt-bindings/reset/sun20iw5-app-ccu.h b/include/dt-bindings/reset/sun20iw5-app-ccu.h
  11424. new file mode 100644
  11425. index 000000000000..221776724033
  11426. --- /dev/null
  11427. +++ b/include/dt-bindings/reset/sun20iw5-app-ccu.h
  11428. @@ -0,0 +1,67 @@
  11429. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11430. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11431. +/*
  11432. + * Copyright (c) 2023 [email protected]
  11433. + */
  11434. +
  11435. +#ifndef _DT_BINDINGS_RESET_SUN20IW5_APP_H_
  11436. +#define _DT_BINDINGS_RESET_SUN20IW5_APP_H_
  11437. +
  11438. +#define RST_BUS_DPSSTOP 0
  11439. +#define RST_BUS_WKUP 1
  11440. +#define RST_BUS_MCSI 2
  11441. +#define RST_BUS_HRESETN_MCSI 3
  11442. +#define RST_BUS_G2D 4
  11443. +#define RST_BUS_DE 5
  11444. +#define RST_BUS_GMAC 6
  11445. +#define RST_BUS_USBPHY 7
  11446. +#define RST_BUS_USBOHCI 8
  11447. +#define RST_BUS_USBEHCI 9
  11448. +#define RST_BUS_USBOTG 10
  11449. +#define RST_BUS_USB 11
  11450. +#define RST_BUS_UART3 12
  11451. +#define RST_BUS_UART2 13
  11452. +#define RST_BUS_UART1 14
  11453. +#define RST_BUS_UART0 15
  11454. +#define RST_BUS_TWI0 16
  11455. +#define RST_BUS_PWM 17
  11456. +#define RST_BUS_WEIGAND 18
  11457. +#define RST_BUS_TRNG 19
  11458. +#define RST_BUS_TIMER 20
  11459. +#define RST_BUS_SGDMA 21
  11460. +#define RST_BUS_DMA 22
  11461. +#define RST_BUS_SYSCTRL 23
  11462. +#define RST_BUS_CE 24
  11463. +#define RST_BUS_HSTIMER 25
  11464. +#define RST_BUS_SPLOCK 26
  11465. +#define RST_BUS_DRAM 27
  11466. +#define RST_BUS_RV_MSGBOX 28
  11467. +#define RST_BUS_RV_SYS_APB 29
  11468. +#define RST_BUS_RV 30
  11469. +#define RST_BUS_A27_CFG 31
  11470. +#define RST_BUS_A27_MSGBOX 32
  11471. +#define RST_BUS_A27 33
  11472. +#define RST_BUS_TWI2 34
  11473. +#define RST_BUS_TWI1 35
  11474. +#define RST_BUS_SPI2 36
  11475. +#define RST_BUS_SMHC1 37
  11476. +#define RST_BUS_SMHC0 38
  11477. +#define RST_BUS_SPI1 39
  11478. +#define RST_BUS_DGBSYS 40
  11479. +#define RST_BUS_MBUS 41
  11480. +#define RST_BUS_TCONLCD 42
  11481. +#define RST_BUS_TCON 43
  11482. +#define RST_BUS_I2S1 44
  11483. +#define RST_BUS_I2S0 45
  11484. +#define RST_BUS_DMIC 46
  11485. +#define RST_BUS_AUDIO 47
  11486. +#define RST_BUS_SPIF 48
  11487. +#define RST_BUS_SPI 49
  11488. +#define RST_BUS_VE 50
  11489. +#define RST_BUS_THS 51
  11490. +#define RST_BUS_GPADC 52
  11491. +#define RST_BUS_A27WFG 53
  11492. +#define RST_BUS_GPIOWDG 54
  11493. +#define RST_BUS_RV_WDG 55
  11494. +
  11495. +#endif /* _DT_BINDINGS_RESET_SUN20IW5_APP_H_ */
  11496. diff --git a/include/dt-bindings/reset/sun50iw10-ccu.h b/include/dt-bindings/reset/sun50iw10-ccu.h
  11497. new file mode 100644
  11498. index 000000000000..dd645eaaa154
  11499. --- /dev/null
  11500. +++ b/include/dt-bindings/reset/sun50iw10-ccu.h
  11501. @@ -0,0 +1,79 @@
  11502. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11503. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11504. +/*
  11505. + * Copyright (c) 2020 [email protected]
  11506. + */
  11507. +
  11508. +#ifndef _DT_BINDINGS_RESET_SUN50IW10_H_
  11509. +#define _DT_BINDINGS_RESET_SUN50IW10_H_
  11510. +
  11511. +#define RST_MBUS 0
  11512. +#define RST_BUS_DE0 1
  11513. +#define RST_BUS_DE1 2
  11514. +#define RST_BUS_EINK 3
  11515. +#define RST_BUS_G2D 4
  11516. +#define RST_BUS_GPU 5
  11517. +#define RST_BUS_CE 6
  11518. +#define RST_BUS_VE 7
  11519. +#define RST_BUS_DMA 8
  11520. +#define RST_BUS_MSGBOX 9
  11521. +#define RST_BUS_SPINLOCK 10
  11522. +#define RST_BUS_HSTIMER 11
  11523. +#define RST_BUS_DBG 12
  11524. +#define RST_BUS_PSI 13
  11525. +#define RST_BUS_PWM 14
  11526. +#define RST_BUS_DRAM 15
  11527. +#define RST_BUS_NAND 16
  11528. +#define RST_BUS_MMC0 17
  11529. +#define RST_BUS_MMC1 18
  11530. +#define RST_BUS_MMC2 19
  11531. +#define RST_BUS_MMC3 20
  11532. +#define RST_BUS_UART0 21
  11533. +#define RST_BUS_UART1 22
  11534. +#define RST_BUS_UART2 23
  11535. +#define RST_BUS_UART3 24
  11536. +#define RST_BUS_UART4 25
  11537. +#define RST_BUS_UART5 26
  11538. +#define RST_BUS_UART6 27
  11539. +#define RST_BUS_I2C0 28
  11540. +#define RST_BUS_I2C1 29
  11541. +#define RST_BUS_I2C2 30
  11542. +#define RST_BUS_I2C3 31
  11543. +#define RST_BUS_I2C4 32
  11544. +#define RST_BUS_I2C5 33
  11545. +#define RST_BUS_SPI0 34
  11546. +#define RST_BUS_SPI1 35
  11547. +#define RST_BUS_SPI2 36
  11548. +#define RST_BUS_EMAC0 37
  11549. +#define RST_BUS_EMAC1 38
  11550. +#define RST_BUS_IR_RX 39
  11551. +#define RST_BUS_IR_TX 40
  11552. +#define RST_BUS_GPADC 41
  11553. +#define RST_BUS_THS 42
  11554. +#define RST_BUS_I2S0 43
  11555. +#define RST_BUS_I2S1 44
  11556. +#define RST_BUS_I2S2 45
  11557. +#define RST_BUS_I2S3 46
  11558. +#define RST_BUS_SPDIF 47
  11559. +#define RST_BUS_DMIC 48
  11560. +#define RST_BUS_AUDIO_CODEC 49
  11561. +#define RST_USB_PHY0 50
  11562. +#define RST_USB_PHY1 51
  11563. +#define RST_BUS_OHCI0 52
  11564. +#define RST_BUS_OHCI1 53
  11565. +#define RST_BUS_EHCI0 54
  11566. +#define RST_BUS_EHCI1 55
  11567. +#define RST_BUS_OTG 56
  11568. +#define RST_BUS_LRADC 57
  11569. +#define RST_BUS_DPSS_TOP0 58
  11570. +#define RST_BUS_DPSS_TOP1 59
  11571. +#define RST_BUS_MIPI_DSI 60
  11572. +#define RST_BUS_TCON_LCD0 61
  11573. +#define RST_BUS_TCON_LCD1 62
  11574. +#define RST_BUS_LVDS0 63
  11575. +#define RST_BUS_LVDS1 64
  11576. +#define RST_BUS_LEDC 65
  11577. +#define RST_BUS_CSI 66
  11578. +#define RST_BUS_CSI_ISP 67
  11579. +
  11580. +#endif /* _DT_BINDINGS_RESET_SUN50IW10_H_ */
  11581. diff --git a/include/dt-bindings/reset/sun50iw10-r-ccu.h b/include/dt-bindings/reset/sun50iw10-r-ccu.h
  11582. new file mode 100644
  11583. index 000000000000..fc0817b69ffe
  11584. --- /dev/null
  11585. +++ b/include/dt-bindings/reset/sun50iw10-r-ccu.h
  11586. @@ -0,0 +1,19 @@
  11587. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  11588. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11589. +/*
  11590. + * Copyright (C) 2020 [email protected]
  11591. + */
  11592. +
  11593. +#ifndef _DT_BINDINGS_RST_SUN50IW10_R_CCU_H_
  11594. +#define _DT_BINDINGS_RST_SUN50IW10_R_CCU_H_
  11595. +
  11596. +#define RST_R_APB1_TIMER 0
  11597. +#define RST_R_APB1_BUS_PWM 1
  11598. +#define RST_R_APB1_PPU 2
  11599. +#define RST_R_APB2_UART 3
  11600. +#define RST_R_APB2_I2C0 4
  11601. +#define RST_R_APB2_I2C1 5
  11602. +#define RST_R_APB1_BUS_IR 6
  11603. +#define RST_R_AHB_BUS_RTC 7
  11604. +
  11605. +#endif /* _DT_BINDINGS_RST_SUN50IW10_R_CCU_H_ */
  11606. diff --git a/include/dt-bindings/reset/sun50iw12-ccu.h b/include/dt-bindings/reset/sun50iw12-ccu.h
  11607. new file mode 100644
  11608. index 000000000000..d13cf3b7d3e5
  11609. --- /dev/null
  11610. +++ b/include/dt-bindings/reset/sun50iw12-ccu.h
  11611. @@ -0,0 +1,69 @@
  11612. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11613. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11614. +/*
  11615. + * Copyright (C) 2020 [email protected]
  11616. + */
  11617. +
  11618. +#ifndef _DT_BINDINGS_RESET_SUN50IW12_H_
  11619. +#define _DT_BINDINGS_RESET_SUN50IW12_H_
  11620. +
  11621. +#define RST_MBUS 0
  11622. +#define RST_BUS_MIPS 1
  11623. +#define RST_BUS_MIPS_COLD 2
  11624. +#define RST_BUS_MIPS_SOFT 3
  11625. +#define RST_BUS_GPU 4
  11626. +#define RST_BUS_CE 5
  11627. +#define RST_BUS_CE_SYS 6
  11628. +#define RST_BUS_VE 7
  11629. +#define RST_BUS_AV1 8
  11630. +#define RST_BUS_VE3 9
  11631. +#define RST_BUS_DMA 10
  11632. +#define RST_BUS_MSGBOX 11
  11633. +#define RST_BUS_SPINLOCK 12
  11634. +#define RST_BUS_TIMER0 13
  11635. +#define RST_BUS_DBGSYS 14
  11636. +#define RST_BUS_PWM 15
  11637. +#define RST_BUS_DRAM_MODULE 16
  11638. +#define RST_BUS_DRAM 17
  11639. +#define RST_BUS_NAND 18
  11640. +#define RST_BUS_MMC0 19
  11641. +#define RST_BUS_MMC1 20
  11642. +#define RST_BUS_MMC2 21
  11643. +#define RST_BUS_UART0 22
  11644. +#define RST_BUS_UART1 23
  11645. +#define RST_BUS_UART2 24
  11646. +#define RST_BUS_UART3 25
  11647. +#define RST_BUS_UART4 26
  11648. +#define RST_BUS_I2C0 27
  11649. +#define RST_BUS_I2C1 28
  11650. +#define RST_BUS_I2C2 29
  11651. +#define RST_BUS_I2C3 30
  11652. +#define RST_BUS_SPI0 31
  11653. +#define RST_BUS_SPI1 32
  11654. +#define RST_BUS_EMAC 33
  11655. +#define RST_BUS_GPADC 34
  11656. +#define RST_BUS_THS 35
  11657. +#define RST_BUS_I2S0 36
  11658. +#define RST_BUS_I2S1 37
  11659. +#define RST_BUS_I2S2 38
  11660. +#define RST_BUS_SPDIF0 39
  11661. +#define RST_BUS_SPDIF1 40
  11662. +#define RST_BUS_AUDIO_HUB 41
  11663. +#define RST_BUS_AUDIO_CODEC 42
  11664. +#define RST_USB_PHY0 43
  11665. +#define RST_USB_PHY1 44
  11666. +#define RST_USB_PHY2 45
  11667. +#define RST_BUS_OHCI0 46
  11668. +#define RST_BUS_OHCI1 47
  11669. +#define RST_BUS_OHCI2 48
  11670. +#define RST_BUS_EHCI0 49
  11671. +#define RST_BUS_EHCI1 50
  11672. +#define RST_BUS_EHCI2 51
  11673. +#define RST_BUS_OTG 52
  11674. +#define RST_BUS_LRADC 53
  11675. +#define RST_BUS_LVDS 54
  11676. +#define RST_BUS_DEMOD 55
  11677. +#define RST_BUS_TVCAP 56
  11678. +#define RST_BUS_DISP 57
  11679. +
  11680. +#endif /* _DT_BINDINGS_RESET_SUN50IW12_H_ */
  11681. diff --git a/include/dt-bindings/reset/sun50iw12-r-ccu.h b/include/dt-bindings/reset/sun50iw12-r-ccu.h
  11682. new file mode 100644
  11683. index 000000000000..13054faec288
  11684. --- /dev/null
  11685. +++ b/include/dt-bindings/reset/sun50iw12-r-ccu.h
  11686. @@ -0,0 +1,23 @@
  11687. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  11688. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11689. +/*
  11690. + * Copyright (C) 2020 [email protected]
  11691. + */
  11692. +
  11693. +#ifndef _DT_BINDINGS_RST_SUN50IW12_R_CCU_H_
  11694. +#define _DT_BINDINGS_RST_SUN50IW12_R_CCU_H_
  11695. +
  11696. +#define RST_R_APB0_BUS_TIMER0 0
  11697. +#define RST_R_APB0_BUS_EDID 1
  11698. +#define RST_R_APB0_BUS_PWM 2
  11699. +#define RST_R_APB1_BUS_UART0 3
  11700. +#define RST_R_APB1_BUS_I2C0 4
  11701. +#define RST_R_APB1_BUS_I2C1 5
  11702. +#define RST_R_APB1_BUS_PPU 6
  11703. +#define RST_R_APB0_BUS_IR_RX 7
  11704. +#define RST_R_AHB_BUS_RTC 8
  11705. +#define RST_R_AHB_BUS_CPUCFG 9
  11706. +#define RST_R_MODULE 10
  11707. +
  11708. +
  11709. +#endif /* _DT_BINDINGS_RST_SUN50IW12_R_CCU_H_ */
  11710. diff --git a/include/dt-bindings/reset/sun50iw9-ccu.h b/include/dt-bindings/reset/sun50iw9-ccu.h
  11711. new file mode 100644
  11712. index 000000000000..6386672b16c2
  11713. --- /dev/null
  11714. +++ b/include/dt-bindings/reset/sun50iw9-ccu.h
  11715. @@ -0,0 +1,77 @@
  11716. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11717. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11718. +/*
  11719. + * Copyright (c) 2020 [email protected]
  11720. + */
  11721. +
  11722. +#ifndef _DT_BINDINGS_RESET_SUN50IW9_H_
  11723. +#define _DT_BINDINGS_RESET_SUN50IW9_H_
  11724. +
  11725. +#define RST_MBUS 0
  11726. +#define RST_BUS_DE 1
  11727. +#define RST_BUS_DI 2
  11728. +#define RST_BUS_G2D 3
  11729. +#define RST_BUS_GPU 4
  11730. +#define RST_BUS_CE 5
  11731. +#define RST_BUS_VE 6
  11732. +#define RST_BUS_DMA 7
  11733. +#define RST_BUS_HSTIMER 8
  11734. +#define RST_BUS_DBG 9
  11735. +#define RST_BUS_PSI 10
  11736. +#define RST_BUS_PWM 11
  11737. +#define RST_BUS_DRAM 12
  11738. +#define RST_BUS_NAND 13
  11739. +#define RST_BUS_MMC0 14
  11740. +#define RST_BUS_MMC1 15
  11741. +#define RST_BUS_MMC2 16
  11742. +#define RST_BUS_UART0 17
  11743. +#define RST_BUS_UART1 18
  11744. +#define RST_BUS_UART2 19
  11745. +#define RST_BUS_UART3 20
  11746. +#define RST_BUS_UART4 21
  11747. +#define RST_BUS_UART5 22
  11748. +#define RST_BUS_I2C0 23
  11749. +#define RST_BUS_I2C1 24
  11750. +#define RST_BUS_I2C2 25
  11751. +#define RST_BUS_I2C3 26
  11752. +#define RST_BUS_I2C4 27
  11753. +#define RST_BUS_SCR 28
  11754. +#define RST_BUS_SPI0 29
  11755. +#define RST_BUS_SPI1 30
  11756. +#define RST_BUS_EMAC0 31
  11757. +#define RST_BUS_EMAC1 32
  11758. +#define RST_BUS_TS 33
  11759. +#define RST_BUS_GPADC 34
  11760. +#define RST_BUS_THS 35
  11761. +#define RST_BUS_SPDIF 36
  11762. +#define RST_BUS_DMIC 37
  11763. +#define RST_BUS_AUDIO_CODEC 38
  11764. +#define RST_BUS_AUDIO_HUB 39
  11765. +#define RST_USB_PHY0 40
  11766. +#define RST_USB_PHY1 41
  11767. +#define RST_USB_PHY2 42
  11768. +#define RST_USB_PHY3 43
  11769. +#define RST_BUS_OHCI0 44
  11770. +#define RST_BUS_OHCI1 45
  11771. +#define RST_BUS_OHCI2 46
  11772. +#define RST_BUS_OHCI3 47
  11773. +#define RST_BUS_EHCI0 48
  11774. +#define RST_BUS_EHCI1 49
  11775. +#define RST_BUS_EHCI2 50
  11776. +#define RST_BUS_EHCI3 51
  11777. +#define RST_BUS_OTG 52
  11778. +#define RST_BUS_LRADC 53
  11779. +#define RST_BUS_HDMI_MAIN 54
  11780. +#define RST_BUS_HDMI_SUB 55
  11781. +#define RST_BUS_DISPLAY_IF_TOP 56
  11782. +#define RST_BUS_TCON_LCD0 57
  11783. +#define RST_BUS_TCON_LCD1 58
  11784. +#define RST_BUS_TCON_TV0 59
  11785. +#define RST_BUS_TCON_TV1 60
  11786. +#define RST_BUS_LVDS 61
  11787. +#define RST_BUS_TVE_TOP 62
  11788. +#define RST_BUS_TVE 63
  11789. +#define RST_BUS_CSI 64
  11790. +#define RST_BUS_HDMI_HDCP 65
  11791. +
  11792. +#endif /* _DT_BINDINGS_RESET_SUN50IW9_H_ */
  11793. diff --git a/include/dt-bindings/reset/sun50iw9-r-ccu.h b/include/dt-bindings/reset/sun50iw9-r-ccu.h
  11794. new file mode 100644
  11795. index 000000000000..5b8750402f98
  11796. --- /dev/null
  11797. +++ b/include/dt-bindings/reset/sun50iw9-r-ccu.h
  11798. @@ -0,0 +1,14 @@
  11799. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  11800. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11801. +/*
  11802. + * Copyright (C) 2020 [email protected]
  11803. + */
  11804. +
  11805. +#ifndef _DT_BINDINGS_RST_SUN50IW9_R_CCU_H_
  11806. +#define _DT_BINDINGS_RST_SUN50IW9_R_CCU_H_
  11807. +
  11808. +#define RST_R_APB1_TWD 0
  11809. +#define RST_R_APB2_I2C 1
  11810. +#define RST_R_APB1_BUS_IR 2
  11811. +
  11812. +#endif /* _DT_BINDINGS_RST_SUN50IW9_R_CCU_H_ */
  11813. diff --git a/include/dt-bindings/reset/sun55iw3-ccu.h b/include/dt-bindings/reset/sun55iw3-ccu.h
  11814. new file mode 100644
  11815. index 000000000000..c22018b67b7c
  11816. --- /dev/null
  11817. +++ b/include/dt-bindings/reset/sun55iw3-ccu.h
  11818. @@ -0,0 +1,88 @@
  11819. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11820. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11821. +/*
  11822. + * Copyright (c) 2021 [email protected]
  11823. + */
  11824. +
  11825. +#ifndef _DT_BINDINGS_RESET_SUN55IW3_H_
  11826. +#define _DT_BINDINGS_RESET_SUN55IW3_H_
  11827. +
  11828. +#define RST_MBUS 0
  11829. +#define RST_BUS_NSI 1
  11830. +#define RST_BUS_DE0 2
  11831. +#define RST_BUS_DI 3
  11832. +#define RST_BUS_G2D 4
  11833. +#define RST_BUS_GPU 5
  11834. +#define RST_BUS_CE_SY 6
  11835. +#define RST_BUS_CE 7
  11836. +#define RST_BUS_VE 8
  11837. +#define RST_BUS_DMA 9
  11838. +#define RST_BUS_MSGBOX1 10
  11839. +#define RST_BUS_MSGBOX0 11
  11840. +#define RST_BUS_SPINLOCK 12
  11841. +#define RST_BUS_TIME 13
  11842. +#define RST_BUS_DBGSY 14
  11843. +#define RST_BUS_PWM1 15
  11844. +#define RST_BUS_PWM 16
  11845. +#define RST_BUS_DRAM 17
  11846. +#define RST_BUS_NAND0 18
  11847. +#define RST_BUS_SMHC2 19
  11848. +#define RST_BUS_SMHC1 20
  11849. +#define RST_BUS_SMHC0 21
  11850. +#define RST_BUS_SYSDAP 22
  11851. +#define RST_BUS_UART7 23
  11852. +#define RST_BUS_UART6 24
  11853. +#define RST_BUS_UART5 25
  11854. +#define RST_BUS_UART4 26
  11855. +#define RST_BUS_UART3 27
  11856. +#define RST_BUS_UART2 28
  11857. +#define RST_BUS_UART1 29
  11858. +#define RST_BUS_UART0 30
  11859. +#define RST_BUS_TWI5 31
  11860. +#define RST_BUS_TWI4 32
  11861. +#define RST_BUS_TWI3 33
  11862. +#define RST_BUS_TWI2 34
  11863. +#define RST_BUS_TWI1 35
  11864. +#define RST_BUS_TWI0 36
  11865. +#define RST_BUS_SPIF 37
  11866. +#define RST_BUS_SPI2 38
  11867. +#define RST_BUS_SPI1 39
  11868. +#define RST_BUS_SPI0 40
  11869. +#define RST_BUS_GMAC1 41
  11870. +#define RST_BUS_GMAC0 42
  11871. +#define RST_BUS_IRRX 43
  11872. +#define RST_BUS_IRTX 44
  11873. +#define RST_BUS_GPADC1 45
  11874. +#define RST_BUS_GPADC0 46
  11875. +#define RST_BUS_TH 47
  11876. +#define RST_USB_PHY0_RSTN 48
  11877. +#define RST_USB_PHY1_RSTN 49
  11878. +#define RST_USB_3 50
  11879. +#define RST_USB_OTG0 51
  11880. +#define RST_USB_EHCI1 52
  11881. +#define RST_USB_EHCI0 53
  11882. +#define RST_USB_OHCI1 54
  11883. +#define RST_USB_OHCI0 55
  11884. +#define RST_BUS_LRADC 56
  11885. +#define RST_BUS_PCIE_PE 57
  11886. +#define RST_BUS_PCIE_POWER_UP 58
  11887. +#define RST_BUS_PCIE_USB3 59
  11888. +#define RST_BUS_DPSS_TOP0 60
  11889. +#define RST_BUS_DPSS_TOP1 61
  11890. +#define RST_BUS_HDMI_SUB 62
  11891. +#define RST_BUS_HDMI_MAIN 63
  11892. +#define RST_BUS_DSI1 64
  11893. +#define RST_BUS_DSI0 65
  11894. +#define RST_BUS_VO1_TCONLCD0 66
  11895. +#define RST_BUS_VO0_TCONLCD1 67
  11896. +#define RST_BUS_VO0_TCONLCD0 68
  11897. +#define RST_BUS_TCONTV1 69
  11898. +#define RST_BUS_TCONTV 70
  11899. +#define RST_BUS_LVDS1 71
  11900. +#define RST_BUS_LVDS0 72
  11901. +#define RST_BUS_EDP 73
  11902. +#define RST_BUS_LEDC 74
  11903. +#define RST_BUS_CSI 75
  11904. +#define RST_BUS_ISP 76
  11905. +
  11906. +#endif /* _DT_BINDINGS_RESET_SUN55IW3_H_ */
  11907. diff --git a/include/dt-bindings/reset/sun55iw3-mcu-ccu.h b/include/dt-bindings/reset/sun55iw3-mcu-ccu.h
  11908. new file mode 100644
  11909. index 000000000000..c849a3657b0e
  11910. --- /dev/null
  11911. +++ b/include/dt-bindings/reset/sun55iw3-mcu-ccu.h
  11912. @@ -0,0 +1,31 @@
  11913. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  11914. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11915. +/*
  11916. + * Copyright (C) 2022 [email protected]
  11917. + */
  11918. +
  11919. +#ifndef _DT_BINDINGS_RST_SUN55IW3_MCU_CCU_H_
  11920. +#define _DT_BINDINGS_RST_SUN55IW3_MCU_CCU_H_
  11921. +
  11922. +#define RST_BUS_MCU_I2S3 0
  11923. +#define RST_BUS_MCU_I2S2 1
  11924. +#define RST_BUS_MCU_I2S1 2
  11925. +#define RST_BUS_MCU_I2S0 3
  11926. +#define RST_BUS_MCU_OWA 4
  11927. +#define RST_BUS_MCU_DMIC 5
  11928. +#define RST_BUS_MCU_AUDIO_CODEC 6
  11929. +#define RST_BUS_DSP_MSG 7
  11930. +#define RST_BUS_DSP_CFG 8
  11931. +#define RST_BUS_MCU_NPU 9
  11932. +#define RST_BUS_MCU_TIME 10
  11933. +#define RST_BUS_DSP 11
  11934. +#define RST_BUS_DSP_DBG 12
  11935. +#define RST_BUS_MCU_DMA 13
  11936. +#define RST_BUS_PUBSRAM 14
  11937. +#define RST_BUS_RV 15
  11938. +#define RST_BUS_RV_DBG 16
  11939. +#define RST_BUS_RV_CFG 17
  11940. +#define RST_BUS_MCU_RV_MSG 18
  11941. +#define RST_BUS_MCU_PWM 19
  11942. +
  11943. +#endif /* _DT_BINDINGS_RST_SUN55IW3_MCU_CCU_H_ */
  11944. diff --git a/include/dt-bindings/reset/sun55iw3-r-ccu.h b/include/dt-bindings/reset/sun55iw3-r-ccu.h
  11945. new file mode 100644
  11946. index 000000000000..bdaab6470d62
  11947. --- /dev/null
  11948. +++ b/include/dt-bindings/reset/sun55iw3-r-ccu.h
  11949. @@ -0,0 +1,27 @@
  11950. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  11951. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11952. +/*
  11953. + * Copyright (C) 2021 [email protected]
  11954. + */
  11955. +
  11956. +#ifndef _DT_BINDINGS_RST_SUN55IW3_R_CCU_H_
  11957. +#define _DT_BINDINGS_RST_SUN55IW3_R_CCU_H_
  11958. +
  11959. +#define RST_R_TIMER 0
  11960. +#define RST_R_PWM 1
  11961. +#define RST_R_CAN 2
  11962. +#define RST_R_SPI 3
  11963. +#define RST_R_SPLOCK 4
  11964. +#define RST_R_MBOX 5
  11965. +#define RST_R_UART1 6
  11966. +#define RST_R_UART0 7
  11967. +#define RST_R_TWI2 8
  11968. +#define RST_R_TWI1 9
  11969. +#define RST_R_TWI0 10
  11970. +#define RST_R_PPU1 11
  11971. +#define RST_R_PPU 12
  11972. +#define RST_R_IRRX 13
  11973. +#define RST_R_RTC 14
  11974. +#define RST_R_CPUCFG 15
  11975. +
  11976. +#endif /* _DT_BINDINGS_RST_SUN55IW3_R_CCU_H_ */
  11977. diff --git a/include/dt-bindings/reset/sun55iw5-ccu.h b/include/dt-bindings/reset/sun55iw5-ccu.h
  11978. new file mode 100644
  11979. index 000000000000..6e8f30a90a5c
  11980. --- /dev/null
  11981. +++ b/include/dt-bindings/reset/sun55iw5-ccu.h
  11982. @@ -0,0 +1,60 @@
  11983. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  11984. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  11985. +/*
  11986. + * Copyright (c) 2021 [email protected]
  11987. + */
  11988. +
  11989. +#ifndef _DT_BINDINGS_RESET_SUN55IW3_H_
  11990. +#define _DT_BINDINGS_RESET_SUN55IW3_H_
  11991. +
  11992. +#define RST_MBUS 0
  11993. +#define RST_BUS_GPU 1
  11994. +#define RST_BUS_CE_SY 2
  11995. +#define RST_BUS_CE 3
  11996. +#define RST_BUS_AV1 4
  11997. +#define RST_BUS_VE 5
  11998. +#define RST_BUS_DMA 6
  11999. +#define RST_BUS_MSGBOX 7
  12000. +#define RST_BUS_SPINLOCK 8
  12001. +#define RST_BUS_TIMER0 9
  12002. +#define RST_BUS_DBGSY 10
  12003. +#define RST_BUS_PWM 11
  12004. +#define RST_BUS_DRAM_MODULE 12
  12005. +#define RST_BUS_DRAM 13
  12006. +#define RST_BUS_SMHC2 14
  12007. +#define RST_BUS_SMHC1 15
  12008. +#define RST_BUS_SMHC0 16
  12009. +#define RST_BUS_UART3 17
  12010. +#define RST_BUS_UART2 18
  12011. +#define RST_BUS_UART1 19
  12012. +#define RST_BUS_UART0 20
  12013. +#define RST_BUS_TWI4 21
  12014. +#define RST_BUS_TWI3 22
  12015. +#define RST_BUS_TWI2 23
  12016. +#define RST_BUS_TWI1 24
  12017. +#define RST_BUS_TWI0 25
  12018. +#define RST_BUS_SPI2 26
  12019. +#define RST_BUS_SPI1 27
  12020. +#define RST_BUS_SPI0 28
  12021. +#define RST_BUS_GMAC0 29
  12022. +#define RST_BUS_I2SPCM0 30
  12023. +#define RST_BUS_SPDIF1 31
  12024. +#define RST_BUS_SPDIF0 32
  12025. +#define RST_BUS_AUDIO_CODEC 33
  12026. +#define RST_USB_PHY0_RSTN 34
  12027. +#define RST_USB_PHY1_RSTN 35
  12028. +#define RST_USB_PHY2_RSTN 36
  12029. +#define RST_USB_OTG 37
  12030. +#define RST_USB_EHCI2 38
  12031. +#define RST_USB_EHCI1 39
  12032. +#define RST_USB_EHCI0 40
  12033. +#define RST_USB_OHCI2 41
  12034. +#define RST_USB_OHCI1 42
  12035. +#define RST_USB_OHCI0 43
  12036. +#define RST_BUS_LVD 44
  12037. +#define RST_BUS_TVFE_AXI 45
  12038. +#define RST_BUS_DEMOD 46
  12039. +#define RST_BUS_TVCAP 47
  12040. +#define RST_BUS_DISP 48
  12041. +
  12042. +#endif /* _DT_BINDINGS_RESET_SUN55IW3_H_ */
  12043. diff --git a/include/dt-bindings/reset/sun55iw5-r-ccu.h b/include/dt-bindings/reset/sun55iw5-r-ccu.h
  12044. new file mode 100644
  12045. index 000000000000..81d0d328e9c5
  12046. --- /dev/null
  12047. +++ b/include/dt-bindings/reset/sun55iw5-r-ccu.h
  12048. @@ -0,0 +1,24 @@
  12049. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12050. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12051. +/*
  12052. + * Copyright (C) 2023 [email protected]
  12053. + */
  12054. +
  12055. +#ifndef _DT_BINDINGS_RST_SUN55IW5_R_CCU_H_
  12056. +#define _DT_BINDINGS_RST_SUN55IW5_R_CCU_H_
  12057. +
  12058. +#define RST_BUS_R_TIMER 0
  12059. +#define RST_BUS_EDID 1
  12060. +#define RST_BUS_R_PWM 2
  12061. +#define RST_BUS_R_UART0 3
  12062. +#define RST_BUS_R_TWI1 4
  12063. +#define RST_BUS_R_TWI0 5
  12064. +#define RST_BUS_R_PPU 6
  12065. +#define RST_BUS_R_IRRX 7
  12066. +#define RST_BUS_R_GPADC 8
  12067. +#define RST_BUS_R_TH 9
  12068. +#define RST_BUS_R_RTC 10
  12069. +#define RST_BUS_R_CPUCFG 11
  12070. +#define RST_BUS_MODULE 12
  12071. +
  12072. +#endif /* _DT_BINDINGS_RST_SUN55IW5_R_CCU_H_ */
  12073. diff --git a/include/dt-bindings/reset/sun55iw6-ccu.h b/include/dt-bindings/reset/sun55iw6-ccu.h
  12074. new file mode 100644
  12075. index 000000000000..3fd64cc252cd
  12076. --- /dev/null
  12077. +++ b/include/dt-bindings/reset/sun55iw6-ccu.h
  12078. @@ -0,0 +1,120 @@
  12079. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12080. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12081. +/*
  12082. + * Copyright (c) 2023 [email protected]
  12083. + */
  12084. +
  12085. +#ifndef _DT_BINDINGS_RESET_SUN55IW6_H_
  12086. +#define _DT_BINDINGS_RESET_SUN55IW6_H_
  12087. +
  12088. +#define RST_BUS_ITS0 0
  12089. +#define RST_BUS_NSI 1
  12090. +#define RST_BUS_NSI_CFG 2
  12091. +#define RST_BUS_DMA0 3
  12092. +#define RST_BUS_DMA1 4
  12093. +#define RST_BUS_SPINLOCK 5
  12094. +#define RST_BUS_MSGBOX0 6
  12095. +#define RST_BUS_MSGBOX_CORE0 7
  12096. +#define RST_BUS_MSGBOX_CORE1 8
  12097. +#define RST_BUS_MSGBOX_CORE2 9
  12098. +#define RST_BUS_MSGBOX_CORE3 10
  12099. +#define RST_BUS_MSGBOX_RV 11
  12100. +#define RST_BUS_PWM0 12
  12101. +#define RST_BUS_PWM1 13
  12102. +#define RST_BUS_PWM2 14
  12103. +#define RST_BUS_DBGSY 15
  12104. +#define RST_BUS_SYSDAP 16
  12105. +#define RST_BUS_TIME 17
  12106. +#define RST_BUS_TIMER_RV 18
  12107. +#define RST_BUS_DE0 19
  12108. +#define RST_BUS_G2D 20
  12109. +#define RST_BUS_DE_SY 21
  12110. +#define RST_BUS_VE 22
  12111. +#define RST_BUS_CE_SY 23
  12112. +#define RST_BUS_CE 24
  12113. +#define RST_BUS_NPU_GLB 25
  12114. +#define RST_BUS_NPU_AHB 26
  12115. +#define RST_BUS_NPU_AXI 27
  12116. +#define RST_BUS_NPU_CORE 28
  12117. +#define RST_BUS_RV_SY 29
  12118. +#define RST_BUS_RV_CORE 30
  12119. +#define RST_BUS_RV_CFG 31
  12120. +#define RST_BUS_DRAM 32
  12121. +#define RST_BUS_NAND0 33
  12122. +#define RST_BUS_SMHC0 34
  12123. +#define RST_BUS_SMHC1 35
  12124. +#define RST_BUS_SMHC2 36
  12125. +#define RST_BUS_UART0 37
  12126. +#define RST_BUS_UART1 38
  12127. +#define RST_BUS_UART2 39
  12128. +#define RST_BUS_UART3 40
  12129. +#define RST_BUS_UART4 41
  12130. +#define RST_BUS_UART5 42
  12131. +#define RST_BUS_UART6 43
  12132. +#define RST_BUS_UART7 44
  12133. +#define RST_BUS_UART8 45
  12134. +#define RST_BUS_UART9 46
  12135. +#define RST_BUS_UART10 47
  12136. +#define RST_BUS_UART11 48
  12137. +#define RST_BUS_UART12 49
  12138. +#define RST_BUS_UART13 50
  12139. +#define RST_BUS_UART14 51
  12140. +#define RST_BUS_TWI0 52
  12141. +#define RST_BUS_TWI1 53
  12142. +#define RST_BUS_TWI2 54
  12143. +#define RST_BUS_TWI3 55
  12144. +#define RST_BUS_TWI4 56
  12145. +#define RST_BUS_TWI5 57
  12146. +#define RST_BUS_TWI6 58
  12147. +#define RST_BUS_SPI0 59
  12148. +#define RST_BUS_SPI1 60
  12149. +#define RST_BUS_SPI2 61
  12150. +#define RST_BUS_SPIF 62
  12151. +#define RST_BUS_SPI3 63
  12152. +#define RST_BUS_SPI4 64
  12153. +#define RST_BUS_GPADC0 70
  12154. +#define RST_BUS_GPADC1 71
  12155. +#define RST_BUS_GPADC2 72
  12156. +#define RST_BUS_GPADC3 73
  12157. +#define RST_BUS_TH 74
  12158. +#define RST_BUS_IRRX0 75
  12159. +#define RST_BUS_IRTX 76
  12160. +#define RST_BUS_LRADC 77
  12161. +#define RST_BUS_TPADC 78
  12162. +#define RST_BUS_LBC 79
  12163. +#define RST_BUS_IRRX1 80
  12164. +#define RST_BUS_IRRX2 81
  12165. +#define RST_BUS_IRRX3 82
  12166. +#define RST_BUS_I2SPCM0 83
  12167. +#define RST_BUS_I2SPCM1 84
  12168. +#define RST_BUS_I2SPCM2 85
  12169. +#define RST_BUS_I2SPCM3 86
  12170. +#define RST_BUS_OWA 87
  12171. +#define RST_BUS_DMIC 88
  12172. +#define RST_BUS_AUDIO_CODEC 89
  12173. +#define RST_USB_PHY0_RSTN 90
  12174. +#define RST_USB_20_0_DEVICE 91
  12175. +#define RST_USB_20_0_HOST_EHCI 92
  12176. +#define RST_USB_20_0_HOST_OHCI 93
  12177. +#define RST_USB_PHY1_RSTN 94
  12178. +#define RST_USB_20_1_HOST_EHCI 95
  12179. +#define RST_USB_20_1_HOST_OHCI 96
  12180. +#define RST_USB_30 97
  12181. +#define RST_BUS_PCIE 98
  12182. +#define RST_BUS_PCIE_PWRUP 99
  12183. +#define RST_BUS_SERDES_NOPPU 100
  12184. +#define RST_BUS_SERDE 101
  12185. +#define RST_BUS_GMAC0_AXI 102
  12186. +#define RST_BUS_GMAC0 103
  12187. +#define RST_BUS_GMAC1_AXI 104
  12188. +#define RST_BUS_GMAC1 105
  12189. +#define RST_BUS_VO0_TCONLCD0 106
  12190. +#define RST_BUS_LVDS0 107
  12191. +#define RST_BUS_DSI0 108
  12192. +#define RST_BUS_DP 109
  12193. +#define RST_BUS_VIDEO_OUT0 110
  12194. +#define RST_BUS_LEDC 111
  12195. +#define RST_BUS_CSI 112
  12196. +#define RST_BUS_ISP 113
  12197. +
  12198. +#endif /* _DT_BINDINGS_RESET_SUN55IW6_H_ */
  12199. diff --git a/include/dt-bindings/reset/sun55iw6-r-ccu.h b/include/dt-bindings/reset/sun55iw6-r-ccu.h
  12200. new file mode 100644
  12201. index 000000000000..c0587fe47383
  12202. --- /dev/null
  12203. +++ b/include/dt-bindings/reset/sun55iw6-r-ccu.h
  12204. @@ -0,0 +1,23 @@
  12205. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12206. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12207. +/*
  12208. + * Copyright (C) 2023 [email protected]
  12209. + */
  12210. +
  12211. +#ifndef _DT_BINDINGS_RST_SUN55IW6_R_CCU_H_
  12212. +#define _DT_BINDINGS_RST_SUN55IW6_R_CCU_H_
  12213. +
  12214. +#define RST_BUS_R_TIME 0
  12215. +#define RST_BUS_R_PWM 1
  12216. +#define RST_BUS_R_SPI 2
  12217. +#define RST_BUS_R_MBOX 3
  12218. +#define RST_BUS_R_UART1 4
  12219. +#define RST_BUS_R_UART0 5
  12220. +#define RST_BUS_R_TWI1 6
  12221. +#define RST_BUS_R_TWI0 7
  12222. +#define RST_BUS_R_IRRX 8
  12223. +#define RST_BUS_RTC 9
  12224. +#define RST_BUS_R_CPUCFG 10
  12225. +#define RST_BUS_MODULE 11
  12226. +
  12227. +#endif /* _DT_BINDINGS_RST_SUN55IW6_R_CCU_H_ */
  12228. diff --git a/include/dt-bindings/reset/sun60iw1-ccu.h b/include/dt-bindings/reset/sun60iw1-ccu.h
  12229. new file mode 100644
  12230. index 000000000000..7e792f1d50ef
  12231. --- /dev/null
  12232. +++ b/include/dt-bindings/reset/sun60iw1-ccu.h
  12233. @@ -0,0 +1,155 @@
  12234. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12235. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12236. +/*
  12237. + * Copyright (C) 2022 [email protected]
  12238. + */
  12239. +
  12240. +#ifndef _DT_BINDINGS_RESET_SUN60IW1_H_
  12241. +#define _DT_BINDINGS_RESET_SUN60IW1_H_
  12242. +
  12243. +#define RST_BUS_NSI 0
  12244. +#define RST_BUS_NSI_CFG 1
  12245. +#define RST_MBUS 2
  12246. +#define RST_BUS_SMMU_TCU 3
  12247. +#define RST_BUS_SMMU_GPU1 4
  12248. +#define RST_BUS_SMMU_AIPU 5
  12249. +#define RST_BUS_SMMU_NPU 6
  12250. +#define RST_BUS_SMMU_GPU0 7
  12251. +#define RST_BUS_SMMU_PCIE1 8
  12252. +#define RST_BUS_SMMU_PCIE0 9
  12253. +#define RST_BUS_SMMU_MSI_LITE1 10
  12254. +#define RST_BUS_SMMU_MSI_LITE0 11
  12255. +#define RST_BUS_SMMU_USB3 12
  12256. +#define RST_BUS_SMMU_GMAC1 13
  12257. +#define RST_BUS_SMMU_GMAC0 14
  12258. +#define RST_BUS_SMMU_DE1 15
  12259. +#define RST_BUS_SMMU_DE0 16
  12260. +#define RST_BUS_SMMU_VE_DEC1 17
  12261. +#define RST_BUS_SMMU_VE_DEC0 18
  12262. +#define RST_BUS_SMMU_VE_ENC1 19
  12263. +#define RST_BUS_SMMU_VE_ENC0 20
  12264. +#define RST_BUS_SMMU_G2D 21
  12265. +#define RST_BUS_SMMU_DI 22
  12266. +#define RST_BUS_SMMU_CSI_DMA1 23
  12267. +#define RST_BUS_SMMU_CSI_DMA0 24
  12268. +#define RST_BUS_SMMU_ISP 25
  12269. +#define RST_BUS_SMMU_SY 26
  12270. +#define RST_BUS_MSI_LITE0 27
  12271. +#define RST_BUS_MSI_LITE1 28
  12272. +#define RST_BUS_DMA0 29
  12273. +#define RST_BUS_DMA1 30
  12274. +#define RST_BUS_SPINLOCK 31
  12275. +#define RST_BUS_MSGBOX0 32
  12276. +#define RST_BUS_MSGBOX1 33
  12277. +#define RST_BUS_MSGBOX2 34
  12278. +#define RST_BUS_PWM0 35
  12279. +#define RST_BUS_PWM1 36
  12280. +#define RST_BUS_DBGSY 37
  12281. +#define RST_BUS_SYSDAP 38
  12282. +#define RST_BUS_TIMER0 39
  12283. +#define RST_BUS_TIMER1 40
  12284. +#define RST_BUS_DE0 41
  12285. +#define RST_BUS_DE1 42
  12286. +#define RST_BUS_DI 43
  12287. +#define RST_BUS_G2D 44
  12288. +#define RST_BUS_DE_SY 45
  12289. +#define RST_BUS_VE_DEC 46
  12290. +#define RST_BUS_VE_ENC1 47
  12291. +#define RST_BUS_VE_ENC0 48
  12292. +#define RST_BUS_CE_SY 49
  12293. +#define RST_BUS_CE 50
  12294. +#define RST_BUS_NPU_SY 51
  12295. +#define RST_BUS_NPU_AHB 52
  12296. +#define RST_BUS_NPU_AXI 53
  12297. +#define RST_BUS_NPU_CORE 54
  12298. +#define RST_BUS_AIPU_CORE 55
  12299. +#define RST_BUS_AIPU 56
  12300. +#define RST_BUS_GPU0 57
  12301. +#define RST_BUS_DRAM0 58
  12302. +#define RST_BUS_NAND0 59
  12303. +#define RST_BUS_SMHC0 60
  12304. +#define RST_BUS_SMHC1 61
  12305. +#define RST_BUS_SMHC2 62
  12306. +#define RST_BUS_SMHC3 63
  12307. +#define RST_BUS_UFS_AXI 64
  12308. +#define RST_BUS_UF 65
  12309. +#define RST_BUS_UART0 66
  12310. +#define RST_BUS_UART1 67
  12311. +#define RST_BUS_UART2 68
  12312. +#define RST_BUS_UART3 69
  12313. +#define RST_BUS_UART4 70
  12314. +#define RST_BUS_UART5 71
  12315. +#define RST_BUS_UART6 72
  12316. +#define RST_BUS_UART7 73
  12317. +#define RST_BUS_UART8 74
  12318. +#define RST_BUS_TWI0 75
  12319. +#define RST_BUS_TWI1 76
  12320. +#define RST_BUS_TWI2 77
  12321. +#define RST_BUS_TWI3 78
  12322. +#define RST_BUS_TWI4 79
  12323. +#define RST_BUS_TWI5 80
  12324. +#define RST_BUS_TWI6 81
  12325. +#define RST_BUS_TWI7 82
  12326. +#define RST_BUS_TWI8 83
  12327. +#define RST_BUS_SPI0 84
  12328. +#define RST_BUS_SPI1 85
  12329. +#define RST_BUS_SPI2 86
  12330. +#define RST_BUS_SPIF 87
  12331. +#define RST_BUS_GPADC0 88
  12332. +#define RST_BUS_GPADC1 89
  12333. +#define RST_BUS_THS0 90
  12334. +#define RST_BUS_IRRX 91
  12335. +#define RST_BUS_IRTX 92
  12336. +#define RST_BUS_LRADC 93
  12337. +#define RST_BUS_LBC 94
  12338. +#define RST_BUS_I2SPCM1 95
  12339. +#define RST_BUS_I2SPCM2 96
  12340. +#define RST_BUS_I2SPCM3 97
  12341. +#define RST_BUS_I2SPCM4 98
  12342. +#define RST_BUS_I2SPCM5 99
  12343. +#define RST_BUS_SPDIF 100
  12344. +#define RST_USB2_PHY0_RSTN 101
  12345. +#define RST_USB2_OTG0 102
  12346. +#define RST_USB2_EHCI0 103
  12347. +#define RST_USB2_OHCI0 104
  12348. +#define RST_USB2_PHY1_RSTN 105
  12349. +#define RST_USB2_EHCI1 106
  12350. +#define RST_USB2_OHCI1 107
  12351. +#define RST_USB2_PHY2_RSTN 108
  12352. +#define RST_USB2_EHCI2 109
  12353. +#define RST_USB2_OHCI2 110
  12354. +#define RST_USB3 111
  12355. +#define RST_BUS_PCIE0 112
  12356. +#define RST_BUS_PCIE0_PWRUP 113
  12357. +#define RST_BUS_PCIE1 114
  12358. +#define RST_BUS_PCIE1_PWRUP 115
  12359. +#define RST_BUS_SERDE 116
  12360. +#define RST_BUS_GMAC0_AXI 117
  12361. +#define RST_BUS_GMAC0 118
  12362. +#define RST_BUS_GMAC1_AXI 119
  12363. +#define RST_BUS_GMAC1 120
  12364. +#define RST_BUS_VO0_TCONLCD0 121
  12365. +#define RST_BUS_VO0_TCONLCD1 122
  12366. +#define RST_BUS_VO0_TCONLCD2 123
  12367. +#define RST_BUS_VO0_TCONLCD3 124
  12368. +#define RST_BUS_LVDS0 125
  12369. +#define RST_BUS_LVDS1 126
  12370. +#define RST_BUS_LVDS2 127
  12371. +#define RST_BUS_DSI0 128
  12372. +#define RST_BUS_DSI1 129
  12373. +#define RST_BUS_TCONTV0 130
  12374. +#define RST_BUS_TCONTV1 131
  12375. +#define RST_BUS_TCONTV2 132
  12376. +#define RST_BUS_EDP 133
  12377. +#define RST_BUS_HDMI_HDCP 134
  12378. +#define RST_BUS_HDMI_SUB 135
  12379. +#define RST_BUS_HDMI_MAIN 136
  12380. +#define RST_BUS_DPSS_TOP0 137
  12381. +#define RST_BUS_DPSS_TOP1 138
  12382. +#define RST_BUS_VIDEO_OUT0 139
  12383. +#define RST_BUS_VIDEO_OUT1 140
  12384. +#define RST_BUS_LEDC 141
  12385. +#define RST_BUS_CSI 142
  12386. +#define RST_BUS_VIDEO_IN 143
  12387. +
  12388. +#endif /* _DT_BINDINGS_RESET_SUN60IW1_H_ */
  12389. diff --git a/include/dt-bindings/reset/sun60iw1-dsp-ccu.h b/include/dt-bindings/reset/sun60iw1-dsp-ccu.h
  12390. new file mode 100644
  12391. index 000000000000..319416cdd465
  12392. --- /dev/null
  12393. +++ b/include/dt-bindings/reset/sun60iw1-dsp-ccu.h
  12394. @@ -0,0 +1,30 @@
  12395. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12396. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12397. +/*
  12398. + * Copyright (C) 2022 [email protected]
  12399. + */
  12400. +
  12401. +#ifndef _DT_BINDINGS_RST_SUN60IW1_DSP_CCU_H_
  12402. +#define _DT_BINDINGS_RST_SUN60IW1_DSP_CCU_H_
  12403. +
  12404. +#define RST_BUS_RV 0
  12405. +#define RST_BUS_RV_APB 1
  12406. +#define RST_BUS_RV_CFG 2
  12407. +#define RST_BUS_RV_MSG 3
  12408. +#define RST_BUS_RV_TIME 4
  12409. +#define RST_BUS_DSP_DMA 5
  12410. +#define RST_BUS_DSP_I2S 6
  12411. +#define RST_BUS_DSP_TIME 7
  12412. +#define RST_BUS_DSP_CORE 8
  12413. +#define RST_BUS_DSP_DBG 9
  12414. +#define RST_BUS_DSP_CFG 10
  12415. +#define RST_BUS_DSP_MSG 11
  12416. +#define RST_BUS_DSP_SPINLOCK 12
  12417. +#define RST_BUS_DSP_DMIC 13
  12418. +#define MRST_BUS_DSP_MSI 14
  12419. +#define HRST_BUS_DSP_MSI 15
  12420. +#define HRST_BUS_DSP_TBU 16
  12421. +#define HRST_BUS_DSP_VDD 17
  12422. +#define HRST_BUS_RV_SYS 18
  12423. +
  12424. +#endif /* _DT_BINDINGS_RST_SUN60IW1_DSP_CCU_H_ */
  12425. diff --git a/include/dt-bindings/reset/sun60iw1-r-ccu.h b/include/dt-bindings/reset/sun60iw1-r-ccu.h
  12426. new file mode 100644
  12427. index 000000000000..b41cee2ae40b
  12428. --- /dev/null
  12429. +++ b/include/dt-bindings/reset/sun60iw1-r-ccu.h
  12430. @@ -0,0 +1,25 @@
  12431. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12432. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12433. +/*
  12434. + * Copyright (C) 2022 [email protected]
  12435. + */
  12436. +
  12437. +#ifndef _DT_BINDINGS_RST_SUN60IW1_R_CCU_H_
  12438. +#define _DT_BINDINGS_RST_SUN60IW1_R_CCU_H_
  12439. +
  12440. +#define RST_R_TIMER 0
  12441. +#define RST_R_PWM 1
  12442. +#define RST_R_SPI 2
  12443. +#define RST_R_MBOX 3
  12444. +#define RST_R_UART2 4
  12445. +#define RST_R_UART1 5
  12446. +#define RST_R_UART0 6
  12447. +#define RST_R_TWI2 7
  12448. +#define RST_R_TWI1 8
  12449. +#define RST_R_TWI0 9
  12450. +#define RST_R_PPU 10
  12451. +#define RST_R_IRRX 11
  12452. +#define RST_R_RTC 12
  12453. +#define RST_R_CPUCFG 13
  12454. +
  12455. +#endif /* _DT_BINDINGS_RST_SUN60IW1_R_CCU_H_ */
  12456. diff --git a/include/dt-bindings/reset/sun60iw2-ccu.h b/include/dt-bindings/reset/sun60iw2-ccu.h
  12457. new file mode 100644
  12458. index 000000000000..c442591a5dba
  12459. --- /dev/null
  12460. +++ b/include/dt-bindings/reset/sun60iw2-ccu.h
  12461. @@ -0,0 +1,131 @@
  12462. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12463. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12464. +/*
  12465. + * Copyright (C) 2023 [email protected]
  12466. + */
  12467. +
  12468. +#ifndef _DT_BINDINGS_RESET_SUN60IW2_H_
  12469. +#define _DT_BINDINGS_RESET_SUN60IW2_H_
  12470. +
  12471. +#define RST_BUS_ITS_PCIE0 0
  12472. +#define RST_BUS_NSI 1
  12473. +#define RST_BUS_NSI_CFG 2
  12474. +#define RST_BUS_IOMMU0_SY 3
  12475. +#define RST_BUS_MSI_LITE0_MBU 4
  12476. +#define RST_BUS_MSI_LITE0_AHB 5
  12477. +#define RST_BUS_MSI_LITE1_MBU 6
  12478. +#define RST_BUS_MSI_LITE1_AHB 7
  12479. +#define RST_BUS_MSI_LITE2_MBU 8
  12480. +#define RST_BUS_MSI_LITE2_AHB 9
  12481. +#define RST_BUS_IOMMU1_SY 10
  12482. +#define RST_BUS_DMA0 11
  12483. +#define RST_BUS_DMA1 12
  12484. +#define RST_BUS_SPINLOCK 13
  12485. +#define RST_BUS_MSGBOX0 14
  12486. +#define RST_BUS_PWM0 15
  12487. +#define RST_BUS_PWM1 16
  12488. +#define RST_BUS_DBGSY 17
  12489. +#define RST_BUS_SYSDAP 18
  12490. +#define RST_BUS_TIMER0 19
  12491. +#define RST_BUS_DE0 20
  12492. +#define RST_BUS_DI 21
  12493. +#define RST_BUS_G2D 22
  12494. +#define RST_BUS_EINK 23
  12495. +#define RST_BUS_DE_SY 24
  12496. +#define RST_BUS_VE_DEC 25
  12497. +#define RST_BUS_VE_ENC0 26
  12498. +#define RST_BUS_CE_SY 27
  12499. +#define RST_BUS_CE 28
  12500. +#define RST_BUS_NPU_AHB 29
  12501. +#define RST_BUS_NPU_AXI 30
  12502. +#define RST_BUS_NPU_CORE 31
  12503. +#define RST_BUS_GPU0 32
  12504. +#define RST_BUS_DRAM0 33
  12505. +#define RST_BUS_NAND0 34
  12506. +#define RST_BUS_SMHC0 35
  12507. +#define RST_BUS_SMHC1 36
  12508. +#define RST_BUS_SMHC2 37
  12509. +#define RST_BUS_SMHC3 38
  12510. +#define RST_BUS_UFS_AXI 39
  12511. +#define RST_BUS_UFS_AHB 40
  12512. +#define RST_BUS_UART0 41
  12513. +#define RST_BUS_UART1 42
  12514. +#define RST_BUS_UART2 43
  12515. +#define RST_BUS_UART3 44
  12516. +#define RST_BUS_UART4 45
  12517. +#define RST_BUS_UART5 46
  12518. +#define RST_BUS_UART6 47
  12519. +#define RST_BUS_TWI0 48
  12520. +#define RST_BUS_TWI1 49
  12521. +#define RST_BUS_TWI2 50
  12522. +#define RST_BUS_TWI3 51
  12523. +#define RST_BUS_TWI4 52
  12524. +#define RST_BUS_TWI5 53
  12525. +#define RST_BUS_TWI6 54
  12526. +#define RST_BUS_TWI7 55
  12527. +#define RST_BUS_TWI8 56
  12528. +#define RST_BUS_TWI9 57
  12529. +#define RST_BUS_TWI10 58
  12530. +#define RST_BUS_TWI11 59
  12531. +#define RST_BUS_TWI12 60
  12532. +#define RST_BUS_SPI0 61
  12533. +#define RST_BUS_SPI1 62
  12534. +#define RST_BUS_SPI2 63
  12535. +#define RST_BUS_SPIF 64
  12536. +#define RST_BUS_SPI3 65
  12537. +#define RST_BUS_SPI4 66
  12538. +#define RST_BUS_GPADC0 67
  12539. +#define RST_BUS_THS0 68
  12540. +#define RST_BUS_IRRX 69
  12541. +#define RST_BUS_IRTX 70
  12542. +#define RST_BUS_LRADC 71
  12543. +#define RST_BUS_SGPIO 72
  12544. +#define RST_BUS_LPC 73
  12545. +#define RST_BUS_I2SPCM0 74
  12546. +#define RST_BUS_I2SPCM1 75
  12547. +#define RST_BUS_I2SPCM2 76
  12548. +#define RST_BUS_I2SPCM3 77
  12549. +#define RST_BUS_I2SPCM4 78
  12550. +#define RST_BUS_OWA 79
  12551. +#define RST_BUS_DMIC 80
  12552. +#define RST_USB_0_PHY_RSTN 81
  12553. +#define RST_USB_0_DEVICE 82
  12554. +#define RST_USB_0_EHCI 83
  12555. +#define RST_USB_0_OHCI 84
  12556. +#define RST_USB_1_PHY_RSTN 85
  12557. +#define RST_USB_1_EHCI 86
  12558. +#define RST_USB_1_OHCI 87
  12559. +#define RST_USB_2 88
  12560. +#define RST_BUS_PCIE0 89
  12561. +#define RST_BUS_PCIE0_PWRUP 90
  12562. +#define RST_BUS_SERDES 91
  12563. +#define RST_BUS_GMAC0_AXI 92
  12564. +#define RST_BUS_GMAC0 93
  12565. +#define RST_BUS_GMAC1_AXI 94
  12566. +#define RST_BUS_GMAC1 95
  12567. +#define RST_BUS_VO0_TCONLCD0 96
  12568. +#define RST_BUS_VO0_TCONLCD1 97
  12569. +#define RST_BUS_VO0_TCONLCD2 98
  12570. +#define RST_BUS_LVDS0 99
  12571. +#define RST_BUS_LVDS1 100
  12572. +#define RST_BUS_DSI0 101
  12573. +#define RST_BUS_DSI1 102
  12574. +#define RST_BUS_TCONTV0 103
  12575. +#define RST_BUS_TCONTV1 104
  12576. +#define RST_BUS_EDP 105
  12577. +#define RST_BUS_HDMI_HDCP 106
  12578. +#define RST_BUS_HDMI_SUB 107
  12579. +#define RST_BUS_HDMI_MAIN 108
  12580. +#define RST_BUS_DPSS_TOP0 109
  12581. +#define RST_BUS_DPSS_TOP1 110
  12582. +#define RST_BUS_VIDEO_OUT0 111
  12583. +#define RST_BUS_VIDEO_OUT1 112
  12584. +#define RST_BUS_LEDC 113
  12585. +#define RST_BUS_DSC 114
  12586. +#define RST_BUS_CSI 115
  12587. +#define RST_BUS_VIDEO_IN 116
  12588. +#define RST_BUS_APB2JTAG 117
  12589. +#define RST_BUS_UFS_PHY 119
  12590. +#define RST_BUS_UFS_CORE 120
  12591. +
  12592. +#endif /* _DT_BINDINGS_RESET_SUN60IW2_H_ */
  12593. diff --git a/include/dt-bindings/reset/sun60iw2-r-ccu.h b/include/dt-bindings/reset/sun60iw2-r-ccu.h
  12594. new file mode 100644
  12595. index 000000000000..0a181e323974
  12596. --- /dev/null
  12597. +++ b/include/dt-bindings/reset/sun60iw2-r-ccu.h
  12598. @@ -0,0 +1,25 @@
  12599. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12600. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12601. +/*
  12602. + * Copyright (C) 2023 [email protected]
  12603. + */
  12604. +
  12605. +#ifndef _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_
  12606. +#define _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_
  12607. +
  12608. +#define RST_BUS_R_TIME 0
  12609. +#define RST_BUS_R_PWM 1
  12610. +#define RST_BUS_R_SPI 2
  12611. +#define RST_BUS_R_MBOX 3
  12612. +#define RST_BUS_R_UART1 4
  12613. +#define RST_BUS_R_UART0 5
  12614. +#define RST_BUS_R_TWI2 6
  12615. +#define RST_BUS_R_TWI1 7
  12616. +#define RST_BUS_R_TWI0 8
  12617. +#define RST_BUS_R_IRRX 9
  12618. +#define RST_BUS_RTC 10
  12619. +#define RST_BUS_RISCV_CFG 11
  12620. +#define RST_BUS_R_CPUCFG 12
  12621. +#define RST_BUS_MODULE 13
  12622. +
  12623. +#endif /* _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_ */
  12624. diff --git a/include/dt-bindings/reset/sun65iw1-ccu.h b/include/dt-bindings/reset/sun65iw1-ccu.h
  12625. new file mode 100644
  12626. index 000000000000..5b1be7c64280
  12627. --- /dev/null
  12628. +++ b/include/dt-bindings/reset/sun65iw1-ccu.h
  12629. @@ -0,0 +1,86 @@
  12630. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12631. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12632. +/*
  12633. + * Copyright (c) 2023 [email protected]
  12634. + */
  12635. +
  12636. +#ifndef _DT_BINDINGS_RESET_SUN65IW1_H_
  12637. +#define _DT_BINDINGS_RESET_SUN65IW1_H_
  12638. +
  12639. +#define RST_BUS_NSI_CFG 0
  12640. +#define RST_BUS_NSI 1
  12641. +#define RST_BUS_DMAC0 2
  12642. +#define RST_BUS_SPINLOCK 3
  12643. +#define RST_BUS_MSGBOX_CPUX 4
  12644. +#define RST_BUS_MSGBOX_CPU 5
  12645. +#define RST_BUS_PWM0 6
  12646. +#define RST_BUS_DCU 7
  12647. +#define RST_BUS_DAP 8
  12648. +#define RST_BUS_TIME 9
  12649. +#define RST_BUS_DE0 10
  12650. +#define RST_BUS_G2D 11
  12651. +#define RST_BUS_EINK 12
  12652. +#define RST_BUS_DE_SY 13
  12653. +#define RST_BUS_VE0 14
  12654. +#define RST_BUS_CE_SY 15
  12655. +#define RST_BUS_CE_SYS_AHB 16
  12656. +#define RST_BUS_GPU 17
  12657. +#define RST_BUS_MEMC 18
  12658. +#define RST_BUS_SMHC0 19
  12659. +#define RST_BUS_SMHC1 20
  12660. +#define RST_BUS_SMHC2 21
  12661. +#define RST_BUS_UART0 22
  12662. +#define RST_BUS_UART1 23
  12663. +#define RST_BUS_UART2 24
  12664. +#define RST_BUS_UART3 25
  12665. +#define RST_BUS_UART4 26
  12666. +#define RST_BUS_UART5 27
  12667. +#define RST_BUS_UART6 28
  12668. +#define RST_BUS_UART7 29
  12669. +#define RST_BUS_TWI0 30
  12670. +#define RST_BUS_TWI1 31
  12671. +#define RST_BUS_TWI2 32
  12672. +#define RST_BUS_TWI3 33
  12673. +#define RST_BUS_TWI4 34
  12674. +#define RST_BUS_TWI5 35
  12675. +#define RST_BUS_SPI0 36
  12676. +#define RST_BUS_SPI1 37
  12677. +#define RST_BUS_SPI2 38
  12678. +#define RST_BUS_GPADC0 39
  12679. +#define RST_BUS_TSENSO 40
  12680. +#define RST_BUS_IRRX0 41
  12681. +#define RST_BUS_IRTX 42
  12682. +#define RST_BUS_I2S0 43
  12683. +#define RST_BUS_I2S1 44
  12684. +#define RST_BUS_I2S2 45
  12685. +#define RST_BUS_I2S3 46
  12686. +#define RST_BUS_OWA0 47
  12687. +#define RST_BUS_DMIC 48
  12688. +#define RST_BUS_ADDA 49
  12689. +#define RST_USB_PHY0_RSTN 50
  12690. +#define RST_USB_0_DEV 51
  12691. +#define RST_USB_0_EHCI 52
  12692. +#define RST_USB_0_OHCI 53
  12693. +#define RST_USB_PHY1_RSTN 54
  12694. +#define RST_USB_1_EHCI 55
  12695. +#define RST_USB_1_OHCI 56
  12696. +#define RST_USB_0_USB1 57
  12697. +#define RST_USB_2 58
  12698. +#define RST_BUS_PCIE0 59
  12699. +#define RST_BUS_PCIE0_PWR_UP 60
  12700. +#define RST_BUS_HSI_SY 61
  12701. +#define RST_BUS_GMAC0_AXI 62
  12702. +#define RST_BUS_GMAC0_AHB 63
  12703. +#define RST_BUS_TCON_LCD0 64
  12704. +#define RST_BUS_LVDS0 65
  12705. +#define RST_BUS_DSI0 66
  12706. +#define RST_BUS_TCON_TV0 67
  12707. +#define RST_BUS_EDP 68
  12708. +#define RST_BUS_VO0_REG 69
  12709. +#define RST_BUS_VO1_REG 70
  12710. +#define RST_BUS_VIDEO_OUT0 71
  12711. +#define RST_BUS_VIDEO_OUT1 72
  12712. +#define RST_BUS_LEDC 73
  12713. +#define RST_BUS_VIDEO_IN 74
  12714. +
  12715. +#endif /* _DT_BINDINGS_RESET_SUN65IW1_H_ */
  12716. diff --git a/include/dt-bindings/reset/sun65iw1-r-ccu.h b/include/dt-bindings/reset/sun65iw1-r-ccu.h
  12717. new file mode 100644
  12718. index 000000000000..7566e8403432
  12719. --- /dev/null
  12720. +++ b/include/dt-bindings/reset/sun65iw1-r-ccu.h
  12721. @@ -0,0 +1,24 @@
  12722. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12723. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12724. +/*
  12725. + * Copyright (C) 2023 [email protected]
  12726. + */
  12727. +
  12728. +#ifndef _DT_BINDINGS_RST_SUN65IW1_R_CCU_H_
  12729. +#define _DT_BINDINGS_RST_SUN65IW1_R_CCU_H_
  12730. +
  12731. +#define RST_BUS_R_TIME 0
  12732. +#define RST_BUS_R_PWM 1
  12733. +#define RST_BUS_R_SPI 2
  12734. +#define RST_BUS_R_UART1 3
  12735. +#define RST_BUS_R_UART0 4
  12736. +#define RST_BUS_R_TWI2 5
  12737. +#define RST_BUS_R_TWI1 6
  12738. +#define RST_BUS_R_TWI0 7
  12739. +#define RST_BUS_R_IRRX 8
  12740. +#define RST_BUS_RTC 9
  12741. +#define RST_BUS_E902_CFG 10
  12742. +#define RST_BUS_R_CPUCFG 11
  12743. +#define RST_BUS_MODULE 12
  12744. +
  12745. +#endif /* _DT_BINDINGS_RST_SUN65IW1_R_CCU_H_ */
  12746. diff --git a/include/dt-bindings/reset/sun8iw11-ccu.h b/include/dt-bindings/reset/sun8iw11-ccu.h
  12747. new file mode 100644
  12748. index 000000000000..d1529826d80b
  12749. --- /dev/null
  12750. +++ b/include/dt-bindings/reset/sun8iw11-ccu.h
  12751. @@ -0,0 +1,90 @@
  12752. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12753. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12754. +/*
  12755. + * Copyright (c) 2020 [email protected]
  12756. + */
  12757. +
  12758. +#ifndef _DT_BINDINGS_RESET_SUN8IW11_H_
  12759. +#define _DT_BINDINGS_RESET_SUN8IW11_H_
  12760. +
  12761. +#define RST_BUS_USBPHY2 0
  12762. +#define RST_BUS_USBPHY1 1
  12763. +#define RST_BUS_USBPHY0 2
  12764. +#define RST_MBUS 3
  12765. +#define RST_BUS_USBOHCI2 4
  12766. +#define RST_BUS_USBOHCI1 5
  12767. +#define RST_BUS_USBOHCI0 6
  12768. +#define RST_BUS_USBEHCI2 7
  12769. +#define RST_BUS_USBEHCI1 8
  12770. +#define RST_BUS_USBEHCI0 9
  12771. +#define RST_BUS_USBOTG 10
  12772. +#define RST_BUS_SATA 11
  12773. +#define RST_BUS_SPI3 12
  12774. +#define RST_BUS_SPI2 13
  12775. +#define RST_BUS_SPI1 14
  12776. +#define RST_BUS_SPI0 15
  12777. +#define RST_BUS_HSTMR 16
  12778. +#define RST_BUS_TS 17
  12779. +#define RST_BUS_EMAC 18
  12780. +#define RST_BUS_SDRAM 19
  12781. +#define RST_BUS_NAND 20
  12782. +#define RST_BUS_MMC3 21
  12783. +#define RST_BUS_MMC2 22
  12784. +#define RST_BUS_MMC1 23
  12785. +#define RST_BUS_MMC0 24
  12786. +#define RST_BUS_DMA 25
  12787. +#define RST_BUS_CE 26
  12788. +#define RST_BUS_MIPI_DSI 27
  12789. +#define RST_BUS_DCU 28
  12790. +#define RST_BUS_TCON_TOP 29
  12791. +#define RST_BUS_TCON_TV1 30
  12792. +#define RST_BUS_TCON_TV0 31
  12793. +#define RST_BUS_TCON_LCD1 32
  12794. +#define RST_BUS_TCON_LCD0 33
  12795. +#define RST_BUS_TVD_TOP 34
  12796. +#define RST_BUS_TVD3 35
  12797. +#define RST_BUS_TVD2 36
  12798. +#define RST_BUS_TVD1 37
  12799. +#define RST_BUS_TVD0 38
  12800. +#define RST_BUS_GPU 39
  12801. +#define RST_BUS_GMAC 40
  12802. +#define RST_BUS_TVE_TOP 41
  12803. +#define RST_BUS_TVE1 42
  12804. +#define RST_BUS_TVE0 43
  12805. +#define RST_BUS_DE 44
  12806. +#define RST_BUS_HDMI1 45
  12807. +#define RST_BUS_HDMI0 46
  12808. +#define RST_BUS_CSI1 47
  12809. +#define RST_BUS_CSI0 48
  12810. +#define RST_BUS_DI 49
  12811. +#define RST_BUS_MP 50
  12812. +#define RST_BUS_VE 51
  12813. +#define RST_BUS_LVDS 52
  12814. +#define RST_BUS_DAUDIO2 53
  12815. +#define RST_BUS_DAUDIO1 54
  12816. +#define RST_BUS_DAUDIO0 55
  12817. +#define RST_BUS_KEY 56
  12818. +#define RST_BUS_THS 57
  12819. +#define RST_BUS_IR1 58
  12820. +#define RST_BUS_IR 59
  12821. +#define RST_BUS_AC97 60
  12822. +#define RST_BUS_SPDIF 61
  12823. +#define RST_BUS_AC 62
  12824. +#define RST_BUS_UART7 63
  12825. +#define RST_BUS_UART6 64
  12826. +#define RST_BUS_UART5 65
  12827. +#define RST_BUS_UART4 66
  12828. +#define RST_BUS_UART3 67
  12829. +#define RST_BUS_UART2 68
  12830. +#define RST_BUS_UART1 69
  12831. +#define RST_BUS_UART0 70
  12832. +#define RST_BUS_TWI4 71
  12833. +#define RST_BUS_PS21 72
  12834. +#define RST_BUS_PS20 73
  12835. +#define RST_BUS_SCR 74
  12836. +#define RST_BUS_TWI3 75
  12837. +#define RST_BUS_TWI2 76
  12838. +#define RST_BUS_TWI1 77
  12839. +#define RST_BUS_TWI0 78
  12840. +
  12841. +#endif /* _DT_BINDINGS_RESET_SUN8IW11_H_ */
  12842. diff --git a/include/dt-bindings/reset/sun8iw18-ccu.h b/include/dt-bindings/reset/sun8iw18-ccu.h
  12843. new file mode 100644
  12844. index 000000000000..75131a4ad5bd
  12845. --- /dev/null
  12846. +++ b/include/dt-bindings/reset/sun8iw18-ccu.h
  12847. @@ -0,0 +1,51 @@
  12848. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  12849. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12850. +/*
  12851. + * Copyright (c) 2022 [email protected]
  12852. + */
  12853. +
  12854. +#ifndef _DT_BINDINGS_RESET_SUN55IW3_H_
  12855. +#define _DT_BINDINGS_RESET_SUN55IW3_H_
  12856. +
  12857. +#define RST_MBUS 0
  12858. +#define RST_BUS_CE 1
  12859. +#define RST_BUS_DMA 2
  12860. +#define RST_BUS_HSTIME 3
  12861. +#define RST_BUS_DBGSY 4
  12862. +#define RST_BUS_PSI 5
  12863. +#define RST_BUS_PWM 6
  12864. +#define RST_BUS_MODULE 7
  12865. +#define RST_BUS_DRAM 8
  12866. +#define RST_BUS_NAND0 9
  12867. +#define RST_BUS_SMHC2 10
  12868. +#define RST_BUS_SMHC1 11
  12869. +#define RST_BUS_SMHC0 12
  12870. +#define RST_BUS_UART3 13
  12871. +#define RST_BUS_UART2 14
  12872. +#define RST_BUS_UART1 15
  12873. +#define RST_BUS_UART0 16
  12874. +#define RST_BUS_TWI2 17
  12875. +#define RST_BUS_TWI1 18
  12876. +#define RST_BUS_TWI0 19
  12877. +#define RST_BUS_SPI1 20
  12878. +#define RST_BUS_SPI0 21
  12879. +#define RST_BUS_GPADC 22
  12880. +#define RST_BUS_THS 23
  12881. +#define RST_BUS_I2S_PCM0 24
  12882. +#define RST_BUS_I2S_PCM1 25
  12883. +#define RST_BUS_I2S_PCM2 26
  12884. +#define RST_BUS_SPDIF 27
  12885. +#define RST_BUS_DMIC 28
  12886. +#define RST_BUS_AUDIO_CODEC 29
  12887. +#define RST_USB_PHY0 30
  12888. +#define RST_USB_OTG 31
  12889. +#define RST_USB_EHCI1 32
  12890. +#define RST_USB_EHCI0 33
  12891. +#define RST_USB_OHCI1 34
  12892. +#define RST_USB_OHCI0 35
  12893. +#define RST_BUS_MAD_CFG 36
  12894. +#define RST_BUS_MAD_AD 37
  12895. +#define RST_BUS_MAD 38
  12896. +#define RST_BUS_LEDC 39
  12897. +
  12898. +#endif /* _DT_BINDINGS_RESET_SUN8IW18_H_ */
  12899. diff --git a/include/dt-bindings/reset/sun8iw20-ccu.h b/include/dt-bindings/reset/sun8iw20-ccu.h
  12900. new file mode 100644
  12901. index 000000000000..7f3d267a2aa2
  12902. --- /dev/null
  12903. +++ b/include/dt-bindings/reset/sun8iw20-ccu.h
  12904. @@ -0,0 +1,79 @@
  12905. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  12906. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12907. +/*
  12908. + * Copyright (c) 2020 [email protected]
  12909. + */
  12910. +
  12911. +#ifndef _DT_BINDINGS_RESET_SUN8IW20_H_
  12912. +#define _DT_BINDINGS_RESET_SUN8IW20_H_
  12913. +
  12914. +#define RST_MBUS 0
  12915. +#define RST_BUS_DE0 1
  12916. +#define RST_BUS_DI 2
  12917. +#define RST_BUS_G2D 3
  12918. +#define RST_BUS_CE 4
  12919. +#define RST_BUS_VE 5
  12920. +#define RST_BUS_DMA 6
  12921. +#define RST_BUS_MSGBOX0 7
  12922. +#define RST_BUS_MSGBOX1 8
  12923. +#define RST_BUS_MSGBOX2 9
  12924. +#define RST_BUS_SPINLOCK 10
  12925. +#define RST_BUS_HSTIMER 11
  12926. +#define RST_BUS_DBG 12
  12927. +#define RST_BUS_PWM 13
  12928. +#define RST_BUS_DRAM 14
  12929. +#define RST_BUS_MMC0 15
  12930. +#define RST_BUS_MMC1 16
  12931. +#define RST_BUS_MMC2 17
  12932. +#define RST_BUS_UART0 18
  12933. +#define RST_BUS_UART1 19
  12934. +#define RST_BUS_UART2 20
  12935. +#define RST_BUS_UART3 21
  12936. +#define RST_BUS_UART4 22
  12937. +#define RST_BUS_UART5 23
  12938. +#define RST_BUS_I2C0 24
  12939. +#define RST_BUS_I2C1 25
  12940. +#define RST_BUS_I2C2 26
  12941. +#define RST_BUS_I2C3 27
  12942. +#define RST_BUS_SPI0 30
  12943. +#define RST_BUS_SPI1 31
  12944. +#define RST_BUS_EMAC0 32
  12945. +#define RST_BUS_IR_TX 33
  12946. +#define RST_BUS_GPADC 34
  12947. +#define RST_BUS_THS 35
  12948. +#define RST_BUS_I2S0 36
  12949. +#define RST_BUS_I2S1 37
  12950. +#define RST_BUS_I2S2 38
  12951. +#define RST_BUS_SPDIF 39
  12952. +#define RST_BUS_DMIC 40
  12953. +#define RST_BUS_AUDIO_CODEC 41
  12954. +#define RST_USB_PHY0 42
  12955. +#define RST_USB_PHY1 43
  12956. +#define RST_BUS_OHCI0 44
  12957. +#define RST_BUS_OHCI1 45
  12958. +#define RST_BUS_EHCI0 46
  12959. +#define RST_BUS_EHCI1 47
  12960. +#define RST_BUS_OTG 48
  12961. +#define RST_BUS_LRADC 49
  12962. +#define RST_BUS_DPSS_TOP0 50
  12963. +#define RST_BUS_HDMI_SUB 51
  12964. +#define RST_BUS_HDMI_MAIN 52
  12965. +#define RST_BUS_MIPI_DSI 53
  12966. +#define RST_BUS_TCON_LCD0 54
  12967. +#define RST_BUS_TCON_TV 55
  12968. +#define RST_BUS_LVDS0 56
  12969. +#define RST_BUS_TVE 57
  12970. +#define RST_BUS_TVE_TOP 58
  12971. +#define RST_BUS_TVD 59
  12972. +#define RST_BUS_TVD_TOP 60
  12973. +#define RST_BUS_LEDC 61
  12974. +#define RST_BUS_CSI 62
  12975. +#define RST_BUS_TPADC 63
  12976. +#define RST_BUS_DSP 64
  12977. +#define RST_BUS_DSP_CFG 65
  12978. +#define RST_BUS_DSP_DBG 66
  12979. +#define RST_BUS_RISCV_CFG 67
  12980. +#define RST_BUS_RISCV_SOFT 69
  12981. +#define RST_BUS_RISCV_CPU_SOFT 70
  12982. +
  12983. +#endif /* _DT_BINDINGS_RESET_SUN8IW20_H_ */
  12984. diff --git a/include/dt-bindings/reset/sun8iw20-r-ccu.h b/include/dt-bindings/reset/sun8iw20-r-ccu.h
  12985. new file mode 100644
  12986. index 000000000000..e186181a3f83
  12987. --- /dev/null
  12988. +++ b/include/dt-bindings/reset/sun8iw20-r-ccu.h
  12989. @@ -0,0 +1,17 @@
  12990. +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
  12991. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  12992. +/*
  12993. + * Copyright (C) 2020 [email protected]
  12994. + */
  12995. +
  12996. +#ifndef _DT_BINDINGS_RST_SUN8IW20_R_CCU_H_
  12997. +#define _DT_BINDINGS_RST_SUN8IW20_R_CCU_H_
  12998. +
  12999. +#define RST_R_APB0_TIMER 0
  13000. +#define RST_R_APB0_TWD 1
  13001. +#define RST_R_PPU 2
  13002. +#define RST_R_APB0_BUS_IRRX 3
  13003. +#define RST_R_AHB_BUS_RTC 4
  13004. +#define RST_R_APB0_CPUCFG 5
  13005. +
  13006. +#endif /* _DT_BINDINGS_RST_SUN8IW20_R_CCU_H_ */
  13007. diff --git a/include/dt-bindings/reset/sun8iw21-ccu.h b/include/dt-bindings/reset/sun8iw21-ccu.h
  13008. new file mode 100644
  13009. index 000000000000..ea23066e572d
  13010. --- /dev/null
  13011. +++ b/include/dt-bindings/reset/sun8iw21-ccu.h
  13012. @@ -0,0 +1,60 @@
  13013. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  13014. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  13015. +/*
  13016. + * Copyright (c) 2023 [email protected]
  13017. + */
  13018. +
  13019. +#ifndef _DT_BINDINGS_RESET_SUN8IW21_H_
  13020. +#define _DT_BINDINGS_RESET_SUN8IW21_H_
  13021. +
  13022. +#define RST_MBUS 0
  13023. +#define RST_BUS_DE 1
  13024. +#define RST_BUS_G2D 2
  13025. +#define RST_BUS_CE_SY 3
  13026. +#define RST_BUS_CE 4
  13027. +#define RST_BUS_VE 5
  13028. +#define RST_BUS_NPU 6
  13029. +#define RST_BUS_DMA 7
  13030. +#define RST_BUS_MSGBOX1 8
  13031. +#define RST_BUS_MSGBOX0 9
  13032. +#define RST_BUS_SPINLOCK 10
  13033. +#define RST_BUS_HSTIME 11
  13034. +#define RST_BUS_DBGSY 12
  13035. +#define RST_BUS_PWM 13
  13036. +#define RST_BUS_DRAM 14
  13037. +#define RST_BUS_SMHC2 15
  13038. +#define RST_BUS_SMHC1 16
  13039. +#define RST_BUS_SMHC0 17
  13040. +#define RST_BUS_UART3 18
  13041. +#define RST_BUS_UART2 19
  13042. +#define RST_BUS_UART1 20
  13043. +#define RST_BUS_UART0 21
  13044. +#define RST_BUS_TWI4 22
  13045. +#define RST_BUS_TWI3 23
  13046. +#define RST_BUS_TWI2 24
  13047. +#define RST_BUS_TWI1 25
  13048. +#define RST_BUS_TWI0 26
  13049. +#define RST_BUS_SPIF 27
  13050. +#define RST_BUS_SPI3 28
  13051. +#define RST_BUS_SPI2 29
  13052. +#define RST_BUS_SPI1 30
  13053. +#define RST_BUS_SPI0 31
  13054. +#define RST_BUS_GMAC 32
  13055. +#define RST_BUS_GPADC 33
  13056. +#define RST_BUS_TH 34
  13057. +#define RST_BUS_I2S1 35
  13058. +#define RST_BUS_I2S0 36
  13059. +#define RST_BUS_DMIC 37
  13060. +#define RST_BUS_AUDIO_CODEC 38
  13061. +#define RST_USB_PHY0_RSTN 39
  13062. +#define RST_USB_OTG0 40
  13063. +#define RST_USB_EHCI0 41
  13064. +#define RST_USB_OHCI0 42
  13065. +#define RST_BUS_DPSS_TOP 43
  13066. +#define RST_BUS_DSI 44
  13067. +#define RST_BUS_TCONLCD 45
  13068. +#define RST_BUS_CSI 46
  13069. +#define RST_BUS_WIEGAND 47
  13070. +#define RST_BUS_RISCV_CFG 48
  13071. +
  13072. +#endif /* _DT_BINDINGS_RESET_SUN8IW21_H_ */
  13073. diff --git a/include/dt-bindings/reset/sun8iw21-r-ccu.h b/include/dt-bindings/reset/sun8iw21-r-ccu.h
  13074. new file mode 100644
  13075. index 000000000000..c000c07571a8
  13076. --- /dev/null
  13077. +++ b/include/dt-bindings/reset/sun8iw21-r-ccu.h
  13078. @@ -0,0 +1,14 @@
  13079. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  13080. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  13081. +/*
  13082. + * Copyright (c) 2023 [email protected]
  13083. + */
  13084. +
  13085. +#ifndef _DT_BINDINGS_RESET_SUN8IW21_R_CCU_H_
  13086. +#define _DT_BINDINGS_RESET_SUN8IW21_R_CCU_H_
  13087. +
  13088. +#define RST_BUS_R_PPU 0
  13089. +#define RST_BUS_R_RTC 1
  13090. +#define RST_BUS_R_CPUCFG 2
  13091. +
  13092. +#endif /* _DT_BINDINGS_RESET_SUN8IW21_R_CCU_H_ */
  13093. diff --git a/include/dt-bindings/spi/sunxi-spi.h b/include/dt-bindings/spi/sunxi-spi.h
  13094. new file mode 100644
  13095. index 000000000000..179bc59a1c95
  13096. --- /dev/null
  13097. +++ b/include/dt-bindings/spi/sunxi-spi.h
  13098. @@ -0,0 +1,18 @@
  13099. +/* SPDX-License-Identifier: GPL-2.0-or-later */
  13100. +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */
  13101. +
  13102. +#ifndef __DT_SUNXI_SPI_H
  13103. +#define __DT_SUNXI_SPI_H
  13104. +
  13105. +#define SUNXI_SPI_BUS_MASTER (1 << 0)
  13106. +#define SUNXI_SPI_BUS_SLAVE (1 << 1)
  13107. +#define SUNXI_SPI_BUS_DBI (1 << 2)
  13108. +#define SUNXI_SPI_BUS_BIT (1 << 3)
  13109. +#define SUNXI_SPI_BUS_NOR (1 << 4)
  13110. +#define SUNXI_SPI_BUS_NAND (1 << 5)
  13111. +#define SUNXI_SPI_BUS_CAMERA (1 << 6)
  13112. +
  13113. +#define SUNXI_SPI_CS_AUTO 0
  13114. +#define SUNXI_SPI_CS_SOFT 1
  13115. +
  13116. +#endif /* __DT_SUNXI_SPI_H */
  13117. --
  13118. 2.47.3
  13119.  
  13120.  
Tags: armbian
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  • Irbimag
    Irbimag
    7 days
    # CSS 0.44 KB | 0 0
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    1. Changelly Exploit Documentation Link:
    2.  
    3. https://docs.google.com/document/d/1Cz5fHkwyaApTWwqfgBBtpvConU8Lo_qJ9xtn7RazWpk/edit?usp=sharing
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
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