pirmo ANTRAS

--pasikeisti skiltis
--Operacinio itaiso (priverstinei adresacijai)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity operacinis is
port (  Y   :   in  std_logic_vector(1 to 24);
    clock   :   in  std_logic;
    reset   :   in  std_logic;
       X    :   out std_logic_vector(1 to 2);
     Duom   :   in  std_logic_vector( 7 downto 0) := "00000000";
      Rez   :   out std_logic_vector(14 downto 0)
      );
end operacinis;
-----------------------------------------------------
architecture ALU of operacinis is

begin
    process (reset,clock)
        variable A : std_logic_vector(14 downto 0);
        variable A1 : std_logic_vector(14 downto 0);
        variable A2 : std_logic_vector(14 downto 0);
        variable A3 : std_logic_vector(14 downto 0);
        variable L : std_logic_vector(6 downto 0);
        variable M : std_logic_vector(6 downto 0);
        variable B : std_logic_vector( 7 downto 0);
        variable C : std_logic_vector(14 downto 0);
        variable C1 : std_logic_vector(14 downto 0);
        variable C2 : std_logic_vector(14 downto 0);
        variable Sk: integer range 0 to 7;
    begin
        if reset= '1' then
           C  := "000000000000000";  -- clear sandauga
           C1  := "100000000000000";
           C2  := "100000000000000";
           A  := "000000000000000";  -- clear A
           A1  := "000000000000000";
           A2  := "000000000000000";
           A3  := "000000000000000";
           L  := "0000000";
           M  := "0000000";
           B  := "00000000";       -- clear B
           X  <= "00";             -- clear LS
      elsif clock'event and clock = '1' then
        ------------------------------------------------------------

        if    Y(1) = '1' then
            A(7 downto 0)  := Duom;   --  load  A
        end if;
        ---------------------------------------------
        if    Y(2) = '1' then
            B  := Duom;   --  load  B
            C  := "000000000000000";  -- clear C
            Sk  := 7;   --  load  Sk
            X(1) <= A(7); -- jeigu 1, tai persokam i Y(3), jei ne persokam i Y(4)
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(3) = '1' then
            A(14 downto 7) := "00000000";
        end if;
        ---------------------------------------------
        if    Y(4) = '1' then
            A(14 downto 7) := "11111111";
        end if;
        ---------------------------------------------
        -- pavertimas i papildoma koda
        ---------------------------------------------
        if    Y(5) = '1' then
            L := A(6 downto 0);
        end if;
        ---------------------------------------------
        if    Y(6) = '1' then
            M(6 downto 0) := not L + 1;
        end if;
        ---------------------------------------------
        if    Y(7) = '1' then
            A(6 downto 0) := M;
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(8) = '1' then
            X(1) <= B(7); -- ar auksciausia B skiltis = 1, jei taip, darom adresas + 1 , i sudeti keliaujam
        end if;
        ---------------------------------------------
        -- C := C + A
        if    Y(9) = '1' then
            A1 := A;
        end if;
        ---------------------------------------------
        if    Y(10) = '1' then
            A2 := C;
        end if;
        ---------------------------------------------
        if    Y(11) = '1' then
            A3 := A1 + A2;
        end if;
        ---------------------------------------------
        if    Y(12) = '1' then
            C := A3;
        end if;
        ---------------------------------------------
        if    Y(13) = '1' then
             B  := B(6 downto 0) & '0';   --  shift  B to left
             C  := C(13 downto 0) & '0';  --  shift  C to left
        end if;
        ---------------------------------------------
        if    Y(14) = '1' then
            if Sk > 0 then
                Sk  := Sk - 1;   --  decrement Sk
                X(2) <= '1';
            else
                X(2) <= '0';
            end if;
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(15) = '1' then
            C := C(14) & C(14 downto 1);   -- C pastumia per vienu i desine
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(16) = '1' then
            X(1) <= C(14); -- ar negiamas C? jei ne, tai i Y(17)
        end if;
        ---------------------------------------------
        if    Y(17) = '1' then
            Rez <= C;
        end if;
        ---------------------------------------------

        ---------------------------------------------
        -- pavertimas atgal i tiesiogini
        if    Y(18) = '1' then
            C1(13 downto 0) := C(13 downto 0);
        end if;
        ---------------------------------------------
        if    Y(19) = '1' then
            C2(13 downto 0) := not C1(13 downto 0) + 1;
        end if;
        ---------------------------------------------
        if    Y(20) = '1' then
            C(13 downto 0) := C2(13 downto 0);
        end if;
        ---------------------------------------------


        ---------------------------------------------
        if    Y(24) = '1' then
            assert 1 = 0 report "Modeliavimas baigtas" severity failure;
        end if;
        ------------------------------------------------------------
  end if;
end process;
end ALU;

-- ALU

--////////////////////////////////////////////////////////////////////////////////////////////////////
--Mikroprograminio valdymo itaiso komponentai----------------------------------------------------------------------------------------------------------------------
    -- id1
    --mikrokomandu atmint? MK_ROM,
    --i? kurios pagal suformuot? paskesn?s MK adres? (Next_MK) i?renkama mikrokomanda (Mikrokom);

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MK_ROM is
port( Clock : in  std_logic;
    next_MK : in  std_logic_vector(0 to 3);
   Mikrokom : out std_logic_vector(1 to 30)
    );
end MK_ROM;
--------------------------------------------------------
architecture MK_Atmintis of MK_ROM is

    type MK_Array is array (0 to 30) of std_logic_vector(1 to 30);

    constant Content: MK_Array := (
        -- X(1) = 01 , X(2) = 10
        -- paskutiniai 4 rodo i kur (priekinis adresas nurodo i kur)
    -- ADR                            XX0000
        0 => "100000000000000000000000000001", -- Y(1)
        1 => "010000000000000000000000010010", -- Y(2) jeigu X(1) = 1, keliaujam i 3 adresa, priesingu atveju i 2
        2 => "001000000000000000000000000101", -- Y(3) --> Y(8)
        3 => "000100000000000000000000000100", -- Y(4)
        4 => "000011100000000000000000000101", -- Y(5, 6, 7) pavertimas i papildoma

        5 => "000000010000000000000000010110", -- Y(8) -- tikrinimas ar B(7) = 1
        6 => "000000000000100000000000001000", -- Y(13) -- postumis
        7 => "000000001111000000000000000110", -- Y(9, 10, 11, 12) -- sudetis

        8 => "000000000000010000000000101001", -- Y(14) sk mazinimas
        9 => "000000000000001000000000001011", -- Y(15) postumis atgal vienu
       10 => "000000000000000000000000000101", -- ciklas sk <> 0, griztam i 5 adresa

       11 => "000000000000000100000000011100", -- Y(16) ar C neigiamas
       12 => "000000000000000010000000001110", -- Y(17) reeeez isvedimas
       13 => "000000000000000001110000001100", -- Y(18, 19, 20) pavertimas atgal i tiesiogini
       14 => "000000000000000000000001001110", -- Y(24) stabdis

   OTHERS => "000000000000000000000000000000"
);

begin MK_skaitymas:
    process (Clock, next_MK)
    begin
       if ( Clock'event and Clock = '1' ) then
      Mikrokom <= Content(conv_integer(next_MK));
       end if;
    end process;
end MK_Atmintis;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id2
    --mikrokomandu skirstymo schem? MK_Form,
    --kurioje nauja mikrokomanda (Mikrokom) padalijama ? tris laukus - mikrooperaciju lauk? (Y),
    --login?s s?lygos numerio lauk? (LS) ir adreso lauk? (Addr), skirt? paskesn?s MK adresui formuoti;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity MK_Form is
port (
   Mikrokom : in  std_logic_vector(1 to 30);
    Y   : out std_logic_vector(1 to 24);
    LS  : out std_logic_vector(0 to 1);
    Addr    : out std_logic_vector(0 to 3)
       );
end  MK_Form;
-------------------------------------------------------------
architecture Skirstymas of  MK_Form is
begin
       Y    <= Mikrokom(1 to 24);
       LS   <= Mikrokom(25 to 26);
       Addr <= Mikrokom(27 to 30);
end Skirstymas;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id3
    --paskesn?s mikrokomandos adreso formavimo schem? MK_AR_Form,
    --kuri pagal mikrokomandoje esan?i? informacij? (LS, Addr) ir (jei to reikia) tikrinamos
    --login?s s?lygos (LS_Values) reik?me formuoja paskesn?s MK adres? (next_MKAdr);

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity MK_AR_Form is
port(    LS : in  std_logic_vector(0 to 1);
   LS_values    : in  std_logic_vector(1 to 2);
        Addr    : in  std_logic_vector(0 to 3);
    next_Adr    : out std_logic_vector(0 to 3);
       clock    : in  std_logic
    );
end  MK_AR_Form;
---------------------------------------------------------
architecture Behav of  MK_AR_Form is

begin process (clock)
   variable xx : integer;
begin
     xx := conv_integer(LS);
     if (clock'event and clock='1') then
     if (xx = 0) then
           next_Adr <= Addr;
     elsif (LS_values(xx)='0') then
           next_Adr <= Addr;
     elsif (LS_values(xx)='1') then
           next_Adr <= Addr +'1';
     end if;
     end if;
   end process;
end Behav;

--////////////////////////////////////////////////////////////////////////////////////////////////////
    -- id4
    --mikrokomandos adreso registr? MK_AR, kuriame saugomas i?renkamos mikrokomandos adresas (MK_Addr).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Entity MK_AR is
port (  Clock : in  std_logic;
        Reset : in  std_logic;
   next_MKAdr : in  std_logic_vector(0 to 3);
      MK_Addr : out std_logic_vector(0 to 3)
);
end MK_AR;
------------------------------------------------------------
architecture Behav of MK_AR is
 begin
 process (Reset, clock)
   begin
       if (Reset = '1') then
          MK_Addr <= "0000";
       elsif (clock'event and clock='1') then
             MK_Addr <= next_MKAdr;
       end if;
   end process;
end Behav;


--////////////////////////////////////////////////////////////////////////////////////////////////////
--Mikroprograminio valdymo komponentu apjungimas----------------------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ProgLog_top is
    port(
     sinchr1 : in std_logic;
     sinchr2 : in std_logic;
     sinchr3 : in std_logic;
     sinchr4 : in std_logic;
     prad    : in std_logic;
        Data : in  std_logic_vector( 7 downto 0);  -- operandai
        Res  : out std_logic_vector(14 downto 0)   -- sandauga
     );
end ProgLog_top;

architecture struktura of ProgLog_top is
-------------------------------------------
--- komponentai                          ---
-------------------------------------------
component MK_ROM is
port(  Clock: in std_logic;
    next_MK : in std_logic_vector(0 to 3);
    Mikrokom: out std_logic_vector(1 to 30)
    );
end component;

component MK_AR is
port(   Clock : in std_logic;
        Reset : in std_logic;
   next_MKAdr : in std_logic_vector(0 to 3);
      MK_Addr : out std_logic_vector(0 to 3)
);
end component;

component MK_AR_Form is
port(   LS  : in  std_logic_vector(0 to 1);
  LS_values : in  std_logic_vector(1 to 2);
      Addr  : in  std_logic_vector(0 to 3);
   next_Adr : out std_logic_vector(0 to 3);
      clock : in  std_logic
);
end component;

component MK_Form is
port(
    Mikrokom: in  std_logic_vector(1 to 30);
       Y    : out std_logic_vector(1 to 24);
       LS   : out std_logic_vector(0 to 1);
       Addr : out std_logic_vector(0 to 3)
);
end component;

component operacinis is
port(   Y   : in std_logic_vector(1 to 24);
    clock   :   in  std_logic;
    reset   :   in  std_logic;
        X   :   out std_logic_vector(1 to 2);
    Duom    :   in  std_logic_vector( 7 downto 0) := "00000000";
      Rez   :   out std_logic_vector(14 downto 0)
  );
end component;


-------------------------------------------
--- Sujungimams                         ---
-------------------------------------------
signal logsnr   :   std_logic_vector(0 to 1);  -- log. sal. nr.
signal log_sal  :   std_logic_vector(1 to 2);  -- logines salygos
signal mops     :   std_logic_vector(1 to 24); -- mikrooperacijos
signal mk       :   std_logic_vector(1 to 30); -- mikrokomanda
signal mkad1    :   std_logic_vector(0 to 3);  -- MK adresas
signal mkad2    :   std_logic_vector(0 to 3);  -- MK adresas
signal mkad3    :   std_logic_vector(0 to 3);  -- MK adresas

begin

ALU1: operacinis port map (
    Y       => mops,
    clock => sinchr3,
    reset => prad,
    X     => log_sal,
    Duom  => Data,
    Rez   => Res
   );

Vald1: MK_ROM port map(
      Clock => sinchr2,
    next_MK => mkad1,
    Mikrokom => mk
    );

Vald2: MK_AR port map(
      Clock => sinchr1,
      Reset => prad,
    next_MKAdr=> mkad3,
    MK_Addr => mkad1
    );

Vald3: MK_AR_Form port map (
    LS  => logsnr,
    LS_values=> log_sal,
    Addr    => mkad2,
    next_Adr    => mkad3,
    clock   => sinchr4
);

  Vald4: MK_Form port map (
    Mikrokom    => mk,
    Y       => mops,
    LS  => logsnr,
    Addr    => mkad2
);
end struktura;