library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;

entity guess_game is
port(inputs : in std_logic_vector(7 downto 0);
set : in std_logic; -- Set predefined value
show : in std_logic; -- Show predefined value
try : in std_logic; -- Evaluate guess
hex1 : out std_logic_vector(6 downto 0); -- 7-seg ones
hex10: out std_logic_vector(6 downto 0) -- 7-seg tens
);
end;

architecture guess_game_arc of guess_game is
signal activate: std_logic_vector(1 downto 0); --All the signals between all the entities.
signal secretvalue,mux_t: std_logic_vector(7 downto 0);
signal sigmux: std_logic_vector(13 downto 0);
begin
k1: entity work.latch_a port map(output => secretvalue , set => set , input => inputs);
k2: entity work.compare_logic port map(try=>try , result => secretvalue, mux_act=> activate, guess => inputs);
k3: entity work.mux port map(show=>show, input=>inputs, secret => secretvalue, show_output=>mux_t);
k4: entity work.bintohex port map(bin=>mux_t(3 downto 0), Sseg=>sigmux(13 downto 7));
k5: entity work.bintohex port map(bin=>mux_t(7 downto 4), Sseg=>sigmux(6 downto 0));
k6: entity work.muxto port map(muxout(13 downto 7) => hex10, muxout(6 downto 0) => hex1, activate => activate, muxin => sigmux);
end;