-- Łukasz Lech
-- 243 265
-- Serializer 8-bit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity serializer is

    port(
        RESET, CLK : in std_logic;
        WE : in std_logic_vector(7 downto 0);
        WY : out std_logic
    );

end entity serializer;


architecture serial_arch of serializer is

signal counter : std_logic_vector(2 downto 0) := "000";
signal enable : std_logic := '0';
signal reg : std_logic_vector(7 downto 0) := "00000000";

begin

    licznik: process(RESET, CLK)
    begin
        if(RESET = '0') then
            counter <= (others => '0');
        elsif(CLK'event and CLK = '1') then
            counter <= counter + 1;
        end if;
    end process licznik;

    enable_reg : process(counter, RESET)
    begin
        if(RESET = '1' and counter = "000") then
            enable <= '1';
        else
            enable <= '0';
        end if;
    end process enable_reg;

    regIsEnabled : process(enable, CLK, RESET)
    begin
        if(enable = '1') then
            reg(0) <= WE(7);
            reg(1) <= WE(6);
            reg(2) <= WE(5);
            reg(3) <= WE(4);
            reg(4) <= WE(3);
            reg(5) <= WE(2);
            reg(6) <= WE(1);
            reg(7) <= WE(0);
        end if;

        if(RESET = '0') then
            reg <= (others => '0');
        elsif(CLK'event and CLK = '1') then
            reg <= '0' & reg(7 downto 1);
        end if;
    end process regIsEnabled;

    WY <= reg(0);

end architecture serial_arch;