4_1_tb

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY lab4_1_tb IS
END lab4_1_tb;

ARCHITECTURE behavior OF lab4_1_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT lab4_1
    PORT(
         Syg : IN  std_logic;
         Sel : IN  std_logic_vector(1 downto 0);
         A : OUT  std_logic;
         B : OUT  std_logic;
         C : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal Syg : std_logic := '0';
   signal Sel : std_logic_vector(1 downto 0) := (others => '0');

    --Outputs
   signal A : std_logic;
   signal B : std_logic;
   signal C : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: lab4_1 PORT MAP (
          Syg => Syg,
          Sel => Sel,
          A => A,
          B => B,
          C => C
        );


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
        Syg<='1';
        Sel<="00"; wait for 100 ns;
        Sel<="01"; wait for 100 ns;
        Sel<="10"; wait for 100 ns;
        Sel<="11"; wait for 100 ns;
      -- insert stimulus here

      wait;
   end process;

END;