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xmega_a4u.c

a guest Mar 4th, 2016 117 Never
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  1. #include "xmega_a4u.h"
  2.  
  3. uint8_t ReadCalibrationByte( uint8_t index ){
  4.     uint8_t result;
  5.  
  6.     /* Load the NVM Command register to read the calibration row. */
  7.     NVM_CMD = NVM_CMD_READ_CALIB_ROW_gc;
  8.     result = pgm_read_byte(index);
  9.  
  10.     /* Clean up NVM Command register. */
  11.     NVM_CMD = NVM_CMD_NO_OPERATION_gc;
  12.  
  13.     return( result );
  14. }
  15.  
  16. void cal_dac(uint8_t ch0gc, uint8_t ch0oc, uint8_t ch1gc, uint8_t ch1oc)
  17. {
  18.   DACB.CH0GAINCAL = ch0gc;
  19.   DACB.CH0OFFSETCAL= ch0oc;
  20.   DACB.CH1GAINCAL = ch1gc;
  21.   DACB.CH1OFFSETCAL= ch1oc;
  22. }
  23.  
  24. void cal_adc(void)
  25. {
  26.   ADCA.CALL = ReadCalibrationByte( offsetof(NVM_PROD_SIGNATURES_t, ADCACAL0) );
  27.   ADCA.CALH = ReadCalibrationByte( offsetof(NVM_PROD_SIGNATURES_t, ADCACAL1) );
  28. }
  29.  
  30. void setup_clk_1M_int(void)
  31. {
  32.    //setup clock
  33.   CCP = CCP_IOREG_gc;
  34.   OSC.CTRL |= OSC_RC2MEN_bm;
  35.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  36.  
  37.   CCP = CCP_IOREG_gc;
  38.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | OSC_PLLDIV_bm;
  39.  
  40.   CCP = CCP_IOREG_gc;
  41.   OSC.CTRL |= OSC_PLLEN_bm;
  42.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  43.    
  44.   CCP = CCP_IOREG_gc;  
  45.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  46.  
  47.   CCP = CCP_IOREG_gc;
  48.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  49.  
  50.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  51.  
  52. }
  53.  
  54. void setup_clk_2M_int(void)
  55. {
  56.    //setup clock
  57.   CCP = CCP_IOREG_gc;
  58.   OSC.CTRL |= OSC_RC2MEN_bm;
  59.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  60.  
  61.   CCP = CCP_IOREG_gc;
  62.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 1);
  63.  
  64.   CCP = CCP_IOREG_gc;
  65.   OSC.CTRL |= OSC_PLLEN_bm;
  66.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  67.    
  68.   CCP = CCP_IOREG_gc;  
  69.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  70.  
  71.   CCP = CCP_IOREG_gc;
  72.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  73.  
  74.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  75.  
  76. }
  77.  
  78. void setup_clk_4M_int(void)
  79. {
  80.    //setup clock
  81.   CCP = CCP_IOREG_gc;
  82.   OSC.CTRL |= OSC_RC2MEN_bm;
  83.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  84.  
  85.   CCP = CCP_IOREG_gc;
  86.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 2);
  87.  
  88.   CCP = CCP_IOREG_gc;
  89.   OSC.CTRL |= OSC_PLLEN_bm;
  90.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  91.    
  92.   CCP = CCP_IOREG_gc;  
  93.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  94.  
  95.   CCP = CCP_IOREG_gc;
  96.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  97.  
  98.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  99.  
  100. }
  101.  
  102. void setup_clk_8M_int(void)
  103. {
  104.    //setup clock
  105.   CCP = CCP_IOREG_gc;
  106.   OSC.CTRL |= OSC_RC2MEN_bm;
  107.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  108.  
  109.   CCP = CCP_IOREG_gc;
  110.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 4);
  111.  
  112.   CCP = CCP_IOREG_gc;
  113.   OSC.CTRL |= OSC_PLLEN_bm;
  114.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  115.    
  116.   CCP = CCP_IOREG_gc;  
  117.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  118.  
  119.   CCP = CCP_IOREG_gc;
  120.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  121.  
  122.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  123.  
  124. }
  125.  
  126. void setup_clk_16M_int(void)
  127. {
  128.    //setup clock
  129.   CCP = CCP_IOREG_gc;
  130.   OSC.CTRL |= OSC_RC2MEN_bm;
  131.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  132.  
  133.   CCP = CCP_IOREG_gc;
  134.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 8);
  135.  
  136.   CCP = CCP_IOREG_gc;
  137.   OSC.CTRL |= OSC_PLLEN_bm;
  138.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  139.    
  140.   CCP = CCP_IOREG_gc;  
  141.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  142.  
  143.   CCP = CCP_IOREG_gc;
  144.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  145.  
  146.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  147.  
  148. }
  149.  
  150. void setup_clk_32M_int(void)
  151. {
  152.    //setup clock
  153.   CCP = CCP_IOREG_gc;
  154.   OSC.CTRL |= OSC_RC2MEN_bm;
  155.   do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
  156.  
  157.   CCP = CCP_IOREG_gc;
  158.   OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 16);
  159.  
  160.   CCP = CCP_IOREG_gc;
  161.   OSC.CTRL |= OSC_PLLEN_bm;
  162.   do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
  163.    
  164.   CCP = CCP_IOREG_gc;  
  165.   CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
  166.  
  167.   CCP = CCP_IOREG_gc;
  168.   CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
  169.  
  170.   OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
  171.  
  172. }
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