Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- #include "xmega_a4u.h"
- uint8_t ReadCalibrationByte( uint8_t index ){
- uint8_t result;
- /* Load the NVM Command register to read the calibration row. */
- NVM_CMD = NVM_CMD_READ_CALIB_ROW_gc;
- result = pgm_read_byte(index);
- /* Clean up NVM Command register. */
- NVM_CMD = NVM_CMD_NO_OPERATION_gc;
- return( result );
- }
- void cal_dac(uint8_t ch0gc, uint8_t ch0oc, uint8_t ch1gc, uint8_t ch1oc)
- {
- DACB.CH0GAINCAL = ch0gc;
- DACB.CH0OFFSETCAL= ch0oc;
- DACB.CH1GAINCAL = ch1gc;
- DACB.CH1OFFSETCAL= ch1oc;
- }
- void cal_adc(void)
- {
- ADCA.CALL = ReadCalibrationByte( offsetof(NVM_PROD_SIGNATURES_t, ADCACAL0) );
- ADCA.CALH = ReadCalibrationByte( offsetof(NVM_PROD_SIGNATURES_t, ADCACAL1) );
- }
- void setup_clk_1M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | OSC_PLLDIV_bm;
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
- void setup_clk_2M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 1);
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
- void setup_clk_4M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 2);
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
- void setup_clk_8M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 4);
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
- void setup_clk_16M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 8);
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
- void setup_clk_32M_int(void)
- {
- //setup clock
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_RC2MEN_bm;
- do {} while( !(OSC.STATUS & OSC_RC2MRDY_bm) );
- CCP = CCP_IOREG_gc;
- OSC.PLLCTRL = OSC_PLLSRC_RC2M_gc | (OSC_PLLFAC_gm & 16);
- CCP = CCP_IOREG_gc;
- OSC.CTRL |= OSC_PLLEN_bm;
- do {} while( !(OSC_STATUS & OSC_PLLRDY_bm) );
- CCP = CCP_IOREG_gc;
- CLK.PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
- CCP = CCP_IOREG_gc;
- CLK.CTRL = CLK_SCLKSEL_gm & CLK_SCLKSEL_PLL_gc;
- OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC32KEN_bm);
- }
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement