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  1. library IEEE;
  2. use IEEE.std_logic_1164.all;
  3. use IEEE.numeric_std.all;
  4.  
  5. entity Ram is
  6. port(writeClk : in std_logic;
  7.       writeEnable : in std_logic;
  8.       writeData : in std_logic_vector(16 downto 0);
  9.       address : in std_logic_vector(5 downto 0);
  10.      readData : out std_logic_vector(16 downto 0));
  11. end Ram;
  12.  
  13. architecture Behavioral of Ram is
  14. constant NUM_WORDS : integer := 5;
  15. subtype TDataWord is std_logic_vector(16 downto 0);
  16. type TMemory is array (0 to NUM_WORDS-1) of TDataWord;
  17. signal s_memory : TMemory;
  18. begin
  19.     process(writeClk)
  20.     begin
  21.         if (rising_edge(writeClk)) then
  22.             if (writeEnable = '1') then
  23.                 s_memory(to_integer(unsigned(address))) <= writeData;
  24.             end if;
  25.         end if;
  26.     end process;
  27.     readData <= s_memory(to_integer(unsigned(address)));
  28. end Behavioral;
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