dcfm synchronuos counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c1 is
port(c:in std_logic_vector(3 downto 0);
     clk:in std_logic_vector(0 downto 0);
     q:out std_logic_vector(3 downto 0));
end c1;
architecture bev of c1 is
begin
process(c,clk)
begin
if(clk ="1") then
case c is
when "1111"=>q<= "0000";
when others =>q<= c + "0001";
end case;
end if;
end process;
end bev;