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Oct 11th, 2017
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VHDL 1.17 KB | None | 0 0
  1. #File sistema.vhd
  2.  
  3. entity sistema is
  4.     port(...)
  5. end entity sistema;
  6.  
  7. architecture struct of sistema is
  8.  
  9. component decoder_c is
  10.     port([...])
  11. end component decoder_c;
  12.  
  13. begin
  14.  
  15.     dec: component decoder_c
  16.         port map ([...]);
  17.  
  18. end architecture struct;
  19.  
  20. #File decoder.vhd
  21.  
  22. entity decoder is
  23.     port([...])
  24. end entity decoder;
  25.  
  26. architecture behav of decoder is
  27. [...]
  28. begin
  29. [...]
  30. end architecture behav;
  31.  
  32. architecture struct of decoder is
  33. [...]
  34. begin
  35. [...]
  36. end architecture behav;
  37.  
  38. #File configuration.vhd
  39. -- Per usare l'architettura behav
  40. configuration config of sistema is
  41.     for struct
  42.         for dec:decoder_c
  43.             use entity work.decoder(behav);
  44.         end for;
  45.     end for;
  46. end configuration config;
  47.  
  48. -- Per usare l'architettura struct
  49. configuration config of sistema is
  50.     for struct
  51.         for dec:decoder_c
  52.             use entity work.decoder(struct);
  53.                 for struct
  54.                     for all: nand_port
  55.                         use entity work.nand_porta(behav);
  56.                     end for;
  57.  
  58.                     for all: inverter
  59.                         use entity work.inv_porta(behav);
  60.                     end for;
  61.  
  62.                     for all: and_inv_port
  63.                         use entity work.and_inv_porta(behav);
  64.                     end for;
  65.                 end for;
  66.         end for;
  67.     end for;
  68. end configuration config;
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