UCISW zamek szyfrowy VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity zamek_szyfrowy is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           Z : in  STD_LOGIC;
           Y : out  STD_LOGIC;
              SEG7 : out STD_LOGIC_VECTOR (7 downto 0));
end zamek_szyfrowy;

-- clock, reset oczywiste
-- Z - wejscie
-- Y - wyjscie na diode (zapalenie / zgaszenie)
-- SEG7 - wyjscie na wyswietlacz 7-seg, kazdy stan przedstawia

architecture Behavioral of zamek_szyfrowy is
type state_type is (q0, q1, q2, q3, q4, q5);    -- wszystkie mozliwe stany
signal state, next_state: state_type;   -- deklaracja stanow typu state_type

begin
    clockSet: process (clock, reset)
    begin
        if (reset = '1') then   -- po wcisnieciu przycisku reset
            state <= q0;
        elsif rising_edge(clock) then   -- pojawienie sie narastajacego zbocza fali zegara
            state <= next_state;    -- zmiana stanu na kolejny
        end if;
    end process;

    stateChange: process (state, Z)
    begin
        case state is
            when q0 =>
                if Z ='1' then
                    next_state <= q0;
                else
                    next_state <= q1;
                end if;
            when q1 =>
                if Z ='1' then
                    next_state <= q2;
                else
                    next_state <= q1;
                end if;
            when q2 =>
                if Z ='1' then
                    next_state <= q0;
                else
                    next_state <= q3;
                end if;
            when q3 =>
                if Z ='1' then
                    next_state <= q4;
                else
                    next_state <= q1;
                end if;
            when q4 =>
                if Z ='1' then
                    next_state <= q0;
                else
                    next_state <= q5;
                end if;
            when q5 =>
                if Z ='1' then
                    next_state <= q0;
                else
                    next_state <= q1;
                end if;
        end case;
    end process;

    outputLED: process (state)  -- dioda reprezentujaca wyjscie Y
    begin
        case state is
            when q0 => y <= '1';    -- zgaszona dioda
            when q1 => y <= '1';
            when q2 => y <= '1';
            when q3 => y <= '1';
            when q4 => y <= '1';
            when q5 => y <= '0';    -- zapalona dioda
        end case;
    end process;

    output7SEG: process (state) -- wyswietlacz 7-segmentowny reprezentujacy
    begin                                   -- kolejne stany
        case state is
            when q0 => SEG7 <= "11000000";  -- pgfedbca
            when q1 => SEG7 <= "11111001";
            when q2 => SEG7 <= "10100100";
            when q3 => SEG7 <= "10110000";
            when q4 => SEG7 <= "10011001";
            when q5 => SEG7 <= "10010010";
        end case;
    end process;

end Behavioral;