rom3

----------------------------------------------------------------------------------
-- Logicko projektovanje racunarskih sistema 1
-- 2011/2012
-- Lab 7
--
-- Instruction ROM
--
-- author: Branislav Nikolic, e13592
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity instr_rom is
    Port ( iA : in  STD_LOGIC_VECTOR (4 downto 0);
           oQ : out  STD_LOGIC_VECTOR (14 downto 0));
end instr_rom;

architecture Behavioral of instr_rom is

    -- ALU instructions --
    constant cMOV : std_logic_vector(5 downto 0) := "000000";
    constant cADD : std_logic_vector(5 downto 0) := "000001";
    constant cSUB : std_logic_vector(5 downto 0) := "000010";
    constant cAND : std_logic_vector(5 downto 0) := "000011";
    constant cOR : std_logic_vector(5 downto 0) := "000100";
    constant cNOT : std_logic_vector(5 downto 0) := "000101";
    constant cINC : std_logic_vector(5 downto 0) := "000110";
    constant cDEC : std_logic_vector(5 downto 0) := "000111";
    constant cSHL : std_logic_vector(5 downto 0) := "001000";
    constant cSHR : std_logic_vector(5 downto 0) := "001001";
    constant cASHL : std_logic_vector(5 downto 0) := "001010";
    constant cASHR : std_logic_vector(5 downto 0) := "001011";
    constant cJMP:  std_logic_vector(5 downto 0) :="010000";
    constant cJMPZ:  std_logic_vector(5 downto 0) :="010001";
    constant cJMPS:  std_logic_vector(5 downto 0) :="010010";
    constant cJMC:  std_logic_vector(5 downto 0) :="010011";
    constant cJMPNZ:  std_logic_vector(5 downto 0) :="010101";
    constant cJMPNS:  std_logic_vector(5 downto 0) :="010110";
    constant cJMNC:  std_logic_vector(5 downto 0) :="010111";

    -- Other instructions --
    constant cLD : std_logic_vector(5 downto 0) := "100000";
    constant cST : std_logic_vector(5 downto 0) := "110000";

    -- Registers --
    constant cR0 : std_logic_vector(2 downto 0) := "000";
    constant cR1 : std_logic_vector(2 downto 0) := "001";
    constant cR2 : std_logic_vector(2 downto 0) := "010";
    constant cR3 : std_logic_vector(2 downto 0) := "011";
    constant cR4 : std_logic_vector(2 downto 0) := "100";
    constant cR5 : std_logic_vector(2 downto 0) := "101";
    constant cR6 : std_logic_vector(2 downto 0) := "110";
    constant cR7 : std_logic_vector(2 downto 0) := "111";
    constant cRX : std_logic_vector(2 downto 0) := "---"; -- reg field not used

begin
 process(iA)begin
    case (iA)is

--loopA:
            when "00000"=> oQ<= cLD &cR5 &cRX &cR5;
            when "00001" =>  oQ<= cINC &cR5 &cR5 &cRX;
            when "00010" =>  oQ<= cASHL &cR5 &cR5 &cRX;
            when"00011" =>oQ<= cINC &cR5 &cR5 &cRX; --R5=3=Q

            when"00100" =>oQ<= cDEC &cR5 &cR5 &cRX;
            when "00101" => oQ<= cJMPZ &"000000000";

--loopB:
            when "00110" => oQ<= cLD &cR6 &cRX &cR6;
            when "00111" => oQ<= cINC &cR6 &cR6 &cRX;
            when "01000" => oQ<= cASHL &cR6 &cR6 &cRX; --R6=2=X

            --when "01001"=> oQ<= cLD &cR7 &cRX &cR7;
            when "01001"=>oQ<= cINC &cR7 &cR7 &cRX; --R7=1=C
            when "01010"=> oQ<= cASHL &cR7 &cR7 &cRX;



            when "01011"=>oQ<= cMOV &cR1 &cR6 &cRX; --R1=X=2
            when "01100"=>oQ<= cASHL &cR4 &cR1 &cRX; --R1*2
            when "01101"=>oQ <= cMOV &cR2 &cR4 &cRX; --R2=2*R1
            when "01110"=>oQ<= cDEC &cR7 &cR7 &cRX;
            when "01111" =>     oQ<= cJMPZ &"000010110";
--do_false:
            when "10000" =>oQ<= cASHR &cR2 &cR2 &cRX;
            when "10001" =>oQ<= cASHR &cR2 &cR2 &cRX;
            when "10010"=> oQ<= cDEC &cR2 &cR2 &cRX;
            when "10011"=> oQ<= cDEC &cR2 &cR2 &cRX;
            when "10100"=> oQ<= cMOV &cR3 &cR2 &cRX;
            when "10101"=> oQ<= cJMP &"000000000";
--do_true:
            when "10110"=> oQ<= cINC &cR3 &cR3 &cRX;
            when "10111"=> oQ<= cINC &cR3 &cR3 &cRX;
            when "11000"=> oQ<= cINC &cR3 &cR3 &cRX;
            when "11001"=> oQ<= cASHL &cR3 &cR3 &cRX;
            when "11010"=> oQ<= cASHL &cR3 &cR3 &cRX; --R3=12
            when "11011"=> oQ<= cJMP &"000000110";
    when others => oQ<= (others => '0');

    end case;
end process;

end Behavioral;