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Roniere

Testbench - RAM Memory in VHDL

Aug 18th, 2021
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  1. library IEEE;
  2.     use IEEE.std_logic_1164.all;
  3.     use IEEE.numeric_std.all;
  4.  
  5. entity RAM_Shared_Addr_And_Data_tb is
  6.  
  7. end RAM_Shared_Addr_And_Data_tb;
  8.  
  9. --a arquitetura
  10. architecture behavioral of RAM_Shared_Addr_And_Data_tb is
  11.  
  12.     component RAM_Shared_Addr_And_Data
  13.         generic (
  14.             data_address_size : integer := 8
  15.         );
  16.    
  17.         port(
  18.             clk        : in std_logic;
  19.             rst        : in std_logic;
  20.            
  21.             en_W_R     : in std_logic; -- 1 -> WRITE / 0 -> READ
  22.             en_Out     : in std_logic;
  23.        
  24.             data_address_sel : in std_logic; -- 1 -> DATA / 0 -> ADDRESS
  25.        
  26.             data_address_io : inout std_logic_vector((data_address_size - 1) downto 0)
  27.         );
  28.     end component;
  29.  
  30.     signal rst : std_logic;
  31.     signal clk : std_logic := '0';
  32.     signal en_Out  : std_logic;
  33.     signal en_W_R  : std_logic;
  34.     signal data_address_sel : std_logic;
  35.     signal data_address_io : std_logic_vector(7 downto 0);
  36.  
  37.     constant clk_period : time := 20 ns;
  38.  
  39. begin
  40.  
  41.     clk  <= not clk after 10 ns;
  42.     rst <= '0', '1' after 10 ns;
  43.    
  44.     process
  45.     begin
  46.         --inicio do reset
  47.         data_address_io <= (others=>'Z');
  48.         en_Out  <= '0';
  49.         en_W_R  <= '0';
  50.         data_address_sel <= '0';
  51.         wait until rst = '0';
  52.        
  53.         --espera uma borda para alinhar com o clock e ficar bonito.
  54.         wait until rising_edge(clk);
  55.        
  56.         --escreve no endereço 3, data = A4 (10100100)
  57.         data_address_sel <= '1';
  58.         --data_address_io <= (2 downto 0 => "011", others=>'0');
  59.         data_address_io <= "00000011";
  60.         wait until rising_edge(clk);
  61.         data_address_sel <= '0';
  62.         en_W_R  <= '1';
  63.         data_address_io <= x"A4";
  64.         wait until rising_edge(clk);
  65.        
  66.         --escreve no endereço 4, data = A5 (10100100)
  67.         data_address_sel <= '1';
  68.         --data_address_io <= (2 downto 0 => "100", others=>'0');
  69.         data_address_io <= "00000100";
  70.         wait until rising_edge(clk);
  71.         data_address_sel <= '0';
  72.         en_W_R  <= '1';
  73.         data_address_io <= x"A5";
  74.         wait until rising_edge(clk);
  75.        
  76.         --para garantir, vou zerar todos os controles.
  77.         en_Out  <= '0';
  78.         en_W_R  <= '0';
  79.         data_address_sel <= '0';
  80.         data_address_io <= (others=>'Z');
  81.         wait until rising_edge(clk);
  82.        
  83.         --leitura addr 3
  84.         data_address_sel <= '1';
  85.         --data_address_io <= (2 downto 0 => "011", others=>'0');
  86.         data_address_io <= "00000011";
  87.         wait until rising_edge(clk);
  88.         en_Out  <= '1';
  89.         data_address_io <= (others=>'Z');  
  90.         --data_address_sel <= '0';
  91.         --data_address_io <= (others=>'Z');
  92.         wait until rising_edge(clk);
  93.        
  94.         --leitura addr 4
  95.         data_address_sel <= '1';
  96.         --data_address_io <= (2 downto 0 => "100", others=>'0');
  97.         data_address_io <= "00000100";
  98.         wait until rising_edge(clk);
  99.         en_Out  <= '1';
  100.         data_address_io <= (others=>'Z');
  101.         --data_address_sel <= '0';
  102.         --data_address_io <= (others=>'Z');
  103.         wait until rising_edge(clk);
  104.        
  105.         wait;
  106.     end process;
  107.  
  108.     dut : RAM_Shared_Addr_And_Data
  109.         port map (
  110.             rst => rst,
  111.             clk => clk,
  112.             data_address_io => data_address_io,
  113.             en_Out  => en_Out,
  114.             en_W_R  => en_W_R,
  115.             data_address_sel => data_address_sel
  116.         ); 
  117. end behavioral;
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