Weird FPGA behavior

-- Main.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Main is
    Port(
        BCDInput : in STD_LOGIC_VECTOR(3 downto 0);
        SevenSegment : out STD_LOGIC_VECTOR(6 downto 0);
        SevenSegmentEnable : out STD_LOGIC_VECTOR(2 downto 0)
    );
end Main;

architecture Behavioral of Main is
component bcd_7segment is
Port (
    BCDin : in STD_LOGIC_VECTOR (3 downto 0);
    Seven_Segment : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
begin
bcd_to_7seg: bcd_7segment port map (BCDInput, SevenSegment);
SevenSegmentEnable(0) <= '1'; -- I also tried setting it all at once with "101" and with pre-defined signal, also tried setting only one. Both enable pins and 7Seg pins are active low.
SevenSegmentEnable(1) <= '0';
SevenSegmentEnable(2) <= '1';
end Behavioral;

-- BCD_To_7Seg.vhd - I don't think it matters, but just for sure...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcd_7segment is
Port (
    BCDin : in STD_LOGIC_VECTOR (3 downto 0);
    Seven_Segment : out STD_LOGIC_VECTOR (6 downto 0)
);
end bcd_7segment;

architecture Behavioral of bcd_7segment is

begin

process(BCDin)
begin

case BCDin is
when "0000" =>
Seven_Segment <= "0000001"; ---0
when "0001" =>
Seven_Segment <= "1001111"; ---1
when "0010" =>
Seven_Segment <= "0010010"; ---2
when "0011" =>
Seven_Segment <= "0000110"; ---3
when "0100" =>
Seven_Segment <= "1001100"; ---4
when "0101" =>
Seven_Segment <= "0100100"; ---5
when "0110" =>
Seven_Segment <= "0100000"; ---6
when "0111" =>
Seven_Segment <= "0001111"; ---7
when "1000" =>
Seven_Segment <= "0000000"; ---8
when "1001" =>
Seven_Segment <= "0000100"; ---9
when others =>
Seven_Segment <= "1111111"; ---null
end case;

end process;

end Behavioral;

-- Main.ucf
CONFIG VCCAUX = "3.3" ;

NET "SevenSegmentEnable[2]"           LOC = B3  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegmentEnable[1]"           LOC = A2  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegmentEnable[0]"           LOC = B2  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET "SevenSegment[0]"     LOC = A5  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[1]"     LOC = C6  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[2]"     LOC = D6  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[3]"     LOC = C5  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[4]"     LOC = C4  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[5]"     LOC = A4  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "SevenSegment[6]"     LOC = B4  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;

NET "BCDInput[0]"         LOC = C17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "BCDInput[1]"         LOC = C18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "BCDInput[2]"         LOC = D17  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;
NET "BCDInput[3]"         LOC = D18  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | PULLUP;

-- Board: https://numato.com/product/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram
-- Schematic: https://numato.com/blog/wp-content/uploads/2016/08/MimasV2Sch.pdf