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Nov 21st, 2018
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VHDL 0.37 KB | None | 0 0
  1. Div_decode: process (div_start, input1, outdend, dsor)
  2. begin
  3.     if div_start = '1' then
  4.         inDend <= X"00" & input1; --at first clock when Start = 1, set outDend
  5.         ResLsb <= '0';
  6.     elsif outDend >= Dsor then
  7.         ResLSB <= '1';
  8.         inDend <= outDend - Dsor; --Substract outDend from Dsor and put in inDend
  9.     else
  10.         ResLsb <= '0';
  11.         inDend <= outDend;
  12.     end if;
  13. end process;
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