library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mul4x4 is
    Port ( x0 : in  STD_LOGIC_VECTOR (3 downto 0);
           x1 : in  STD_LOGIC_VECTOR (3 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end mul4x4;

architecture Behavioral of mul4x4 is

component sum8bit is
    Port ( COUT : out  STD_LOGIC;
           CIN : in  STD_LOGIC;
           x0 : in  STD_LOGIC_VECTOR (7 downto 0);
           x1 : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end component;

signal line0:STD_LOGIC_VECTOR (7 downto 0);
signal line1:STD_LOGIC_VECTOR (7 downto 0);
signal line2:STD_LOGIC_VECTOR (7 downto 0);
signal line3:STD_LOGIC_VECTOR (7 downto 0);
signal add0:STD_LOGIC_VECTOR (7 downto 0);
signal add1:STD_LOGIC_VECTOR (7 downto 0);
begin

line0 <= "00000000" when x1(0) = '0' else "0000"&x0;
line1 <= "00000000" when x1(1) = '0' else "000"&x0&"0";
line2 <= "00000000" when x1(2) = '0' else "00"&x0&"00";
line3 <= "00000000" when x1(3) = '0' else "0"&x0&"000";

S80: sum8bit port map (CIN => '0', x0 => line0, x1 => line1, y => add0);
S81: sum8bit port map (CIN => '0', x0 => line2, x1 => line3, y => add1);
S82: sum8bit port map (CIN => '0', x0 => add0, x1 => add1, y => y);


end Behavioral;