library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Ram is
   generic (
        g_ADDR_BITS : natural := 16;
        g_DATA_BITS : natural := 8
    );
    port (
        CLOCK            : in  std_logic;
        WRITE_SIGNAL : in  std_logic;
        WRITE_ADDR   : in  std_logic_vector (g_ADDR_BITS-1 downto 0);
        WRITE_DATA   : in  std_logic_vector (g_DATA_BITS-1 downto 0);

        READ_ADDR    : in  std_logic_vector (g_ADDR_BITS-1 downto 0);
        READ_DATA    : out std_logic_vector (g_DATA_BITS-1 downto 0)
    );
end entity Ram;

architecture RTL of Ram is

    subtype t_Word is std_logic_vector (g_DATA_BITS-1 downto 0);
    type t_BlockMem is array(0 to 2**g_ADDR_BITS-1) of t_Word;

    signal r_Ram : t_BlockMem := (others => (others => '0'));

begin

    p_WriteData : process (CLOCK) is begin
        if rising_edge(CLOCK) then
            if WRITE_SIGNAL = '1' then
                r_Ram(to_integer(unsigned(WRITE_ADDR))) <= WRITE_DATA;
            end if;
        end if;
    end process p_WriteData;

    p_ReadData : process (CLOCK) is begin
        if rising_edge(CLOCK) then
            READ_DATA <= r_Ram(to_integer(unsigned(READ_ADDR)));
        end if;
    end process p_ReadData;

end architecture RTL;